JPH01229348A - Circuit and method for detecting command - Google Patents

Abstract

PURPOSE:To improve the efficiency of communication by discriminating data as a command when a carrier detection signal and the detection signal of data and silent state are sequentially introduced to a command discrimination means. CONSTITUTION:Since a CPU inputs a read signal 1 to one input terminal of a NAND gage 333 in a command discrimination circuit when command reading terminates, the output shows zero. FF331 outputs data 1 from an output terminal Q in accordance with the output of the gate 333 and the fall of a clock. Consequently, '1' is inputted to the terminal 2 of an AND gate 341 and data '0' is outputted from the gate 341. Since a command signal is supplied from the command discrimination circuit to the CPU as long as the state is maintained, the CPU recognizes that received data is that except for the command. The output of data '1' is maintained until the surface of a transmission line comes to a silent state and '0' is supplied from a carrier detection part 311 to the reset terminal of FF331.

Description

[Detailed Description of the Invention] (Table of Contents) (Overview Industrial Field of Application) Conventional Technology Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems, Correspondence between Examples and Figure 1 ■, Structure of the embodiment ■, Operation of the embodiment (i) Initial reset operation (11) Command discrimination operation (iii) Data reception operation ■, Summary of the embodiment %7. Modifications of the invention Effects of the invention () Already Regarding command detection circuits and command detection methods that detect commands sent before data, the first detection is performed by detecting carriers sent via a transmission path, with the aim of increasing communication efficiency. a carrier detection means for outputting a signal; a data detection means for detecting that data is included in the carrier sent via the transmission path and outputting a second detection signal;
A third signal is detected by detecting a no-signal state on the transmission path according to the detection signal.
The device is configured to include a no-signal state detection means for outputting a detection signal, and a command discrimination means for discriminating data as a command when the third detection signal, the first detection signal, and the second detection signal are sequentially introduced. .

[Industrial Application Field] The present invention relates to a command detection circuit and a command detection method that detect a command transmitted before data.

[Prior Art] In normal data communication, it is necessary to determine whether the data being communicated is a command or processing data.

For example, the start focus and stop bits in serial data communication (communication via R3-232C, etc.) recognize the data sandwiched between them.

This is a command for separating.

- In order to separate commands from data and recognize them, there are two ways to do this: ■ Using a specific code exclusively for commands, ■ Providing a signal line to identify whether it is a command or data, or ■ Using data to separate commands from data. Examples include a method of communicating by converting it into characters.

[The problem that the invention tries to solve! By the way, the method (2) described above has a problem in that the degree of freedom is reduced because the codes that can be used as data are limited. For example, data is limited by defining start bits and stop bits. Furthermore, the method (2) has a problem in that the addition of signal lines leads to an increase in cost. The method (2) has the problem that the amount of data required for communication of a predetermined capacity increases and the communication speed decreases. Therefore, when commands are separated from data using the conventional method, there is a problem that communication efficiency deteriorates.

The present invention was created in view of the above points, and an object of the present invention is to provide a command detection circuit and a command detection method that can improve communication efficiency.

[Means to solve the problem]

FIG. 1 is a principle block diagram of a command detection circuit according to the present invention.

In the figure, a carrier detecting means 111 detects a carrier sent through a transmission path and generates a first detection signal 113.
Output.

The data detection means 121 detects that data is included in the carrier sent via the transmission path, and outputs a second detection signal 123.

The no-signal state detection means 131 detects a no-signal state on the transmission path according to the first detection signal 113 and outputs the third detection signal 13.
Outputs 3.

The command determining means 141 receives the third detection signal 133, the first
When the detection signal 113 and the second detection signal 123 are introduced in order, the data is determined as a command.

Therefore, overall, when there is no signal on the transmission path, the system is configured to detect a carrier on the transmission path, further detect that the carrier contains data, and perform command discrimination. There is.

[For production]

Carrier detection means 111 detects carriers sent via the transmission path. A first detection signal 113 is output when a carrier is detected.

The no-signal state detection means 131 is the carrier detection means 111.
When the first detection signal 113 is not supplied from the transmission path, a no-signal state on the transmission path is detected, and the third detection signal 133 is output.

Further, the data detection means 121 detects that data is included in the carrier on the transmission path, and the second detection signal 121 detects that data is included in the carrier on the transmission path.
Outputs 3.

These third detection signals 133. When the first detection signal 113 and the second detection signal 123 are sequentially introduced, the command determining means 141 determines the data as a command.

In the present invention, a no-signal state on the transmission path is detected when the third detection signal 133 is output, carrier detection is further performed in accordance with the first detection signal 113, and the second detection signal 133 is detected.
When it is detected that data is included in the carrier in accordance with No. 23, the command is executed (Embodiment) Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment of the present invention. Also, the third
The figure shows the configuration of a command detection circuit according to an embodiment.

1. Correspondence between the embodiment of the present invention and FIG. 1 will be shown below.

The carrier detection means 111 corresponds to the carrier detection section 311.

The first detection signal 113 corresponds to data output from the carrier detection section 311.

The data detection means 121 includes an R3 type flip-flop (R
3-FF) corresponds to 323.

The second detection signal 123 corresponds to data output from the R3-FF 323.

The no-signal state detection means 131 is a D-type flip-flop (
D-FF) 331.

The third detection signal 133 corresponds to data output from the D-FF 331.

The command determining means 141 corresponds to the AND gate 341.

Examples of the present invention will be described below assuming that the above-mentioned correspondence exists.

-L-1110 Column 1 In Figure 2, the communication system of this embodiment includes a CPU 211 that performs overall control and processes communication data, a receiver 253 that receives signals on the transmission path, and a receiver 253 that sends signals onto the transmission path. The driver 255 that outputs data from the carrier (
a communication circuit 25 that separates the data (including commands) and converts the separated data (serial data) into parallel data 7, or converts the parallel data for transmission into serial data and sends out the serial data;
1, a command discrimination circuit 221 that discriminates commands in received data, a decoder 231 that decodes address data output from the CPU 211 to obtain a control signal, and a reset circuit 241 that initializes the communication system. We are prepared.

Both the input end of the receiver 253 and the output end of the driver 255 are connected to a transmission path, and the output end of the receiver 253 and the input end of the driver 255 are both connected to the communication circuit 251. Further, the output end of the receiver 253 is connected to the command discrimination circuit 221. The communication circuit 251 supplies a full signal (FULL) to the command discrimination circuit 221 when the received serial data reaches a predetermined number of bits.

The CPU 211 has a data bus 291 and an address bus 2.
93, the communication circuit 251 is connected to this data bus 291, and the decoder 231 is connected to this address bus 293.
are connected to each.

Furthermore, a predetermined bit line in the data bus 291 is connected to the command discrimination circuit 221, and a mask signal (MSK) is supplied from the CPU 211 to the command discrimination circuit 221 via this focus line.

The decoder 231 creates a select signal (SEL) based on address data input via the address bus 293 and supplies it to the command discrimination circuit 221.

In addition, the reset circuit (*RESET, * is a symbol indicating a negative logic signal) output from the reset circuit 241 is
2 i i and the command discrimination circuit 221 .

Furthermore, the CPU 211 supplies a read signal (RD) and a write signal (WR) to the command discrimination circuit 221. The command determination circuit 221 sends a command signal to the CPU 21 representing a determination result as to whether or not the received data is a command.
Supply to 1.

FIG. 3 also shows the command discrimination circuit 221 shown in FIG.
The detailed configuration is shown below.

The command discrimination circuit 221 includes a carrier detection section 311 that detects a carrier according to the voltage level at the output terminal of the receiver 253, an R3-FF 323, and two D-FF3.
31, 351, two Nant gates 333, 353, inverter 321, and AND gate 341 (negative input)
It is equipped with

Further, the carrier detection section 311 includes two diodes 36
1,364 and two resistors 362, 365 (resistor 3
62 is the resistance value of resistor 365), and capacitor 363. It is composed of a Schmitt trigger inverter 366 and an inverter 367. R3-FF323
is composed of two nonand gates 325 and 327.

In the carrier detection section 311, the anode side of the diode 361 is connected to the output end of the receiver 253,
The cathode side of the diode 361 is grounded via a resistor 362 and a capacitor 363. Further, the cathode side of the diode 364 is connected to the operating voltage line +VCC, and the anode side of the diode 364 is connected to the resistor 3.
It is grounded via 65. One end of resistor 362 (
capacitor 363 side) and the anode side of diode 364 are connected, and this connection point is connected to R3- through Schmitt trigger inverter 366 and inverter 367.
Connected to FF323.

In R3-FF323, the output terminal of the Nant gate 325 is connected to one input terminal of the Nant gate 327.
The output terminal of 27 is connected to one input terminal of the Nant gate 325. The other input terminal of the Nandt gate 325 is connected to the output terminal of the inverter 367 of the carrier detection section 311.

The other input terminal of the Nant gate 327 is the inverter 321
It is connected to the receiver 253 via the communication circuit 2.
The full signal output from 51 is supplied to R3-FF 323 via this inverter 321. Further, the output terminal of the Nant gate 325 is connected to the first input terminal of the AND gate 341.

One input terminal of each of the Nant gate 333 and the Nant gate 353 is connected to the output terminal of the decoder 231, and a select signal from the decoder 231 is supplied to each. The other input terminal of the Nant gate 333 is CP
It is connected to U211, and the read signal from CPU211 is supplied. The output terminal of the Nant gate 333 is D-
Connected to the clock terminal of FF331.

The other input end of the Nant gate 353 is connected to the CPU 211, and a write signal from the CPU 211 is supplied thereto. The output terminal of the Nant gate 353 is connected to the clock terminal of the D-FF 351.

In the D-FF331, the set terminal 5ET (fl, logic) and the input terminal are connected to the operating voltage line +VCC, the reset terminal R3T (negative logic) is connected to the output terminal of the inverter 367 of the carrier detection section 311, and the output terminal Q is connected to the AND gate. 341, respectively.

In addition, in the D-FF351, the reset terminal R3T (
(negative logic) is connected to the operating voltage line +VCC, and the output terminal Q is connected to the third input terminal of the AND gate 341.

The output terminal of the AND gate 341 is connected to the CPU 211, and a command signal is supplied from the AND gate 341 to the CPU 211.

- Created by the town's most talented Keshi Sugi team Next, the operation of the embodiment of the present invention described above will be explained.

FIG. 4 shows the state on the receiving path, and the receiver 25
We are focusing on the output end of No.3. "State 1" is a no-signal state (
The state in which there is no carrier on the transmission path is called "state 2".
represents a state in which only carriers that do not contain data exist on the transmission path. ji3J each indicates a state in which a carrier containing data exists on the transmission path.

Hereinafter, reference will be made to FIGS. 2 to 4.

1 Prior to the set communication operation, the power switch (
(not shown), an initial reset operation is performed first.

First, when a predetermined period of time has passed after the power switch is turned on, the reset signal "0" supplied from the reset circuit 241 to the D-FF 351 is released, and from then on, data "1" is output from the output terminal Q of the D-FF 351. Ru.

The reset signal supplied to the D-FF351 is the CPU21
1 is also introduced, and the CPU 211 starts operating after a predetermined period of time has elapsed.

Next, the CPU 211 sends a select signal "°1" to the Nant gate 333 and the Nant gate 35 for instructing the command discriminating operation in the command discriminating circuit 221.
3 to one input terminal of the Nant gate 35.
Insert write signal “1” to the other input terminal of D-FF
A mask signal 0' is supplied to the input terminal of 351.

In the Nantes Gate 353, the CPU 211 is connected to the two input terminals.
When a select signal and a write signal are supplied from the output terminal, data "0" is output from the output terminal.

This data "Ooo" is supplied to the clock terminal of the D-FF 351, and the D-FF 351 takes in the mask signal "0" supplied to the input terminal in response to the falling edge of the data supplied from the Nantes gate 353. . From now on, D
Data "0" is output from the output terminal Q of the -FF 351.

j　　Command゛'11 Next, the command determination operation will be explained.

The state of the transmission line after the above-described "(1) initial reset operation" is "state 1" in FIG. 4. At this time, the potential at the input end of the Schmidts +-+-regain converter 366 of the carrier detection unit 311 is at a low level (data “0”).
), and the carrier detection unit 311 outputs data “O
゛ is output.

The output “0” of the carrier detection unit 311 is the output of the D-FF 331.
is supplied to the reset terminal R3T of and the input terminal A of R3-FF323.

In addition, the communication circuit 2 is connected to the input terminal B of R3-FF323.
A full signal output when data is received at 51 is supplied via inverter 321. Immediately after the initial reset, data "1" is supplied to the input terminal B of the R3-FF 323.

Therefore, data "0" is input to one input terminal (carrier detection section 311 side) of the Nant gate 325 of R3-FF323, and data "0" is input to the other input terminal (output terminal side of the Nant gate 327). Nantes Gate 32
Data "1" is output from the output terminal of the Nand gate 325. The output "1" of the Nandt gate 325 is supplied to the first input terminal of the AND gate 341 as the output of the R3-FF 323.

At this time, the data “
0° is supplied to the CPU 211 as a command signal. When the CPU 211 receives the command signal "0", it recognizes that the command is not being received.

Next, when only the carrier is received, the carrier detection unit 31
The potential at the input end of the No. 1 Schmitt trigger inverter 366 becomes high level, and the carrier detection unit 311 outputs data “1P”.

However, there is no change in the data "1" input to the input terminal B of the R3-FF 323, and the state in which data "1" is supplied from the R3-FF 323 to the AND gate 341 is maintained. Recognize that it is not receiving data.

Note that the output “1” of the carrier detection unit 311 is the output of the D-FF 33.
1 reset terminal R3T, thereby D-
The FF 331 becomes operable (data "0°" is output when reset is released).

Next, when a carrier containing data is sent, the communication circuit 251 separates the data (serial data) from the supplied signal. Then, when the data reaches a predetermined bit (for example, 8 bits), a full signal "1" is output.

The full signal output from the communication circuit 251 is input to the input terminal B of the R3-FF 323 via the inverter 321. At this time, data "1P" is input to input terminal A of R3-FF323, and data I to input terminal B is input.
In response to the supply of IOI+, the Nant gate 325 outputs data "0°". This Nantes Gate 325
The output “°0” is supplied to the first input terminal of the AND gate 341 as the output of the R3-FF 323.

At this time, the second input terminal of the AND gate 341 has D-F.
Data “0” from F331 is D-F at the third input terminal.
The data "0" from F351 is supplied respectively, and data "1" is output in response to the data "0"' being supplied to the first input terminal.The output of this AND gate 341 is the command signal P1°. '' is supplied to the CPU 211.

The CPU 211 receives the command signal "1" from the command discrimination circuit 221, and thereafter recognizes n bytes (determined in advance by a communication protocol, etc.) as a command.

iii 8 pieces of data Next, the operation of receiving data excluding commands will be explained.

When the CPU 211 finishes selling three n-byte commands, the CPU 211 sends a read signal "°" to the command discrimination circuit 221.
Outputs 1゛. This read signal is the Nantes gate 333
is input to one input end of the .

Since the select signal "1"" is input to the other input terminal, the Nant gate 333 outputs the data "o".

The D-FF 331 takes in the data ladder "1" supplied to the input terminal in response to the falling edge of the data supplied from the Nant gate 333 to the clock terminal. From then on,
Data “1” is output from the output terminal Q of the D-FF 331.

Therefore, the second input terminal of the AND gate 341 has data "
1" is input, and the AND gate 341 outputs data "
'0pa is output. As long as this state is maintained, the command signal II O11 is supplied from the command discrimination circuit 221 to the CPU 211, so the CPU 211 recognizes that the received data is data other than a command.

Since the input terminal of the D-FF331 is connected to the operating voltage line, there is no signal on the transmission path and data "0" is output from the carrier detection section 311 until the data is supplied to the reset terminal R3T. The output of data "'1pa" is maintained.

■, - Summary of 1 In this way, when the state changes from "state 1" to "state 2" and "state 3" in FIG. is input. At this time, the CPU 211 recognizes the reception of the command, and thereafter receives the n-byte command. Next, when data reception is restarted after being interrupted, the command determination circuit 221 sends a message to the CPU 21! Since the command signal "0" is supplied to the terminal, it is recognized as data other than a command. When the reception of data is completed and the transmission path becomes a no-signal state, the next received data is recognized as a command.

Therefore, communication efficiency can be improved by detecting a state in which only a carrier is received and a state in which data is received from a no-signal state and performing command discrimination.

In particular, conventional transmission lines can be used, and there is no need to use specific code data as commands.
All pattern data can be used as communication data. Further, the command length can be arbitrarily set in advance, and the optimum command length can be determined depending on the communication device.

Incidentally, in the embodiment of the present invention described above, the case where serial data is received has been considered, but the same applies to parallel data. In this case, it is only necessary to change the timing of the full signal output from the communication circuit 251.

In addition, in the embodiment, in order to perform initial reset, D-F
Although the F351 and the Nant gate 353 are provided, they may be omitted to make the cylinder abbreviated.

Furthermore, in "1. Correspondence between Examples and FIG. 1",
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, a no-signal state on the transmission path is detected when the third detection signal is output, and
By performing carrier detection according to the detection signal and performing command discrimination when it is detected that data is included in the carrier according to the second detection signal, communication efficiency can be increased, so it is practical. is extremely useful.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the command detection circuit of the present invention, FIG. 2 is a block diagram of an embodiment to which the command detection circuit and command detection method of the present invention is applied, and FIG. 3 is a diagram of the command discrimination circuit of the embodiment. The detailed configuration diagram, FIG. 4, is an explanatory diagram of command discrimination in the embodiment. In the figure, 111 is a carrier detection means, 113 is a first detection signal, 121 is a data detection means, 123 is a second detection signal, 131 is a no-signal state detection means, 133 is a third detection signal, 141 is a command discrimination means, 211 is CPU. 221 is a command discrimination circuit, 231 is a decoder, 241 is a reset circuit, 251 is a communication circuit, 253 is a receiver, 255 is a driver, 291 is a data bus, 293 is an address bus, 311 is a carrier detection unit, 321.367 is an inverter, 323 is R3-FF, 325.327, 333, 353 is Nantes Gate, 33
1.351 is a D-FF, 361.364 is a diode, 363.365 is a resistor, 363 is a capacitor, and 366 is a Schmitt trigger inverter. To I≦ζ$Aprinciple block diagram of the present invention Figure 1 Configuration diagram of four columns of implementation Figure 2

Claims (2)

[Claims] (1) Carrier detection means (
111), data detection means (121) that detects that data is included in the carrier sent via the transmission path and outputs a second detection signal (123), and the first detection signal (113) for detecting a no-signal state on the transmission path and outputting a third detection signal (133);
133), command determining means (141) for determining the data as a command when the first detection signal (113) and the second detection signal (123) are introduced in sequence;
A command detection circuit comprising: (2) When there is no signal on the transmission path, detect a carrier sent through the transmission path, further detect that the carrier contains data, and use the data as a command. A command detection method characterized by determining.