CN112185452A - High-efficiency self-detection circuit on EEPROM chip - Google Patents

High-efficiency self-detection circuit on EEPROM chip Download PDF

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Publication number
CN112185452A
CN112185452A CN202011039837.9A CN202011039837A CN112185452A CN 112185452 A CN112185452 A CN 112185452A CN 202011039837 A CN202011039837 A CN 202011039837A CN 112185452 A CN112185452 A CN 112185452A
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counter
comparator
output
data
input
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CN202011039837.9A
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孙晓霞
张建伟
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Shanghai Mingsi Microelectronics Co ltd
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Shanghai Mingsi Microelectronics Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

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Abstract

The invention provides a high-efficiency self-detection circuit on an EEPROM chip, which is characterized by comprising: shift register 1, counter 2, comparator 1, flip-flop, comparator 2, counter 3, comparator 3, selector and shift register 2. Write and read requests are sent autonomously to the EEPROM when the digital logic circuit receives a 0x86 command. The upper computer sends a 0x87 command to poll the chip detection state, when the ack is received to be 1, the chip is in the self-detection state, and when the ack is received to be 0, the chip immediately sends 8-bit valid data 0xaa or 0x55 to represent the self-detection result.

Description

High-efficiency self-detection circuit on EEPROM chip
Technical Field
The present invention is in the field of integrated circuit chip design, and more particularly in the field of erasable programmable memory (EEPROM).
Background
Generally, after the wafer is produced, the chip in the front test needs an erase-write test, and after the chip passes the erase-write test, the chip passing the front test is picked up and packaged.
The conventional EEPROM chip consumes a lot of time to test in the front test. For example, based on the IIC protocol, an EEPROM with a capacity of 128K bits, one page is 64 bytes for a capacity of 256 pages, and the fastest test mode is to write 256 pages by using a page write mode and then read the full array by using a sequential read mode. The IIC serial mode consumes a large amount of time, and the time for reading and writing one chip is about 2 hours.
Disclosure of Invention
In order to solve the above problems, the present invention provides a high-efficiency self-test circuit of a chip based on an IIC protocol: after the upper computer sends a command, the chip initiates writing and reading of EEPROM, and after the writing and reading are completed, the chip responds to the confirmation completion of the upper computer. In the set of flow, the chip can complete the full-array data writing only by once erasing; the logic and EEPROM array are based on a 32 bit data operation, and the test time for the read operation is 1/32 the original test time.
The efficient self-detection circuit of the chip is characterized by comprising the following components: shift register 1, counter 2, comparator 1, flip-flop, comparator 2, counter 3, comparator 3, selector and shift register 2.
As shown in fig. 1, the shift register 1 functions to convert the IIC input valid serial data into 8-bit parallel data and output the data of the shift register 1 to the comparator 1. The input of the shift register 1 is data sda _ i of IIC, and the output is data [7:0] connected to the input of the comparator 1.
As shown in fig. 1, the counter 1 is used for counting clocks after the IIC start flag bit, and the count range is 0 to 8, which takes 9 clocks of one byte plus one response ack bit as a period. The input of the counter 1 is the IIC clock upper edge, the count value is output to two paths, one path is connected to the input of the comparator 1, and the other path is connected to the input of the counter 2.
As shown in fig. 1, the counter 2 is used for counting the number of cycles of the counter 1, and when the value of the counter 1 is 8, the counter 2 starts to accumulate; when the IIC start flag is received, the initial value of the counter 2 is set to 0. The input of the counter 2 is the counting value of the counter 1, and the output is connected to the input of the comparator 1.
As shown in fig. 1, the comparator 1 is operative to compare the input data of IIC, the counter 1, the counter 2 and the expected value, and generate corresponding self-test, data and response signals. The inputs of the comparator 1 are the output data [7:0] of the shift register 1, the count value of the counter 2, a fixed value of 0x86 and a fixed value of 0x 87. The 0x86 and 0x87 are IIC command characteristic values. The comparator 1 has three functions. Function 1: when the comparator 1 monitors that the output data of the input shift register 1 is 0x86, the value of the counter 1 is 7, the value of the counter 2 is 1, and the self _ check signal is set to change from 0 to 1 after the three conditions are met, the writing operation of the logic state machine is started, and simultaneously the input signal wt _ all of the EEPROM is enabled to be 1. The self check signal is simultaneously connected to the input of the comparator 3. Function 2: when the comparator 1 monitors that the value of the counter 1 is 7 and the value of the counter 2 is 2, the output data input into the shift register 1 is registered into output check _ data [7:0] after the two conditions are met, and the check _ data [7:0] is connected to an input data signal data _ ee _ i of the EEPROM and used as write data of the EEPROM write operation. The check _ data [7:0] signals are also connected to the inputs of comparator 2. Function 3: when the comparator 1 detects that the output data of the input shift register 1 is 0x87, the value of the counter 1 is 7, the value of the counter 2 is 1, and the response _ en signal is set to change from 0 to 1 when the above three conditions are met, and the response _ en signal is simultaneously connected to the input of the comparator 3.
As shown in FIG. 1, the comparator 2 is used for comparing whether the output data _ ee _ o and check _ data [7:0] of the EEPROM in the reading data phase are equal. The input of the comparator 2 is the output data _ ee _ o of the EEPROM and the output value check _ data of the comparator 1, if the output data of the EEPROM is equal to the IIC receiving value check _ data, 0 is output, otherwise, 1 is output. The output of the comparator 2 is connected to the input of a counter 3.
As shown in fig. 1, the counter 3 functions to count the number of clocks at which the comparator 2 is at a high level. The counter 3 sets an initial value to 0 when receiving the IIC start signal, and accumulates 1 when receiving an output signal of the comparator 2 to 1. The output of the counter 3 is connected to a comparator 3.
As shown in fig. 1, the comparator 3 is operative to detect whether the counter 3 is 0. The inputs of the comparator 3 self _ check, response _ en and the output count value of the counter 3. When self _ check is 0, response _ en is 1, and the output value of the counter 3 is 0, the output signal of the counter 3 is 0. When self _ check is 0, response _ en is 1, and the output value of the counter 3 is not 0, the output signal of the counter 3 is 1. The output signal of the comparator 3 is connected to a selector.
As shown in fig. 1, the selector functions to select a particular value to the output port. The input of the selector is the output of the comparator 3, if 0, the selector outputs 0xaa, otherwise the selector outputs 0x 55. The output value of the selector is connected to the shift register 2.
As shown in fig. 1, the shift register 2 is used to convert parallel data into serial data and output the serial data to IIC sda _ o. The input of the shift register 2 is the output value of the selector 0xaa or 0 xaa.
In the invention, when the self _ check signal is high, a logic write operation is started, the wt _ all signal output by the write operation can complete the erasing and writing of all arrays at one time, and the function can be supported in the test mode of most EEPROM products. After the writing operation is complete, the logic state machine is switched to the reading operation, and the EEPROM input address is started to automatically accumulate until the whole array is read. The self _ check signal is a high-order segment and cannot respond to the IIC command, so when the upper computer sends a 0x87 command, the ack response is always 1, that is, the IIC slave is no response. When the logic state machine completes the write and read operations, the self _ check signal is set to 0. The 0x87 command ack response to be 0 after the self _ check signal is 0, and enables the comparator 3 to start operating after the self _ check signal is 0.
In the present invention, the digital logic circuit autonomously sends write and read requests to the EEPROM after receiving the 0x86 command. The upper computer sends a 0x87 command to poll the chip detection state, when the ack is received to be 1, the chip is in the self-detection state, and when the ack is received to be 0, the chip immediately sends 8-bit valid data 0xaa or 0x55 to represent the self-detection result.
The invention has the following advantages:
1. after the digital logic circuit parses the command, it automatically sends write and read EEPROM requests. The traditional tedious read-write time sequence is replaced.
2. The interface of the digital circuit to the EEPROM is a parallel data process.
And 3, the read-write clock adopted by the EEPROM interface is generally larger than the IIC serial clock.
4. After the upper computer sends the command, the digital logic circuit does not need to return the data read from the EEPROM. Only 1 byte flag bit is required to be returned to the upper computer to tell that the current detection is finished.
5. The command development process of the upper computer is simplified to a great extent, and the error probability is reduced.
It can be seen that the reduction of the overhead of the EEPROM self-test approach of the present invention is apparent. Although this scheme will slightly increase some digital logic resources, it will further highlight its practical value in terms of the precious time cost.
Drawings
Fig. 1 illustrates an efficient self-test circuit on a chip according to an embodiment of the present invention.
Detailed Description
The following describes embodiments of the present apparatus in detail with reference to the drawings.
After the chip is powered on, the logic self-detection state machine is started according to the IIC input command 0x 86. The first step of self-detection is the array full-erasing function, and data set by an upper computer is written in. After erasing, starting the second step, reading the full array function, and comparing the 32-bit data read from each address with the written data. When all the addresses are correct, responding to an input command 0x87 of the upper computer and outputting 0 xaa. When all address comparison fails, responding to an input command 0x87 of the upper computer and outputting 0x 55. If the self-test is not completed, the host computer input command 0x87 is not responded.
As shown in fig. 1, the shift register 1 has data sda _ i of IIC as input, and data [7:0] connected to the input of the comparator 1.
As shown in fig. 1, the input of the counter 1 is the IIC clock rising edge, and outputs the count value to two paths, one path is connected to the input of the comparator 1, and the other path is connected to the input of the counter 2.
As shown in fig. 1, the input of the counter 2 is the count value of the counter 1, and the output is connected to the input of the comparator 1.
As shown in FIG. 1, the inputs of the comparator 1 are the output data [7:0] of the shift register 1, the count value of the counter 2, a fixed value of 0x86 and a fixed value of 0x 87. The 0x86 and 0x87 are IIC command characteristic values. The comparator 1 has three functions. Function 1: when the comparator 1 monitors that the output data of the input shift register 1 is 0x86, the value of the counter 1 is 7, the value of the counter 2 is 1, and the self _ check signal is set to change from 0 to 1 after the three conditions are met, the writing operation of the logic state machine is started, and simultaneously the input signal wt _ all of the EEPROM is enabled to be 1. The self check signal is simultaneously connected to the input of the comparator 3. Function 2: when the comparator 1 monitors that the value of the counter 1 is 7 and the value of the counter 2 is 2, the output data input into the shift register 1 is registered into the check _ data [7:0] after the two conditions are met, and the check _ data [7:0] is connected to the input data signal data _ ee _ i of the EEPROM and used as the write data of the EEPROM write operation. The check _ data [7:0] signals are also connected to the inputs of comparator 2. Function 3: when the comparator 1 detects that the output data of the input shift register 1 is 0x87, the value of the counter 1 is 7, the value of the counter 2 is 1, and the response _ en signal is set to change from 0 to 1 when the above three conditions are met, and the response _ en signal is simultaneously connected to the input of the comparator 3.
As shown in fig. 1, the inputs of the comparator 2 are the output data _ ee _ o of the EEPROM and the output value check _ data of the comparator 1, if the output data of the EEPROM is equal to the IIC received value check _ data, 0 is output, otherwise, 1 is output. The output of the comparator 2 is connected to the input of a counter 3.
As shown in fig. 1, the counter 3 sets an initial value to 0 when receiving the IIC start signal, and increments by 1 when receiving an output signal of the comparator 2 to 1. The output of the counter 3 is connected to a comparator 3.
As shown in fig. 1, the inputs of the comparator 3 self _ check, response _ en and the output count value of the counter 3. When self _ check is 0, response _ en is 1, and the output value of the counter 3 is 0, the output signal of the counter 3 is 0. When self _ check is 0, response _ en is 1, and the output value of the counter 3 is not 0, the output signal of the counter 3 is 1. The output signal of the comparator 3 is connected to a selector.
As shown in fig. 1, the input of the selector is the output of the comparator 3, and if 0, the selector outputs 0xaa, otherwise the selector outputs 0x 55. The output value of the selector is connected to the shift register 2.
As shown in fig. 1, the shift register 2 is used to convert parallel data into serial data and output the serial data to IIC sda _ o. The input of the shift register 2 is the output value of the selector 0xaa or 0 xaa.
In the invention, when the self _ check signal is high, the original write operation of the logic is started, the wt _ all signal output by the write operation can complete the erasing and writing of all arrays at one time, and the function can be supported in most EEPROM products. After the writing operation is complete, the logic state machine transfers to the array reading operation, and starts the EEPROM input address to automatically accumulate until the whole array is read. The self _ check signal is a high-order segment and cannot respond to the IIC command, so when the upper computer sends a 0x87 command, the ack response is always 1, that is, the IIC slave is no response. After the state machine completes the write and read operations described above, the self _ check signal is set to 0. The 0x87 command ack response to be 0 after the self _ check signal is 0, and enables the comparator 3 to start operating after the self _ check signal is 0.
In the present invention, the digital logic circuit autonomously sends write and read requests to the EEPROM after receiving the 0x86 command. The upper computer sends a 0x87 command to poll the chip detection state, when ack is received to be 1, the chip is in the self-detection state, and when ack is received to be 0, the chip immediately sends 8-bit valid data to represent the self-detection result.
While the present invention has been described in detail with respect to the preferred embodiments thereof, it will be apparent that various modifications and alternatives thereto will become apparent to those skilled in the art upon reading the foregoing description. The above description and drawings are only examples of the practice of the invention, and it should be understood that the above description is not to be taken as limiting the invention.

Claims (1)

1. An efficient self-test circuit on an EEPROM chip, comprising: shift register 1, counter 2, comparator 1, flip-flop, comparator 2, counter 3, comparator 3, selector and shift register 2. The shift register 1 functions to convert the IIC input valid serial data into 8-bit parallel data and output the data of the shift register 1 to the comparator 1. The input of the shift register 1 is data sda _ i of IIC, and the output is data [7:0] connected to the input of the comparator 1. The counter 1 is used for counting clocks after the IIC start flag bit, 9 clocks which are formed by adding one byte and one response ack bit are used as periods, and the counting range is 0-8. The input of the counter 1 is the IIC clock upper edge, the count value is output to two paths, one path is connected to the input of the comparator 1, and the other path is connected to the input of the counter 2. The counter 2 is used for calculating the period number of the counter 1, and when the value of the counter 1 is 8, the counter 2 starts to accumulate; when the IIC start flag is received, the initial value of the counter 2 is set to 0. The input of the counter 2 is the counting value of the counter 1, and the output is connected to the input of the comparator 1. The comparator 1 is used for comparing the input data of the IIC, the counter 1, the counter 2 and the expected value to generate corresponding self-test signals, data and response signals. The inputs of the comparator 1 are the output data [7:0] of the shift register 1, the count value of the counter 2, a fixed value of 0x86 and a fixed value of 0x 87. The 0x86 and 0x87 are IIC command characteristic values. The comparator 1 has three functions. Function 1: when the comparator 1 monitors that the output data of the input shift register 1 is 0x86, the value of the counter 1 is 7, the value of the counter 2 is 1, and the self _ check signal is set to change from 0 to 1 after the three conditions are met, the writing operation of the logic state machine is started, and simultaneously the input signal wt _ all of the EEPROM is enabled to be 1. The self check signal is simultaneously connected to the input of the comparator 3. Function 2: when the comparator 1 monitors that the value of the counter 1 is 7 and the value of the counter 2 is 2, the output data input into the shift register 1 is registered into output check _ data [7:0] after the two conditions are met, and the check _ data [7:0] is connected to an input data signal data _ ee _ i of the EEPROM and used as write data of the EEPROM write operation. The check _ data [7:0] signals are also connected to the inputs of comparator 2. Function 3: when the comparator 1 detects that the output data of the input shift register 1 is 0x87, the value of the counter 1 is 7, the value of the counter 2 is 1, and the response _ en signal is set to change from 0 to 1 when the above three conditions are met, and the response _ en signal is simultaneously connected to the input of the comparator 3. The comparator 2 is used for comparing whether the output data _ ee _ o and check _ data [7:0] of the EEPROM in the data reading phase are equal or not. The input of the comparator 2 is the output data _ ee _ o of the EEPROM and the output value check _ data of the comparator 1, if the output data of the EEPROM is equal to the IIC receiving value check _ data, 0 is output, otherwise, 1 is output. The output of the comparator 2 is connected to the input of a counter 3. The counter 3 functions to count the number of clocks that the comparator 2 is high. The counter 3 sets an initial value to 0 when receiving the IIC start signal, and accumulates 1 when receiving an output signal of the comparator 2 to 1. The output of the counter 3 is connected to a comparator 3. The function of the comparator 3 is to detect whether the counter 3 is 0. The inputs of the comparator 3 self _ check, response _ en and the output count value of the counter 3. When self _ check is 0, response _ en is 1, and the output value of the counter 3 is 0, the output signal of the counter 3 is 0. When self _ check is 0, response _ en is 1, and the output value of the counter 3 is not 0, the output signal of the counter 3 is 1. The output signal of the comparator 3 is connected to a selector. The selector functions to select a particular value to the output port. The input of the selector is the output of the comparator 3, if 0, the selector outputs 0xaa, otherwise the selector outputs 0x 55. The output value of the selector is connected to the shift register 2. The function of the shift register 2 is to convert the parallel data into serial data, and output the serial data to IIC sda _ o. The input of the shift register 2 is the output value of the selector 0xaa or 0 xaa. The self-detection circuit is characterized in that when the self _ check signal is high, a logic write operation is started, the wt _ all signal output by the write operation can erase and write all arrays at one time, and the function can be supported in the test mode of most EEPROM products. After the writing operation is complete, the logic state machine is switched to the reading operation, and the EEPROM input address is started to automatically accumulate until the whole array is read. The self _ check signal is a high-order segment and cannot respond to the IIC command, so when the upper computer sends a 0x87 command, the ack response is always 1, that is, the IIC slave is no response. When the logic state machine completes the write and read operations, the self _ check signal is set to 0. The 0x87 command ack response to be 0 after the self _ check signal is 0, and enables the comparator 3 to start operating after the self _ check signal is 0. The self-detection circuit and the digital logic circuit autonomously send write and read requests to the EEPROM after receiving the 0x86 command. The upper computer sends a 0x87 command to poll the chip detection state, when the ack is received to be 1, the chip is in the self-detection state, and when the ack is received to be 0, the chip immediately sends 8-bit valid data 0xaa or 0x55 to represent the self-detection result.
CN202011039837.9A 2020-09-29 2020-09-29 High-efficiency self-detection circuit on EEPROM chip Withdrawn CN112185452A (en)

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