CN216352286U - Detection apparatus for I2C bus - Google Patents
Detection apparatus for I2C bus Download PDFInfo
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Abstract
The utility model discloses a detection device of an I2C bus, wherein the device comprises: a bus state detection module; a counter; a register group; a data serial-parallel conversion module; an address comparison module; the bus state detection module is connected with the counter, the counter is connected with the data serial-parallel conversion module, the data serial-parallel conversion module is connected with the register bank, and the address comparison module is connected with the register bank. The device and the method are built by adopting a gate-level circuit, so that the area of the circuit can be reduced, and the performance of a chip in unit area is improved. The device method has no system clock and is designed for an asynchronous circuit, so that the compatibility of the module can be improved.
Description
Technical Field
The utility model relates to the technical field of chip detection, in particular to a detection device for an I2C bus.
Background
The market puts increasing demands on the function and performance of the chip, so in order to better control the functional characteristics of the chip and improve the flexibility of the chip, a plurality of corresponding registers are needed to carry out relevant configuration on the chip function, and in order to improve the system stability and reduce the cost, a chip peripheral circuit which is as simple as possible is also required. To maintain good compatibility, these registers are typically configured through the PHILIPS I2C interface. However, the above prior art has the following technical problems: chip configuration mostly uses a synchronous design, compatibility is not strong, and requirements for mobile equipment and video monitoring equipment with high power consumption area are not ideal.
SUMMERY OF THE UTILITY MODEL
One of the purposes of the utility model is to provide a detection device for an I2C bus, which is built by adopting a gate-level circuit, can reduce the area of the circuit and improve the performance of a chip in unit area.
Another object of the present invention is to provide a device for detecting I2C bus, which has no system clock and is designed for asynchronous circuit, and can improve the compatibility of the module.
Another object of the present invention is to provide a device for detecting an I2C bus, which can reduce the total power consumption of a chip on the basis of reducing the circuit area, and can improve the cruising ability after being applied to a mobile device.
To achieve at least one of the above objects, the present invention further provides a device for detecting I2C bus, the device comprising:
a bus state detection module;
a counter;
a register group;
a data conversion module;
an address comparison module;
the bus state detection module is connected with the counter, the counter is connected with the data conversion module, the data conversion module is connected with the register bank, and the address comparison module is connected with the register bank.
According to a preferred embodiment of the present invention, the data conversion module includes an input data serial-to-parallel conversion module and an output data parallel-to-serial conversion module, and the register set includes a first output terminal and a second output terminal, wherein the first output terminal is connected to the input data serial-to-parallel conversion module, and the second output terminal is connected to the output data parallel-to-serial conversion module.
According to another preferred embodiment of the present invention, the address comparison module includes a slave address comparison module and an on-chip address selection module, wherein the input data serial-parallel conversion module is connected to the slave address comparison module, the slave address comparison module is connected to the on-chip address selection module, and the on-chip address selection module is connected to the register set.
According to another preferred embodiment of the present invention, the apparatus comprises a data input interface, a clock input interface and a data output interface, and the counter is a memory with 8 bits, wherein the data input interface is respectively disposed on the bus state detection module, the input data serial-parallel conversion module and the address comparison module.
According to another preferred embodiment of the present invention, the apparatus includes a data output line enable interface and a reset interface, wherein the data output line enable interface is disposed at the output data parallel-to-serial conversion module, and the reset interface is disposed at the bus state detection module.
According to another preferred embodiment of the present invention, the register set comprises 9 registers, wherein the 9 registers are configured as 8-bit registers,
according to another preferred embodiment of the present invention, the counter includes a clock signal output interface, and the clock signal output interface is respectively connected to the input data serial-to-parallel conversion module, the output data parallel-to-serial conversion module, and the address comparison module.
According to another preferred embodiment of the present invention, the bus state detection module includes a clock signal enable interface, and the clock signal enable interface is connected to the counter.
According to another preferred embodiment of the present invention, the bus state detection module comprises a signal start interface and a signal stop interface, wherein the signal start interface and the signal stop interface are respectively connected to the counter.
In order to achieve at least one of the above objects of the present invention, the present invention further provides a method for detecting an I2C bus, including:
the bus state detection module samples a D trigger of an input clock signal for a falling edge of an input data signal to generate a first detection signal;
sampling the first detection signal at the rising edge of a clock signal to generate a second detection signal, and carrying out phase comparison on the inverted signal phase of the first detection signal and the inverted signal phase of the second detection signal to generate an initial detection signal;
the clock output signal counts and outputs according to the clock period of the clock SCL;
the reset signal and the reset error signal asynchronously clear the count when being pulled up;
or when the count enable signal is high and the reference signal is high and the address comparison fails, the count is synchronously cleared.
According to a preferred embodiment of the present invention, the input deserializing module includes a shift register, when the count enable signal is high, the serial data is stored in the input deserializing module through the data input interface, and when the count value is 8, the stored 8-bit serial data and the slave address of the host are added by 1 bit for comparison, a response signal is replied if the comparison is successful, a non-response signal is replied if the comparison is failed, and the host executes the communication and non-communication commands according to the response signal and the non-response signal, respectively.
The present invention further provides a computer-readable storage medium storing a computer program executable by a processor to perform the method for detecting an I2C bus.
Drawings
Fig. 1 is a schematic structural diagram of a detection apparatus for an I2C bus according to the present invention.
Fig. 2 is a schematic structural diagram of a bus detection module according to the present invention.
Fig. 3 shows a schematic diagram of the structure of the counter according to the present invention.
Fig. 4 is a schematic diagram showing an interface of the input data serial-to-parallel conversion module according to the present invention.
Fig. 5 is a schematic interface diagram of the parallel-to-serial conversion module for outputting data according to the present invention.
FIG. 6 is a schematic diagram of an interface of an address comparison module according to the present invention.
Fig. 7 is a schematic flow chart showing a detection method of a detection apparatus based on an I2C bus according to the present invention.
Detailed Description
The following description is presented to disclose the utility model so as to enable any person skilled in the art to practice the utility model. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the utility model, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the utility model.
It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.
Referring to fig. 1-7, the present invention discloses a device for detecting I2C bus, wherein the device includes the following components: the bus state detection module is connected with a corresponding I2C bus and used for detecting signals related to an I2C bus, the bus state detection module is connected with the counter, the counter comprises an SCL clock and counts according to the period of the SCL clock, the counter is connected with the data conversion module, the data conversion module comprises an input data serial-parallel conversion module and an output data serial-parallel conversion module, the counter is connected with the input data serial-parallel conversion module, the register comprises a first output interface and a second output interface, the first output interface is connected with the input data serial-parallel conversion module, the second output interface is connected with the output data serial-parallel conversion module, and the address comparison module comprises a slave address comparison module and an off-chip address selection module, the input data serial-parallel conversion module is connected with the slave address comparison module, the slave address comparison and conversion module is connected with the off-chip address selection module, the off-chip address selection module is provided with an output end, and the output end of the off-chip address selection module is connected with the register set.
Referring to fig. 2 specifically, the present invention discloses an interface schematic diagram of the bus state detection module, wherein the bus state detection module is connected to an i _ scl signal line, and the i _ scl signal line is connected to a clock interface of the bus state detection module and is used for inputting a clock signal (i _ scl); the bus state detection module is further connected with an i _ sda signal line, wherein the i _ sda signal line is connected with a data input interface of the bus state detection module and is used for acquiring a data input signal (i _ sda), an output end of the bus state detection module comprises a start signal interface for outputting a start signal (start), the bus state detection module comprises a reference signal interface for outputting a reference signal (rs), the bus state detection module comprises an error reference signal interface for outputting an error reference signal (rs _ error), the bus state detection module comprises a stop signal interface and a count signal enable interface, the stop signal interface is used for generating a stop signal (stop), and the count signal enable interface is used for generating a count enable signal (cnt _ en). It should be noted that the bus state detection module may include, but is not limited to, a single chip microcomputer, and the above functions may be implemented through different interfaces and logic settings, which are not described in detail herein.
The bus state detection module is connected to the counter, please refer to fig. 3, an input end of the counter includes a start signal interface, a stop signal interface, an error reference signal interface, and a count enable interface, which are respectively connected to the start signal interface, the stop signal interface, the error reference signal interface, and the count enable interface corresponding to an output end of the bus state detection module, and an output end of the counter includes: a count signal output interface for outputting a count signal (cnt _ scl), wherein the counter comprises a shift register, the shift register.
Referring to fig. 4, the counter is connected to the input data serial-to-parallel conversion module, wherein the input end of the input data serial-to-parallel conversion module includes a counting signal input interface, the counting signal input interface is connected to the counting signal output interface of the counter and is configured to obtain a counting signal (cnt _ scl), the input end of the input data serial-to-parallel conversion module further includes a data input interface, the data input interface of the input data serial-to-parallel conversion module is connected to the register set and is configured to obtain a data input signal (i _ sda) in the register set, and the input data serial-to-parallel conversion module further includes a clock interface, the clock interface is connected to the register set and is configured to obtain an input clock signal (i _ scl) in the register set. The output end of the input data serial-parallel conversion module comprises: the input end of the address comparison module further comprises a data signal input interface and a clock signal input interface which are respectively used for acquiring external data input signals and clock signals, and the address comparison module further comprises a reference signal input interface which is used for acquiring reference signals of the storage register. The address comparison module comprises an address matching output interface for outputting an address matching signal (match/rd _ match). Wherein the output data parallel-serial conversion module is connected with the register group, and the input end of the output data parallel-serial conversion module comprises: the counting signal input interface, the parallel data input interface, the clock signal input interface and the address matching signal input interface respectively receive a counting signal (cnt _ scl), parallel data (reg _ data), a clock signal (i _ scl) and an address matching signal (match/rd _ match), and the input end signal of the output data parallel-serial conversion module is obtained from a register group. The output end of the output data parallel-serial conversion module comprises a data output interface and an output data line enabling interface, and the data output interface and the output data line enabling interface are respectively used for externally forming a data output signal (o _ sda) and generating an enabling signal (o _ sda _ en) of output data.
In order to better explain the utility model, the utility model further provides the following specific detection method of the I2C bus on the basis of the detection device of the I2C bus:
the start signal start _ cnd0 is detected by a D flip-flop sampling i _ scl on the i _ sda falling edge, sampling start _ cd0 on the i _ scl rising edge resulting in the start _ cnd1 signal. The inverse phase of the start _ cnd0 signal and the start _ cnd1 signal forms a start pulse signal, which is the actual circuit start signal. The cnt _ en signal will pull high when the i _ scl falling edge detects the start signal high and will reset asynchronously when the stop signal is high. After cnt _ en is pulled high, cnt _ SCL will count SCL clock cycles on the rising edge of i _ SCL until cnt _ en is low and the count value is asynchronously cleared after rs _ error and stop signals are pulled high. The shift register in the input deserializing unit stores the serial data of the i _ sda line when cnt _ en is high, and when cnt _ scl is 8, the stored 8-bit data is compared with the own 7-bit slave address plus 1-bit write (low), o _ sda _ en is pulled high by the o _ sda enable signal, o _ sda outputs the opposite value of the comparison result, i.e. successfully pulled low o _ sda, and failed pulled high o _ sda, thereby replying a response signal ACK or a non-response signal NACK. The upper 8-bit and lower 8-bit addresses of the internal register are compared when cnt _ scl is 17 and 26, respectively. And after response, if the rs signal is not pulled high, the rs signal is read, and the rs signal detection method is consistent with the start signal, but asynchronous zero clearing is carried out until stop is high. In a read operation, the count of 35 is the value of the selected register to be written into the shift register 0 at this time, after the response signal is replied, the host sends a stop signal stop to complete the register configuration, the stop signal i _ sda signal rises to sample i _ scl, and the start signal is asynchronously cleared when pulled high. If rs is high, the data in the shift register 0 is compared when cnt _ scl counts to 36, the comparison value is the read (high) of adding 1 bit to the own slave address, if the comparison is successful, the 8-bit data of the selected configuration register is written into the shift register 1 at the falling edge of i _ scl, and the next 8 i _ scl clock cycles i _ sda sequentially output 8 data. The communication is finished after the host replies the non-response signal and the termination signal. If an abnormal repeated starting signal is detected in the transmission process, the rs _ error signal generates a single-period pulse, and the count value of the counter is asynchronously cleared; if the termination signal is abnormal, the transmission is directly ended.
It will be understood by those skilled in the art that the embodiments of the present invention described above and illustrated in the drawings are given by way of example only and not by way of limitation, the objects of the utility model having been fully and effectively achieved, the functional and structural principles of the present invention having been shown and described in the embodiments, and that various changes or modifications may be made in the embodiments of the present invention without departing from such principles.
Claims (8)
1. An apparatus for detecting an I2C bus, the apparatus comprising:
a bus state detection module;
a counter;
a register group;
a data conversion module;
an address comparison module;
the bus state detection module is connected with the counter, the counter is connected with the data conversion module, the data conversion module is connected with the register bank, and the address comparison module is connected with the register bank.
2. The I2C bus detection device as claimed in claim 1, wherein the data conversion module comprises an input data serial-to-parallel conversion module and an output data parallel-to-serial conversion module, and the register set comprises a first output terminal and a second output terminal, wherein the first output terminal is connected to the input data serial-to-parallel conversion module, and the second output terminal is connected to the output data parallel-to-serial conversion module.
3. The I2C bus detection device as claimed in claim 2, wherein the address comparison module comprises a slave address comparison module and an on-chip address selection module, wherein the input data serial-parallel conversion module is connected to the slave address comparison module, the slave address comparison module is connected to the on-chip address selection module, and the on-chip address selection module is connected to the register set.
4. The apparatus of claim 2, wherein said register set comprises 9 registers, and wherein said 9 registers are configured as 8-bit registers.
5. The I2C bus detection device as claimed in claim 1, wherein the device comprises a data input interface, a clock input interface and a data output interface, and the counter is an 8-bit memory, wherein the data input interface is respectively disposed on the bus state detection module, the input data serial-parallel conversion module and the address comparison module.
6. The I2C bus detection device as claimed in claim 1, wherein the device comprises a data output line enable interface and a reset interface, the data output line enable interface is disposed on the output data parallel-serial conversion module, and the reset interface is disposed on the bus state detection module.
7. The I2C bus detection device as claimed in claim 2, wherein the counter comprises a clock signal output interface, the clock signal output interface is respectively connected to the input data serial-to-parallel conversion module, the output data parallel-to-serial conversion module and the address comparison module, the bus state detection module comprises a clock signal enable interface, and the clock signal enable interface is connected to the counter.
8. The device as claimed in claim 1, wherein the bus status detection module comprises a signal start interface and a signal stop interface, wherein the signal start interface and the signal stop interface are respectively connected to the counter.
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| CN202122879881.7U CN216352286U (en) | 2021-11-23 | 2021-11-23 | Detection apparatus for I2C bus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116028403A (en) * | 2023-03-27 | 2023-04-28 | 江苏润石科技有限公司 | I2C bus circuit based on asynchronous circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116028403A (en) * | 2023-03-27 | 2023-04-28 | 江苏润石科技有限公司 | I2C bus circuit based on asynchronous circuit |
| CN116028403B (en) * | 2023-03-27 | 2023-06-06 | 江苏润石科技有限公司 | I2C bus circuit based on asynchronous circuit |
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Address after: 311422 4th floor, building 9, Yinhu innovation center, 9 Fuxian Road, Yinhu street, Fuyang District, Hangzhou City, Zhejiang Province Patentee after: Zhejiang Xinmai Microelectronics Co.,Ltd. Address before: 311400 4th floor, building 9, Yinhu innovation center, No.9 Fuxian Road, Yinhu street, Fuyang District, Hangzhou City, Zhejiang Province Patentee before: Hangzhou xiongmai integrated circuit technology Co.,Ltd. |
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