CN116028403B - I2C bus circuit based on asynchronous circuit - Google Patents
I2C bus circuit based on asynchronous circuit Download PDFInfo
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Abstract
The embodiment of the application provides an I2C bus circuit based on an asynchronous circuit, which is arranged on a slave side, is based on the cooperation of a first filter circuit, a second filter circuit, a data decoding module, a state detection module, an SCL clock counter, a finite state machine and a rate mode detection module, does not need to set an extra high-speed clock signal to carry out synchronous circuit design, and detects a communication start mark and a communication end mark of an I2C bus through the relation between the SCL signal and the SDA signal, so that the bus state detection is stable and reliable, the circuit is simple to realize, and the power consumption and the area cost are very small.
Description
Technical Field
The application relates to the technical field of microelectronics, in particular to an I2C bus circuit based on an asynchronous circuit.
Background
I2C (Inter-Integrated Circuit) bus is a serial communication bus that is often used in embedded system designs. It implements bidirectional data communication between multiple interconnected devices in a master-slave manner based on a serial clock (Serial Clock Line, abbreviated SCL) and a serial data Line (SDA) two-wire connection.
The traditional I2C bus needs additional high-speed clock signals to carry out synchronous circuit design besides SCL and SDA double lines, and is large in scale and high in power consumption, as shown in fig. 1, and is inconvenient for accessing terminal equipment of the Internet of things.
Aiming at the problems of large scale and high power consumption caused by the fact that the traditional I2C bus needs additional high-speed clock signals to carry out synchronous circuit design besides SCL and SDA double lines in the related technology, no effective solution exists at present.
Disclosure of Invention
The embodiment of the application provides an I2C bus state detection circuit based on an asynchronous circuit, which aims to solve the problems that in the related art, a traditional I2C bus needs additional high-speed clock signals to carry out synchronous circuit design besides SCL (serial digital interface) and SDA (serial digital interface) double lines, and therefore large scale and high power consumption are caused.
In one embodiment of the present application, an I2C bus state detection circuit based on an asynchronous circuit is provided, provided on a slave side, the circuit comprising:
the first filter circuit is configured to filter an SCL signal sent by the host;
the input end of the second filter circuit is connected with the data decoding module, the output end of the second filter circuit is connected with the state detection module and the finite state machine, and the second filter circuit is configured to filter the SDA signal sent by the host;
the data decoding module is in communication connection with a serial data SDA bus interface, the output end of the data decoding module is connected with the second filter circuit, and the data decoding module is configured to decode data on an SDA bus and send the decoded data to the second filter circuit or the host through the SDA bus interface;
the input end of the state detection module is connected with the first filter circuit and the second filter circuit, the output end of the state detection module is connected with an SCL clock counter and the finite state machine, and the state detection module is configured to detect a communication start mark and a communication end mark of the I2C bus according to the relation between the SCL signal and the SDA signal;
the SCL clock counter is provided with an input end connected with the first filter circuit and the state detection module, an output end connected with the finite state machine, and is configured to count the number of pulses of the SCL signal;
the finite state machine is configured to determine the working state of the slave according to the received SCL signal and the SDA signal, wherein the working state comprises a starting working state and an ideal state;
the speed mode detection module is configured to determine an operating mode of the slave according to an instruction, and further select a peripheral circuit corresponding to the operating mode, wherein the operating mode comprises a standard mode of 100Kbps, a fast mode of 400Kbps and a high-speed mode of 3.4 Mbps.
In an embodiment, the asynchronous circuit based I2C bus state detection circuit further comprises:
and the output data phase fine tuning module is configured to determine the time for the slave to hold the SDA signal when the falling edge of the SCL clock arrives according to the working mode of the slave when the slave controls the SDA bus.
In one embodiment, the output data phase fine adjustment module includes:
the data selector selects one of the standard mode fine tuning unit, the fast mode fine tuning unit and the high-speed mode fine tuning unit to output data according to the working mode of the slave machine determined by the rate mode detection module, wherein the standard mode fine tuning unit keeps the SDA signal for a first time when an SCL clock falling edge arrives, the fast mode fine tuning unit keeps the SDA signal for a second time when an SCL clock falling edge arrives, and the high-speed mode fine tuning unit keeps the SDA signal for a third time when the SCL clock falling edge arrives.
In an embodiment, the finite state machine comprises, internally:
and the data serial-parallel conversion module is configured to perform serial-parallel conversion on the data signal and the clock signal which are input into the finite state machine, and then process the data signal and the clock signal by the finite state machine.
In an embodiment, the state detection module includes a start state detection unit configured to:
when the falling edge of the SDA signal arrives, if SCL is high level, the first starting signal sent by the state detection module is pulled high and kept, and when the falling edge of the next SDA signal arrives, the first starting signal is pulled low;
when the falling edge of the SCL signal arrives, if the first starting signal is high level and the second starting signal sent by the state detection module is low level, the second starting signal is pulled high, and when the falling edge of the next SCL signal arrives, if the first starting signal and the second starting signal are both high level, the second starting signal is pulled low;
and if the third start signal sent by the state detection module only maintains a high level of one SCL period in the communication process of the host and the slave, and takes the rising edge of the third start signal as a mark for starting the communication of the I2C bus when the third start signal is irrelevant to data sent by the host, wherein the rising edge of the third start signal is consistent with the rising edge of the first pulse of the second start signal.
In an embodiment, the state detection module includes an end state detection unit configured to:
when the rising edge of the SDA signal arrives, if the SCL signal is in a high level, the stop signal sent by the state detection module is pulled high, and the rising edge of the stop signal is determined as a mark for ending the communication of the I2C bus.
In an embodiment, the finite state machine is further configured to:
after the state detection module detects a sign of starting the communication of the I2C bus, the finite state machine sets the working state of the slave machine to be a starting working state and receives a first data signal sent by the host machine;
determining the working mode of the slave according to the content of the first data signal;
judging whether the first data signal is matched with the address of the slave machine or not according to the content of the first data signal;
when the first data signal indicates that the address is matched and the writing is valid, writing operation is executed, and the working state of the slave is set to be an ideal state when a mark of communication ending sent by the host is received;
when the first data signal indicates that the address is matched and the reading is effective, reading operation is executed, and the working state of the slave is set to be an ideal state when a mark of the communication end sent by the host is received;
and when the first data signal indicates that the addresses are not matched, setting the working state of the slave to be an ideal state.
In an embodiment, the finite state machine is further configured to:
if the address sent by the host computer is not matched with the slave computer, the finite state machine sends NACK to the host computer, and the working state of the slave computer is set to be an ideal state;
and if the host computer directly transmits a stop bit after transmitting a part of data, the finite state machine discards the currently received data and sets the working state of the slave computer to an ideal state.
In an embodiment, the first filter circuit includes: the SCL signal input by the first Schmitt trigger, the second Schmitt trigger and the first RC low-pass filter firstly passes through the first Schmitt trigger, and when the amplitude of the SCL signal is larger than the forward threshold voltage of the first Schmitt trigger, the output is 0, and otherwise, the output is 1; the SCL signal output by the first Schmitt trigger is filtered by the first RC low-pass filter, the filtered SCL signal is converted into a rectangular pulse signal with a steep edge through the positive feedback effect in the conversion process of the second Schmitt trigger, and the filtered rectangular pulse signal is output by the second Schmitt trigger;
the second filter circuit includes: the input SDA signal firstly passes through the third Schmitt trigger, and when the amplitude of the SDA signal is larger than the forward threshold voltage of the third Schmitt trigger, the output is 0, and otherwise, the output is 1; and the SDA signal output by the third Schmitt trigger is filtered by the second RC low-pass filter, the filtered SDA signal is converted into a rectangular pulse signal with a steep edge by the positive feedback effect in the conversion process of the fourth Schmitt trigger, and the filtered rectangular pulse signal is output by the fourth Schmitt trigger.
According to the I2C bus state detection circuit based on the asynchronous circuit, the problems that the scale is large and the power consumption is high due to the fact that an additional high-speed clock signal is needed for synchronous circuit design besides SCL and SDA double lines in a traditional I2C bus in the related technology are solved, the synchronous circuit design is conducted, the problem that the additional high-speed clock signal is not needed to be set for the synchronous circuit design, the communication start mark and the communication end mark of the I2C bus are detected through the relation between SCL signals and SDA signals, the bus state detection is stable and reliable, the circuit implementation is simple, and the power consumption and the area cost are very small are solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 is a schematic diagram of signal detection of an I2C bus state detection circuit based on a synchronous circuit in the prior art;
FIG. 2 is a schematic diagram of an alternative asynchronous circuit-based I2C bus state detection circuit in an embodiment of the present application;
FIG. 3 is a schematic diagram of an alternative filter circuit configuration according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an alternative transmission data status detection in an embodiment of the present application;
FIG. 5 is a schematic diagram of another alternative transmission data status detection in an embodiment of the present application;
FIG. 6 is an alternative I2C bus state jump schematic diagram according to an embodiment of the present application;
FIG. 7 is a schematic diagram of an alternative standard mode to fast mode switching in accordance with an embodiment of the present application;
FIG. 8 is a schematic diagram of an alternative normal mode to high speed mode switching in accordance with an embodiment of the present application;
FIG. 9 is a schematic diagram of an alternative peripheral circuit switching scheme according to an embodiment of the present application;
FIG. 10 is a schematic diagram of an alternative slave SDA bus data retention time according to an embodiment of the present application;
FIG. 11 is a schematic diagram showing phase fine adjustment of output data in an alternative different rate mode according to an embodiment of the present application.
Detailed Description
The present application will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The technical problem to be solved by the application is to provide an ultralow-power-consumption I2C bus slave circuit based on an asynchronous circuit aiming at the defects of the prior art, and the traditional I2C bus is characterized in that an additional high-speed clock signal is required for synchronous circuit design besides SCL and SDA double lines, so that the problems of large scale and high power consumption are caused. The bus judges the starting and ending states by the relation between SCL and SDA signals, receives data by the rising edge of the SCL signal, and transmits data by the falling edge.
Specifically, in one embodiment of the present application, an I2C bus state detection circuit based on an asynchronous circuit is provided on the slave side. FIG. 2 is a schematic diagram of an alternative asynchronous circuit-based I2C bus state detection circuit according to an embodiment of the present application, where the circuit includes: the filter circuit 1 (corresponding to the first filter circuit), the filter circuit 2 (corresponding to the second filter circuit), the data decoding module (IObuf), the state detection module, the SCL clock counter, the finite state machine, and the rate mode detection module.
The input end of the first filter circuit is connected with the serial clock SCL bus interface, the output end of the first filter circuit is connected with the state detection module and the SCL clock counter, and the first filter circuit is configured to filter SCL signals sent by the host;
the input end of the second filter circuit is connected with the data decoding module, the output end of the second filter circuit is connected with the state detection module and the finite state machine, and the second filter circuit is configured to filter the SDA signal sent by the host;
the data decoding module is in communication connection with the serial data SDA bus interface, the output end of the data decoding module is connected with the second filter circuit, and the data decoding module is configured to decode data on the SDA bus and send the decoded data to the second filter circuit or the host through the SDA bus interface;
the input end of the state detection module is connected with the first filter circuit and the second filter circuit, the output end of the state detection module is connected with the SCL clock counter and the finite state machine, and the state detection module is configured to detect a communication start mark and a communication end mark of the I2C bus according to the relation between the SCL signal and the SDA signal;
the SCL clock counter is provided with an input end connected with the first filter circuit and the state detection module, an output end connected with the finite state machine and configured to count the number of pulses of an SCL signal;
the input end of the finite state machine is connected with the second filter circuit, the state detection module, the SCL clock counter and the register set, the output end of the finite state machine is connected with the rate mode detection module, the output data phase fine adjustment module, the register set and the data decoding module, and the finite state machine is configured to determine the working state of the slave machine according to the received SCL signal and SDA signal, wherein the working state comprises a starting working state and an ideal state;
the speed mode detection module is connected with the state detection module and the finite state machine, the output end of the speed mode detection module is connected with the peripheral circuit, the speed mode detection module is configured to determine the working mode of the slave according to the instruction, and then the peripheral circuit corresponding to the working mode is selected, wherein the working mode comprises a standard mode of 100Kbps, a high-speed mode of 3.4Mbps and a fast mode of 400 Kbps.
In an embodiment, the first filter circuit includes: the SCL signal input by the first Schmitt trigger, the second Schmitt trigger and the first RC low-pass filter firstly passes through the first Schmitt trigger, and when the amplitude of the SCL signal is larger than the forward threshold voltage of the first Schmitt trigger, the output is 0, and otherwise, the output is 1; the SCL signal output by the first Schmitt trigger is filtered by the first RC low-pass filter, the filtered SCL signal is converted into a rectangular pulse signal with a steep edge through the positive feedback effect in the conversion process of the second Schmitt trigger, and the filtered rectangular pulse signal is output by the second Schmitt trigger;
the second filter circuit includes: the input SDA signal firstly passes through the third Schmitt trigger, and when the amplitude of the SDA signal is larger than the forward threshold voltage of the third Schmitt trigger, the output is 0, and otherwise, the output is 1; and the SDA signal output by the third Schmitt trigger is filtered by the second RC low-pass filter, the filtered SDA signal is converted into a rectangular pulse signal with a steep edge by the positive feedback effect in the conversion process of the fourth Schmitt trigger, and the filtered rectangular pulse signal is output by the fourth Schmitt trigger.
The same circuit structure may be used for the first filter circuit and the second filter circuit, and fig. 3 is a schematic diagram of an alternative filter circuit according to an embodiment of the present application, where the filter circuit includes two Schmitt triggers (Schmitt Trigger 1 and Schmitt Trigger 2) and a first-order RC low-pass filter as shown in fig. 3. The filter circuit comprises four MOS tubes M1, M2, M3 and M4, wherein the source electrode of M1 is connected with a power supply, the grid electrode of M1 is connected with the grid electrode of M4, the drain electrode of M1 is connected with the source electrode of M2, the grid electrode of M2 is connected with the grid electrode of M3, the drain electrode of M2 is connected with the drain electrode of M3, the source electrode of M3 is connected with the drain electrode of M4, and the source electrode of M4 is grounded. One end of the first inverter INV1 is connected with the grid of the M2 and the grid of the M3, the other end of the first inverter INV2 is connected with the output end OUT, one end of the second inverter INV2 is connected with the grid of the M1 and the grid of the M4, and the other end of the second inverter INV2 is connected with the first Schmitt Trigger 1. Because asynchronous circuits do not use clock pulses for synchronization, their subsystems are synchronized based on relationships between signals. Therefore, the slave has higher requirements on the signal quality of SCL and SDA input by the master. In order to eliminate signal jitter and glitches that may occur on the bus, embodiments of the present application filter the bus signal in the analog circuit portion.
The Schmitt trigger has two threshold voltages, namely a positive threshold voltage and a negative threshold voltage, and an input signal firstly passes through the first Schmitt trigger, and if the amplitude of the input signal is larger than the positive threshold voltage V+, the output is 0; whereas the output is 1. The shaped signal is filtered by a first-order RC low-pass filter, and burrs in the signal are removed. Wherein, RC value determines the width of the removed burr. The filtered signal is converted into a rectangular pulse signal with a steep edge by utilizing the positive feedback effect in the conversion process of the second Schmitt trigger, and the output end of the second Schmitt trigger can obtain the filtered rectangular pulse signal so as to improve the robustness of the system.
In an embodiment, the state detection module comprises a start state detection unit configured to:
when the falling edge of the SDA signal arrives, if SCL is high level, the first starting signal sent by the state detection module is pulled high and kept, and when the falling edge of the next SDA signal arrives, the first starting signal is pulled low;
when the falling edge of the SCL signal arrives, if the first starting signal is high level and the second starting signal sent by the state detection module is low level, the second starting signal is pulled high, and when the falling edge of the next SCL signal arrives, if the first starting signal and the second starting signal are both high level, the second starting signal is pulled low;
and if the third start signal sent by the state detection module only maintains a high level of one SCL period in the communication process of the host and the slave, and takes the rising edge of the third start signal as a mark for starting the communication of the I2C bus when the third start signal is irrelevant to data sent by the host, wherein the rising edge of the third start signal is consistent with the rising edge of the first pulse of the second start signal.
In an embodiment, the state detection module comprises an end state detection unit configured to:
when the rising edge of the SDA signal arrives, if the SCL signal is in a high level, the stop signal sent by the state detection module is pulled high, and the rising edge of the stop signal is determined as a mark for ending the communication of the I2C bus.
Fig. 4 is a schematic diagram of an alternative transmission data state detection in the embodiment of the present application, and fig. 5 is a schematic diagram of another alternative transmission data state detection in the embodiment of the present application, where, as shown in fig. 4 and fig. 5, the bus state detection module includes a start state detection and an end state detection.
Starting state detection:
when the SDA falling edge arrives, if SCL is high, the START_1 signal (corresponding to the first START signal) is pulled high; the START _1 signal will pull low only when the next SDA falling edge comes. Thus, the duration of the start_1 signal depends on the SDA data sent by the host, which is clearly detrimental to the design of subsequent circuits, which in some special cases may even lead to unpredictable I2C bus state jumps, with poor robustness of the circuit. Thus, the present embodiment introduces a start_2 signal (corresponding to the aforementioned second START signal).
When the SCL falling edge comes, if start_1 is high and start_2 is low, then the start_2 signal is pulled high; when the next falling edge of SCL arrives, if START_1 and START_2 are both high, the START_2 signal is pulled low. And so on. However, as can be seen from fig. 5, the start_2 signal may have multiple transitions. Therefore, the present embodiment introduces a start_3 signal (corresponding to the aforementioned third START signal).
The start_3 signal is the first valid start_2 signal, and the master-slave communication start_3 maintains only one SCL period high level every time, and is stable and reliable irrespective of data sent by the host. Therefore, the embodiment of the present application uses the rising edge of the start_3 signal as a flag for communication START.
And (3) ending detection:
when the rising edge of SDA arrives, if SCL is high, the STOP signal (corresponding to the STOP signal described above) is pulled high as a flag for ending communication. Since both SCL and SDA remain high after the communication is completed, the STOP signal remains high until the next SDA rising edge.
In an embodiment, the finite state machine comprises, internally:
and the data serial-parallel conversion module is configured to perform serial-parallel conversion on the data signal and the clock signal which are input into the finite state machine, and then process the data signal and the clock signal by the finite state machine.
In an embodiment, the finite state machine is further configured to:
after the state detection module detects a sign of starting the communication of the I2C bus, the finite state machine sets the working state of the slave machine to be a starting working state and receives a first data signal sent by the host machine;
determining the working mode of the slave according to the content of the first data signal;
judging whether the first data signal is matched with the address of the slave machine or not according to the content of the first data signal;
when the first data signal indicates that the address is matched and the writing is valid, writing operation is executed, and the working state of the slave is set to be an ideal state when a mark of communication ending sent by the host is received;
when the first data signal indicates that the address is matched and the reading is effective, reading operation is executed, and the working state of the slave is set to be an ideal state when a mark of the communication end sent by the host is received;
and when the first data signal indicates that the addresses are not matched, setting the working state of the slave to be an ideal state.
It should be noted that, the first data signal may be understood as a data signal of a plurality of SCL pulses, and if one byte is acknowledged once between the master and the slave, the first data signal includes one byte, i.e. 8 bits, for example, instruction "00011XXX".
In an embodiment, the finite state machine is further configured to:
if the address sent by the host computer is not matched with the slave computer, the finite state machine sends NACK to the host computer, and the working state of the slave computer is set to be an ideal state;
and if the host computer directly transmits a stop bit after transmitting a part of data, the finite state machine discards the currently received data and sets the working state of the slave computer to an ideal state.
FIG. 6 is an alternative I2C bus state jump schematic diagram of an embodiment of the present application, as shown in FIG. 6, which may be understood as an operation process inside the finite state machine. The default slave machine works in a standard mode, the jump of the I2C bus state machine is controlled by using a START_3 signal, a STOP signal and an SCL counter, and different data are sent to the host machine by the control bus under different states of the state machine, so that master-slave communication is realized. The I2C bus state machine contains 7 states, respectively IDLE (power-on, ideal state), START (START), ADDR (address), hs_mode (high speed Mode), fs_mode (fast Mode), rd_data (read DATA), wr_data (write DATA), and the state jump diagram is shown in fig. 6. Wherein the communication rate in the standard mode may be 100Kbps, the communication rate in the fast mode may be 400Kbps, and the communication rate in the high-speed mode may be 3.4 Mbps.
The I2C bus slave provided by the embodiment of the application supports a standard mode (100 Kbps), a fast mode (400 Kbps) and a high-speed mode (3.4 Mbps). The I2C bus slave operates in standard mode by default and must send a specific instruction code to the slave if the master wants to switch to other rate modes. The timing of the slave mode is shown in fig. 7 and 8, where fig. 7 is a schematic diagram of switching from an optional standard mode to a fast mode in the embodiment of the present application, and fig. 8 is a schematic diagram of switching from an optional standard mode to a fast mode in the embodiment of the present application.
As shown in FIGS. 7 and 8, the slave defaults to operate in the standard MODE with MODE_SEL of 00. When the rate MODE detection module of the slave detects the instruction code '00011 XXX', MODE_SEL is set to 01, and peripheral circuits corresponding to the fast MODE are selected through the multiplexers 2-4 MUX. After the rate MODE detection module of the slave detects the command code "00001XXX", the mode_sel is set to 10, and the peripheral circuits corresponding to the high-speed MODE are selected through the multiplexer 2-4 MUX, and the peripheral circuits in different rate MODEs are shown in fig. 9 (taking a master-slave communication structure mounted on the bus as an example).
Fig. 9 is an alternative peripheral circuit switching schematic diagram according to an embodiment of the present application. As shown in fig. 9, both the SCL and SDA buses are equipped with pull-up resistors and load capacitors, and different combinations of resistors and capacitors determine the time for charging and discharging the capacitors on the buses to be full. The bus remains high when the capacitor is fully charged and low when the capacitor is fully discharged. The smaller the RC product, the faster the capacitor charges and discharges, and the greater the highest transfer rate the bus can support. When the sending rate of the sender exceeds the highest transmission rate of the bus, the receiver may cause a reception error due to the poor quality of the bus signal.
In one embodiment, the asynchronous circuit based I2C bus state detection circuit further comprises:
and the output data phase fine tuning module is configured to determine the time for the slave to hold the SDA signal when the falling edge of the SCL clock arrives according to the working mode of the slave when the slave controls the SDA bus.
In one embodiment, the output data phase fine adjustment module includes:
the data selector selects one of the standard mode fine tuning unit, the fast mode fine tuning unit and the high-speed mode fine tuning unit to output data according to the working mode of the slave machine determined by the rate mode detection module, wherein the standard mode fine tuning unit keeps the SDA signal for a first time when an SCL clock falling edge arrives, the fast mode fine tuning unit keeps the SDA signal for a second time when an SCL clock falling edge arrives, and the high-speed mode fine tuning unit keeps the SDA signal for a third time when the SCL clock falling edge arrives.
Fig. 10 is a schematic diagram of an optional slave SDA bus data retention time according to an embodiment of the present application, and fig. 11 is a schematic diagram of fine adjustment of output data phase in an optional different rate mode according to an embodiment of the present application. As shown in fig. 10 and 11, in order to enable the host to accurately receive the data sent by the slave, the embodiment of the present application fine-adjusts the phase of the output data according to different communication rates. When the SCL clock falling edge arrives, the slave keeps the SDA for a period of time to ensure that the host can accurately receive the data. In the standard mode, the fast mode, the high speed mode, the hold time t hold Approximately 100ns, 80ns, 40ns, respectively.
In one embodiment, the finite state machine is further connected to a register set, where the register set is used to store data, and the finite state machine can read and write data from the register set.
According to the I2C bus state detection circuit based on the asynchronous circuit, the problems that the scale is large and the power consumption is high due to the fact that an additional high-speed clock signal is needed for synchronous circuit design besides SCL and SDA double lines in a traditional I2C bus in the related technology are solved, the synchronous circuit design is conducted, the problem that the additional high-speed clock signal is not needed to be set for the synchronous circuit design, the communication start mark and the communication end mark of the I2C bus are detected through the relation between SCL signals and SDA signals, the bus state detection is stable and reliable, the circuit implementation is simple, and the power consumption and the area cost are very small are solved.
Meanwhile, the asynchronous circuit-based I2C bus state detection circuit provided by the embodiment of the application supports the switching of three rate modes of a standard mode (100 Kbps), a fast mode (400 Kbps) and a high-speed mode (3.4 Mbps), allows the functions of single-byte read-write, continuous-byte read-write, broadcast addressing and the like, and comprises five modules including a filter circuit, bus state detection, normal operation, communication rate switching and output data phase fine adjustment. The design method of the asynchronous circuit is adopted, the communication rate is switchable, the maximum rate reaches 3.4Mbps, the bus state detection is stable and reliable, the circuit is simple to realize, and the power consumption and the area cost are very small.
The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.
Claims (9)
1. An I2C bus circuit based on an asynchronous circuit, provided on a slave side, comprising:
the first filter circuit is configured to filter an SCL signal sent by the host;
the input end of the second filter circuit is connected with the data decoding module, the output end of the second filter circuit is connected with the state detection module and the finite state machine, and the second filter circuit is configured to filter the SDA signal sent by the host;
the data decoding module is in communication connection with a serial data SDA bus interface, the output end of the data decoding module is connected with the second filter circuit, and the data decoding module is configured to decode data on an SDA bus and send the decoded data to the second filter circuit or the host through the SDA bus interface;
the input end of the state detection module is connected with the first filter circuit and the second filter circuit, the output end of the state detection module is connected with an SCL clock counter and the finite state machine, and the state detection module is configured to detect a communication start mark and a communication end mark of the I2C bus according to the relation between the SCL signal and the SDA signal;
the SCL clock counter is provided with an input end connected with the first filter circuit and the state detection module, an output end connected with the finite state machine, and is configured to count the number of pulses of the SCL signal;
the finite state machine is configured to determine the working state of the slave according to the received SCL signal and the SDA signal, wherein the working state comprises a starting working state and an ideal state;
the speed mode detection module is configured to determine an operating mode of the slave according to an instruction, and further select a peripheral circuit corresponding to the operating mode, wherein the operating mode comprises a standard mode of 100Kbps, a fast mode of 400Kbps and a high-speed mode of 3.4 Mbps.
2. The asynchronous circuit based I2C bus circuit of claim 1, wherein the asynchronous circuit based I2C bus state detection circuit further comprises:
and the output data phase fine tuning module is configured to determine the time for the slave to hold the SDA signal when the falling edge of the SCL clock arrives according to the working mode of the slave when the slave controls the SDA bus.
3. The asynchronous circuit based I2C bus circuit of claim 2, wherein the output data phase trimming module comprises:
the data selector selects one of the standard mode fine tuning unit, the fast mode fine tuning unit and the high-speed mode fine tuning unit to output data according to the working mode of the slave machine determined by the rate mode detection module, wherein the standard mode fine tuning unit keeps the SDA signal for a first time when an SCL clock falling edge arrives, the fast mode fine tuning unit keeps the SDA signal for a second time when an SCL clock falling edge arrives, and the high-speed mode fine tuning unit keeps the SDA signal for a third time when the SCL clock falling edge arrives.
4. The asynchronous circuit based I2C bus circuit of claim 1, wherein the finite state machine internally comprises:
and the data serial-parallel conversion module is configured to perform serial-parallel conversion on the data signal and the clock signal which are input into the finite state machine, and then process the data signal and the clock signal by the finite state machine.
5. The asynchronous circuit based I2C bus circuit of claim 1, wherein the status detection module comprises a start status detection unit configured to:
when the falling edge of the SDA signal arrives, if SCL is high level, the first starting signal sent by the state detection module is pulled high and kept, and when the falling edge of the next SDA signal arrives, the first starting signal is pulled low;
when the falling edge of the SCL signal arrives, if the first starting signal is high level and the second starting signal sent by the state detection module is low level, the second starting signal is pulled high, and when the falling edge of the next SCL signal arrives, if the first starting signal and the second starting signal are both high level, the second starting signal is pulled low;
and if the third start signal sent by the state detection module only maintains a high level of one SCL period in the communication process of the host and the slave, and takes the rising edge of the third start signal as a mark for starting the communication of the I2C bus when the third start signal is irrelevant to data sent by the host, wherein the rising edge of the third start signal is consistent with the rising edge of the first pulse of the second start signal.
6. The asynchronous circuit based I2C bus circuit of claim 5, wherein the state detection module comprises an end state detection unit configured to:
when the rising edge of the SDA signal arrives, if the SCL signal is in a high level, the stop signal sent by the state detection module is pulled high, and the rising edge of the stop signal is determined as a mark for ending the communication of the I2C bus.
7. The asynchronous circuit based I2C bus circuit of claim 1, wherein the finite state machine is further configured to:
after the state detection module detects a sign of starting the communication of the I2C bus, the finite state machine sets the working state of the slave machine to be a starting working state and receives a first data signal sent by the host machine;
determining the working mode of the slave according to the content of the first data signal;
judging whether the first data signal is matched with the address of the slave machine or not according to the content of the first data signal;
when the first data signal indicates that the address is matched and the writing is valid, writing operation is executed, and the working state of the slave is set to be an ideal state when a mark of communication ending sent by the host is received;
when the first data signal indicates that the address is matched and the reading is effective, reading operation is executed, and the working state of the slave is set to be an ideal state when a mark of the communication end sent by the host is received;
and when the first data signal indicates that the addresses are not matched, setting the working state of the slave to be an ideal state.
8. The asynchronous circuit based I2C bus circuit of claim 7, wherein the finite state machine is further configured to:
if the address sent by the host computer is not matched with the slave computer, the finite state machine sends NACK to the host computer, and the working state of the slave computer is set to be an ideal state;
and if the host computer directly transmits a stop bit after transmitting a part of data, the finite state machine discards the currently received data and sets the working state of the slave computer to an ideal state.
9. The asynchronous circuit based I2C bus circuit of claim 1, wherein,
the first filter circuit includes: the SCL signal input by the first Schmitt trigger, the second Schmitt trigger and the first RC low-pass filter firstly passes through the first Schmitt trigger, and when the amplitude of the SCL signal is larger than the forward threshold voltage of the first Schmitt trigger, the output is 0, and otherwise, the output is 1; the SCL signal output by the first Schmitt trigger is filtered by the first RC low-pass filter, the filtered SCL signal is converted into a rectangular pulse signal with a steep edge through the positive feedback effect in the conversion process of the second Schmitt trigger, and the filtered rectangular pulse signal is output by the second Schmitt trigger;
the second filter circuit includes: the input SDA signal firstly passes through the third Schmitt trigger, and when the amplitude of the SDA signal is larger than the forward threshold voltage of the third Schmitt trigger, the output is 0, and otherwise, the output is 1; and the SDA signal output by the third Schmitt trigger is filtered by the second RC low-pass filter, the filtered SDA signal is converted into a rectangular pulse signal with a steep edge by the positive feedback effect in the conversion process of the fourth Schmitt trigger, and the filtered rectangular pulse signal is output by the fourth Schmitt trigger.
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