CN108647161B - Hardware monitoring circuit for recording access address history - Google Patents
Hardware monitoring circuit for recording access address history Download PDFInfo
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- CN108647161B CN108647161B CN201810340474.9A CN201810340474A CN108647161B CN 108647161 B CN108647161 B CN 108647161B CN 201810340474 A CN201810340474 A CN 201810340474A CN 108647161 B CN108647161 B CN 108647161B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Abstract
A hardware monitoring circuit for recording memory access address history comprises a monitoring area configuration unit, an arbitration control unit, a tag memory, a tag bit counting unit, a priority content addressing memory bank j, a secondary priority content addressing memory bank and a multiplexer. Compared with the prior art, the invention can monitor a plurality of discontinuous address spaces by adopting the two-stage priority content addressing memory bank, can carry out configuration selection on the monitoring granularity, realizes the compromise optimization of the monitoring range and the monitoring granularity, and provides hardware support for the data information synchronization process after the single computer in the hot backup computer is out of step.
Description
Technical Field
The invention relates to a hardware monitoring circuit for recording access address history.
Background
During the continuous and stable operation of the hot backup computer, a single computer and other single computers are out of step due to various faults, and the complete machine of the hot backup computer is degraded to operate. In order to improve the reliability and the service life of the whole hot backup computer, the significance of reintroducing the desynchronized single computer caused by transient faults into the operation of the whole hot backup computer is great. The problem of how to reintroduce the hot backup computer into the whole hot backup computer to work again is the parallel operation problem.
The GNCC adopts a five-unit hot standby fault-tolerant configuration, wherein four single units have processing capacity, and one single unit has no processing capacity. According to the GNCC operation process, the desynchronized single machine is different from the normal single machine in the field information. The field information can be divided into two categories: 1) time information; 2) and (4) data information. Therefore, the out-of-step single machine can recover the synchronization with other normal single machines only by finishing the time synchronization and the data synchronization.
Disclosure of Invention
The technical problem solved by the invention is as follows: the hardware monitoring circuit overcomes the defects of the prior art, provides a hardware monitoring circuit for recording memory access address history, overcomes the defect that the memory access address history of the traditional processor cannot be recorded, can monitor a plurality of discontinuous address spaces by adopting a two-stage priority content addressing memory bank, can carry out configuration selection on monitoring granularity, realizes compromise optimization of monitoring range and monitoring granularity, and provides hardware support for the data information synchronization process after the single computer in a hot backup computer is out of step.
The technical solution of the invention is as follows: a hardware monitoring circuit for recording memory access address history comprises a monitoring area configuration unit, an arbitration control unit, a tag memory, a tag bit counting unit, a priority content addressing memory bank j, a secondary priority content addressing memory bank and a multiplexer;
the monitoring area configuration unit is used for configuring a monitoring address range, a monitoring address granularity and a monitoring enable according to the external task requirement, sending the configured monitoring address range, the configured monitoring address granularity and the configured monitoring enable to the arbitration control unit, and configuring a monitoring start address register and a monitoring end address register according to the configured monitoring address range, wherein the configuration value of the monitoring start address register is smaller than that of the monitoring end address register; the granularity of the monitoring address is 16n bytes and not more than 1024 bytes, wherein n is an integer;
the arbitration control unit is used for monitoring a write enable signal of the bus to be monitored, judging the granularity of the monitored address when the address to be monitored is in the range of the monitored address and the write enable signal of the bus to be monitored is valid, if the granularity of the monitored address is 16n bytes, generating a mark memory write signal which is valid and the write address is from the (n + 8) th bit to the (n-1) th bit of the address to be monitored, wherein the bit is 10 bits in total, and sending the mark memory write signal and the write address to the mark bit counting unit and the mark memory;
the marking memory is used for receiving a writing signal and a writing address of the marking memory to carry out marking storage, when the writing signal of the marking memory is effective, the bit position corresponding to the writing address is set to be 1, and the rest bit positions are unchanged; sending the numerical values corresponding to 1024 bits in the tag memory to a tag bit counting unit; continuously packaging 32 numerical values corresponding to 1024 bits in the tag memory to obtain 32 numerical value packets, and respectively sending the 32 numerical value packets to a 32-priority content addressing memory bank;
the marking bit counting unit receives numerical values corresponding to 1024 bits in the marking memory, a marking memory writing signal and a writing address, and adds 1 to the marking bit counting unit when the writing enable signal is effective and the bits in the marking memory corresponding to the writing address are 0;
the method comprises the steps that priority content addresses a memory bank j, wherein j is a positive integer not larger than 32, a 32-bit numerical value packet is received, and a monitoring effective mark j and a priority address output j are generated; if all the 32-bit numerical value packets received by the priority content addressing memory bank j are 0, the monitoring valid flag j is 0, otherwise, the monitoring valid flag j is 1; when the k-th bit of the 32-bit value is 1 and the 0 th bit to k-1 bit are 0, the priority address output j is a 5-bit binary of k, where k is 1, 2, 3, …, 31, and when the 0 th bit of the 32-bit value is 1, the priority address output j is 00000; sending the priority address output j to a multi-path selector, and sending a monitoring effective mark j to a secondary priority content addressing memory bank;
the second-level priority content addressing memory bank receives the monitoring effective mark j, obtains a 32-bit monitoring effective mark data packet, and generates a monitoring effective mark and an effective address high bit; if all the 32-bit monitoring valid flag data packets are 0, the monitoring valid flag is 0, otherwise, the monitoring valid flag is 1; when the k bit of the 32-bit monitoring valid flag data packet is 1 and the 0 th bit to k-1 bit are 0, the upper bit of the effective address is a 5-bit binary system of k, wherein k is 1, 2, 3, …, 31, and when the 0 th bit of the 32-bit monitoring valid flag data packet is 1, the upper bit of the effective address is 00000; sending the high order bits of the effective address to a multi-way selector;
the multiplexer receives the high order of the effective address and the priority address output j, and outputs the priority address output j corresponding to the high order of the effective address as the low order of the effective address.
The monitoring granularity can be configured, and a plurality of discontinuous address spaces can be monitored.
Compared with the prior art, the invention has the advantages that:
(1) the invention solves the problem of overlarge time overhead of the current manual design circuit by automatically generating the C unit circuit structure based on the combinational logic output interface, and has the advantage of realizing the reinforcement of the C units of the combinational logic units in batch;
(2) the invention uses two-stage priority content to address the memory bank, compared with the sequential query mode, the invention has higher query efficiency, compared with the one-stage query method of direct parallel query, the invention has higher evaluation frequency;
(3) the structure of the invention can monitor a plurality of discontinuous address spaces, the monitoring granularity can be configured and selected, the compromise optimization of the monitoring range and the monitoring granularity is realized, and the invention has good use value.
Drawings
FIG. 1 is a diagram of the overall circuit configuration of the present invention;
FIG. 2 is a diagram of a content addressable memory bank architecture.
Detailed Description
A hardware monitoring circuit for recording access address history overcomes the defects that the access address history of a traditional processor cannot be recorded, multiple discontinuous address spaces can be monitored by adopting a two-stage priority content addressing memory bank, the monitoring granularity can be configured and selected, compromise optimization of the monitoring range and the monitoring granularity is realized, and hardware support is provided for a data information synchronization process after a single computer in a hot backup computer is out of step.
The monitoring area configuration unit is used for configuring a monitoring address range, a monitoring address granularity and a monitoring enable according to the external task requirement, sending the configured monitoring address range, the configured monitoring address granularity and the configured monitoring enable to the arbitration control unit, and configuring a monitoring start address register and a monitoring end address register according to the configured monitoring address range, wherein the configuration value of the monitoring start address register is smaller than that of the monitoring end address register; the granularity of the monitoring address is 16n bytes and not more than 1024 bytes, wherein n is an integer; the monitoring granularity can be configured, and a plurality of discontinuous address spaces can be monitored.
And the arbitration control unit is used for monitoring the validity of the write enable signal of the bus to be monitored, judging the granularity of the monitored address when the address to be monitored is in the range of the monitored address and the write enable signal of the bus to be monitored is valid, generating the (n + 8) th bit to the (n-1) th bit which mark the validity of the memory write signal and the write address of the address to be monitored if the granularity of the monitored address is 16n bytes, totally 10 bits, and sending the mark memory write signal and the write address to the mark bit counting unit and the mark memory.
The marking memory is used for receiving a writing signal and a writing address of the marking memory to carry out marking storage, when the writing signal of the marking memory is effective, the bit position corresponding to the writing address is set to be 1, and the rest bit positions are unchanged; sending the numerical values corresponding to 1024 bits in the tag memory to a tag bit counting unit; and continuously packaging 32 numerical values corresponding to 1024 bits in the tag memory to obtain 32 numerical value packets, and respectively sending the 32 numerical value packets to the 32 priority content addressing memory bank.
And the marking bit counting unit receives the numerical values corresponding to 1024 bits in the marking memory, a writing signal of the marking memory and a writing address, and adds 1 to the marking bit counting unit when the writing enable signal is effective and the bit in the marking memory corresponding to the writing address is 0.
The method comprises the steps that priority content addresses a memory bank j, wherein j is a positive integer not larger than 32, a 32-bit numerical value packet is received, and a monitoring effective mark j and a priority address output j are generated; if all the 32-bit numerical value packets received by the priority content addressing memory bank j are 0, the monitoring valid flag j is 0, otherwise, the monitoring valid flag j is 1; when the k-th bit of the 32-bit value is 1 and the 0 th bit to k-1 bit are 0, the priority address output j is a 5-bit binary of k, where k is 1, 2, 3, …, 31, and when the 0 th bit of the 32-bit value is 1, the priority address output j is 00000; the priority address output j is sent to the multi-path selector, and the monitoring effective mark j is sent to the second-level priority content addressing memory bank.
The second-level priority content addressing memory bank receives the monitoring effective mark j, obtains a 32-bit monitoring effective mark data packet, and generates a monitoring effective mark and an effective address high bit; if all the 32-bit monitoring valid flag data packets are 0, the monitoring valid flag is 0, otherwise, the monitoring valid flag is 1; when the k bit of the 32-bit monitoring valid flag data packet is 1 and the 0 th bit to k-1 bit are 0, the upper bit of the effective address is a 5-bit binary system of k, wherein k is 1, 2, 3, …, 31, and when the 0 th bit of the 32-bit monitoring valid flag data packet is 1, the upper bit of the effective address is 00000; the high order bits of the effective address are provided to a multiplexer.
The multiplexer receives the high order of the effective address and the priority address output j, and outputs the priority address output j corresponding to the high order of the effective address as the low order of the effective address. For example, if the upper bits of the effective address are 00000, the priority address output 0 is selected as the lower bits of the effective address, and if the upper bits of the effective address are 00110, the priority address output 6 is selected as the lower bits of the effective address. The invention will be explained and explained in detail below with reference to the drawings.
The whole circuit structure of the access address hierarchical monitoring method is shown in figure 1, and the circuit structure comprises a monitoring area configuration unit, an arbitration control unit, a marker bit counting unit, a marker memory, a two-stage priority content addressing memory bank and a multiplexer.
The monitoring process is as follows: after resetting, the numerical values of the tag memories are all '0', when the write enable to be monitored is valid, and simultaneously the write address to be monitored is in the valid interval of the monitoring configuration area, the tag memory mapping bit corresponding to the write address to be monitored is written into '1', the tag bit counting unit is added with 1, the relationship between the write address to be monitored and the tag memory mapping bit can be configured by the monitoring granularity register, when the same address to be monitored is repeatedly written, the counting value of the tag bit counting unit is unchanged, and after the monitoring information is read out, the corresponding RAM mapping bit is written into '0'. Each unit of the circuit structure is designed in detail as follows:
a monitoring area configuration unit:
the module may configure the range, granularity, monitoring enable of the monitoring address. Each monitoring area configuration unit comprises a monitoring start address register and a monitoring end address register, when the configuration value of the monitoring start address register is smaller than that of the monitoring end address register, the configuration is effective, and the structure can monitor the address write access condition in the configuration address range. As shown in fig. 1, there are four monitoring area configuration units, and each monitoring area configuration unit has an independent enable configuration bit, so that the structure can monitor four non-consecutive address spaces. The monitoring region configuration unit may configure a monitoring granularity register that may make a reasonable trade-off between the range to be monitored and the granularity to be monitored. The following formula is satisfied between the range to be monitored, the granularity to be monitored and the capacity of the marking memory:
monitoring range/granularity-monitoring tag memory capacity
Table 1 shows the relationship between the configuration value of the monitor granularity register and the monitor granularity:
(II) an arbitration control unit:
the module is used for arbitrating and gating a plurality of monitoring area configuration units, generating a write signal and a write address of the mark memory by monitoring a bus write enable signal and the write address, and realizing the read-write control of the mark memory.
(III) a mark bit counting unit:
the flag bit refers to a specific bit of the flag memory corresponding to the address to be monitored through the monitor granularity register. And the mark bit counting unit is used for realizing the statistics of the variation of the address to be monitored. And when the write enable to be monitored is valid, the write address to be monitored is in the valid interval of the monitoring configuration area, and the mark bit is not written yet, namely the corresponding data of the mark memory is '0', and adding 1 to the mark bit counting unit.
(IV) marking the memory:
the module is used for storing the changed information of the address to be monitored, when the content of the address to be monitored is changed, the corresponding bit in the mark memory is 1, otherwise, the bit is 0.
(V) priority content addressing memory bank:
the content addressable memory banks differ from the conventional RAM memory structure as shown in fig. 2. In the scheme of the invention, the matching data of the content addressing memory bank is simple and only has one bit, so that the structure of the priority content addressing memory bank is ensured not to be too complex, meanwhile, for the condition that a plurality of addresses are matched with the data to be matched in one memory bank, the output effective address is the matching address with the highest priority, if no data of the address in the whole priority content addressing memory bank can be matched with data '1', the matching mark outputs '0', otherwise, outputs '1'.
The invention adopts a two-stage priority content addressing memory bank, the input of the first stage is the data of a marking memory, which is equivalent to the block statistics of the data of the marking memory, and the output is a low-order effective address and a matching mark; the input of the second-level priority content addressing storage body is a plurality of matching marks of the first-level priority content addressing storage body, and the output is a high-order effective address and a matching mark of the whole system.
Compared with a sequential query mode under the control of a state machine, the two-stage priority content addressing memory bank query method benefits from the parallelism of query and greatly improves the query efficiency, and compared with a one-stage query method for direct parallel query, the method reasonably divides the query pipeline stages and improves the working frequency of the whole system.
(six) a multiplexer:
the multiplexer module is used for gating and outputting effective addresses of the priority content addressing memory banks of the first level according to high-order addresses from the priority content addressing memory banks of the second level.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (2)
1. A hardware monitoring circuit for recording memory access address history is characterized by comprising a monitoring area configuration unit, an arbitration control unit, a mark memory, a mark bit counting unit, a priority content addressing memory bank j, a secondary priority content addressing memory bank and a multiplexer;
the monitoring area configuration unit is used for configuring a monitoring address range, a monitoring address granularity and a monitoring enable according to the external task requirement, sending the configured monitoring address range, the configured monitoring address granularity and the configured monitoring enable to the arbitration control unit, and configuring a monitoring start address register and a monitoring end address register according to the configured monitoring address range, wherein the configuration value of the monitoring start address register is smaller than that of the monitoring end address register; the granularity of the monitoring address is 16n bytes and not more than 1024 bytes, wherein n is an integer;
the arbitration control unit is used for monitoring a write enable signal of the bus to be monitored, judging the granularity of the monitored address when the address to be monitored is in the range of the monitored address and the write enable signal of the bus to be monitored is valid, if the granularity of the monitored address is 16n bytes, generating a mark memory write signal which is valid and the write address is from the (n + 8) th bit to the (n-1) th bit of the address to be monitored, wherein the bit is 10 bits in total, and sending the mark memory write signal and the write address to the mark bit counting unit and the mark memory;
the marking memory is used for receiving a writing signal and a writing address of the marking memory to carry out marking storage, when the writing signal of the marking memory is effective, the bit position corresponding to the writing address is set to be 1, and the rest bit positions are unchanged; sending the numerical values corresponding to 1024 bits in the tag memory to a tag bit counting unit; packing the numerical values corresponding to 1024 bits in the tag memory for 32 times in a continuous way to obtain 32 numerical value packets which are respectively sent to a 32-priority content addressing memory bank;
the marking bit counting unit receives numerical values corresponding to 1024 bits in the marking memory, a marking memory writing signal and a writing address, and adds 1 to the marking bit counting unit when the writing enable signal is effective and the bits in the marking memory corresponding to the writing address are 0;
the method comprises the steps that priority content addresses a memory bank j, wherein j is a positive integer not larger than 32, a 32-bit numerical value packet is received, and a monitoring effective mark j and a priority address output j are generated; if all the 32-bit numerical value packets received by the priority content addressing memory bank j are 0, the monitoring valid flag j is 0, otherwise, the monitoring valid flag j is 1; when the k-th bit of the 32-bit value is 1 and the 0 th bit to k-1 bit are 0, the priority address output j is a 5-bit binary of k, where k is 1, 2, 3, …, 31, and when the 0 th bit of the 32-bit value is 1, the priority address output j is 00000; sending the priority address output j to a multi-path selector, and sending a monitoring effective mark j to a secondary priority content addressing memory bank;
the second-level priority content addressing memory bank receives the monitoring effective mark j, obtains a 32-bit monitoring effective mark data packet, and generates a monitoring effective mark and an effective address high bit; if all the 32-bit monitoring valid flag data packets are 0, the monitoring valid flag is 0, otherwise, the monitoring valid flag is 1; when the k bit of the 32-bit monitoring valid flag data packet is 1 and the 0 th bit to k-1 bit are 0, the upper bit of the effective address is a 5-bit binary system of k, wherein k is 1, 2, 3, …, 31, and when the 0 th bit of the 32-bit monitoring valid flag data packet is 1, the upper bit of the effective address is 00000; sending the high order bits of the effective address to a multi-way selector;
the multiplexer receives the high order of the effective address and the priority address output j, and outputs the priority address output j corresponding to the high order of the effective address as the low order of the effective address.
2. The hardware monitoring circuit for recording the memory access address history as claimed in claim 1, wherein: the monitoring granularity can be configured, and a plurality of discontinuous address spaces can be monitored.
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