KR920001594B1 - Interface board for computers - Google Patents

Abstract

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Description

Interface board for computer

1 is a functional block diagram of a board assembly of the present invention.

2 is a functional diagram of a transmit / receive block of a functional board assembly.

3-8 are diagrams of each of the electrical diagrams of the board.

* Explanation of symbols for main parts of the drawings

1: input memory area 2: central memory area

3: Central memory 4: Communication memory

5: transmit-receive block 6: microprocessor

12: Error checking block 14: Interrupt block

108: melt multiplexer 110: bistable circuit

135, 136: address line 151: NAND gate

159: Meltplexer-Decoder 166: Counter

222: discharge capacitor 232: oscillator

236: bistable circuit

The present invention relates to a computer interface board for use in a facility composed of a personal computer acting as an intelligent terminal and a non-intelligent terminal constituting a medium / large computer acting as a controller.

The board is operated by four blocks having an input memory area, a central memory area, a central memory and a dual port. In addition, a transmit / receive block and a processor are provided. All of the above devices allow the board to handle the communication protocols, allowing the personal computer to have a better response time, while at the same time separating between the terminal devices of the workstation.

In facilities or systems with medium / large computers, it is desirable to use intelligent terminals. When such an intelligent terminal is used, the degree of interaction between the medium / large computer and the terminal will be controlled to the maximum by the computer's basic software, or the computer will be able to It will be enough to control the channel of the dialogue). In this sense, Applicant has developed a personal computer (PC) that can act as an intelligent terminal in such a way that the resources of a medium / large computer can be used over a communication channel in a predetermined format. The set of functions provided by a medium / large computer is configured like an intelligent terminal, and providing a file service for the intelligent terminal is called FSERV. Of course, this FSERV does not only provide access to files. In other words, FSERV is a logical unit in that a dialog exists between a PC and a medium / large computer.

The present invention has designed a diagram in which a PC can be replaced by a non-intelligent terminal as well as an intelligent terminal. According to this diagram, a medium / large computer sees the PC as a set of three terminals. In other words,

Logical Terminal (Fserv)

Interactive display screen type terminal (indicator)

-An interactive printer type terminal (printer).

This group of three terminals is a so-called Office Work Station (O.W.S).

Communication between a medium / large computer and a terminal can be carried out via a serial interface- tine (SIF) communication channel, and can be made to all terminals via the channel, but when using a logic verification system, only one of them will respond.

In the dialog, the initiating part belongs entirely to the controller. In the present invention, since the medium / large computer becomes the controller, a periodic inquiry procedure is established between the computer and the terminal. The fact that a line is shared by multiple terminals means that the overall response rate is determined by the response speed of each terminal.

An object of the present invention is to provide a board designed to be used as an interface between an SIF type communication channel and a PC bus, the main object of which is to provide a better response characteristics to the PC by processing the communication protocol with the workstation (WSC) described above. At the same time, it maintains a dialog with a medium / large computer.

The board separates the three devices in the workstation (W.S.C) so that the data is completely separated when connecting or interfacing with the PC.

The board is provided with the following device in a standard format for a PC.

A microprocessor (operating frequency is 3.75 MHz) that performs a fixed program (firmware: firmware) that processes the logic of the protocol and maintains a dialog for the PC,

4 kilobytes of electrically programmable read-only memory (EPROM) designed for transmitting and receiving lines and for preliminary analysis of information using physical devices (hardware). Block of a specific circuit consisting of

-8 kilobytes of static random access memory (RAM),

-8 kilobytes of EPROM,

One kilobyte of static RAM is provided with two simultaneous access ports that form the communication mechanism between the interface and the bus of the PC.

Advantages of the boat as the subject and object of the present invention are as follows.

A. High speed analysis and fast response of information to operate to the physical characteristics of the channel and to make the best use of the lines (as the present invention handles lines that can be shared between multiple terminals).

B. Has sufficient processing capacity to handle communication protocols and distribute information among the three constituent units that form a workstation (OWS), freeing the PC's processor from heavy loads It is possible to prevent the dialogue with the computer from being degraded, and also to include the information part in the process on the board itself.

C. Have adequate storage capacity to ensure that information in motion is effectively retained.

The presence of intermediate data storage registers results in better average travel.

Because of the processing capacity described above, flexibility suitable for many communication protocols is obtained, and in addition to the standard protocol required for the workstation (O.W.S.), it is possible to process other protocols under the same physical conditions. By all these matters, the interface board of the present invention having very good functional characteristics is obtained, and has a good life and characteristics for the intended function. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The present invention consists of a board for use as an interface between a communication channel and a bus of a personal computer (PC), which board is in accordance with the functional block diagram shown in FIG. 1 is composed of four functional blocks for storing information for a number of purposes, the four functional blocks comprising an input memory area or buffer (1), a central memory area or buffer (2), and a central memory (3). ) And dual port communication memory (4).

For transmission and reception there is a special block 5 which can write directly to the input storage area 1 or communicate with the remaining functional blocks via the processor 6.

In the installation of the above-described device, the input storage area 1 fixes the maximum length of a block that can be processed by the interface as the first receiving device of the information, and this input storage area 1 is also provided by the system. Common to all three building units. Here, the configuration unit is an intelligent terminal (Fserv). Interaction terminal (indicator), emergency call terminal (printer). The three units are combined into a PC to form a workstation (O.W.S.) together.

The central memory area 2 provides an effective retention period as an intermediate memory area (note that the input memory area 1 is common to the three constituent units forming the OWS). It is convenient to have a usable area for each unit to which copying of the input storage area is made free.

The communication memory 4 has two ports with simultaneous access from the interface and a PC, and constitutes an information exchange mechanism therebetween.

The memory provides a mechanism for activating a signal in one port from an opposing port, and the signal can be used to perform a physical communication protocol so that the interface can generate an interrupt at the PC and also need attention to the interface. It can be displayed.

The central memory 3 contains the program and the necessary control variables, while the processor 6 checks for line instructions using interrupts generated by the transmit / receive block 5 and the dialog with the PC Using polling on the interface part, it is maintained by an interrupt on the PC side.

The transmit / receive block 5 is constructed according to the functional diagram shown in FIG. 2, where the dialgram shows two different branches, one corresponding to the transmission (to the right) and the other In response to reception (to the left), there is a first conditional block 7 of signals between the lines and the rest of the circuit.

In the second branch, there is a parity generating block 8 and another block 9 for the sequencing of the word, and the block has a characteristic of transmitting a fixed number of bits per line to the processor to fulfill one single instruction. The entire paritter (in this case the middle) is generated automatically.

At the destination, after the appropriate serial / parallel conversion 10 the signal is verified as follows.

Parity checking and direction testing of the terminal (the operation is carried out in block 11).

-Transmission error checking (performed by block 12). The error is memorized so that the processor can perform the required operation when interrupted.

Pre-decoding is performed by the EPROM at block 13, and if the information is control information, proceed to block 14 to inform the processor to take appropriate action, while the information is data. If so, it is sent to the block 15 and written directly to the input storage area or buffer 1.

In accordance with the above description, the function shown in the electric circuit diagram partially shown in FIGS. 3 to 8 will be explained by the operation described below.

1. Receive and serial / parallel conversion

Search for "bit" logic

The signal reached by the line (which can be greatly attenuated if the sender is at a distance) is retrieved by an operational input amplifier (see also FIG. 3), and the amplifier sends the rememored signal onto pin 17. To pass on.

Circuits 18 and 19 are connected together to form a 16-bit shift register, the function of which is transferred by an operational input amplifier and entered by pins 20 and 21 of circuit 19. One degree, the logical value of the signal, is to search for zero.

Logic detection of bits is accomplished by sampling the input signal with a clock of 15 MHz, which duplicates the signal reaching pins 20 and 21 of circuit 19 every 66.6 ns at the next position of the shift register, The positive edge at the output is achieved by generating an edge after 399.6 ± 66.6 ns on pin 22 of circuit 19. The edge is used as a pulse or bit acknowledgment signal or strobe, where the value of pin 23 of circuit 19 determines the logic value of the bit. To connect the circuit, the line is activated and the correct value is retrieved from the received first completion bit.

[Counting zero]

According to FIG. 3, the circuit 24 is charged to counting zero by each bit-checking pulse of pin 22 of circuit 19 providing a clock pulse to the counter, the counter being operated during the next two operations. Performs one action. Counting: If pin 25 is in the 1 state, i.e., pin 17 of the operational amplifier 16 is in the 0 state, it indicates that the received bit is zero. Loading: If pin 25 is in the 0 state, it indicates that the received bit is one.

As long as 1 is received before the counter reaches the end, the counter is reloaded, which causes the counter to be in the same counting position.

The counter reaches the fifteenth state until fourteen consecutive zeros are received, with the -CYO signal blocking the counter until a one arrives that pulls up the pin 26 and reloads the counter. Generate. The -CYO signal is active after 14 zeros have been reached until 1 is reached, that is, at least 14 zeros are countered, which is preceded by words with zeros at the end of 14 zeros first. Is necessary to anticipate.

[Bit Counting of Words]

As can be seen in FIG. 3, a circuit (counter) 27 is used to count the bits of each word following the fourteen zeros, which means that the clock pulse of the counter is pin 22 of the circuit 19. By providing a bit acknowledgment pulse on the device to take one action during the counting or loading of the counter depending on the state of the pin 28.

When pin 26 of counter 24 goes high, NOR gate 29 generates zero at the load input of counter 27, which reloads into two states upon receiving the corresponding clock pulse edge. do. When the output of the counter 24 goes low, the counter 27 counts 14 bits and causes a word strobe confirmation pulse at the NAND gate 30 to be generated. At the same time, the with strobe confirmation pulse reloads the counter to start bit counting the next word when signal CYW is activated, and signal CYW places zero through the gate 29 at the load input.

Assuming a word strobe confirmation pulse is provided to pin 31 of NOR gate 30, the edges affecting outputs 32, 33 of circuit 18 using inverter 34 are bistable circuit 36. A pulse is generated on pin 35 of. In this way, a word confirmation pulse of 132 ns width is obtained.

[Parity Checking]

The parity checking of the word being reached is performed by the bistable circuit 38 shown in FIG. 3, where the clock of the bistable circuit passes through the inverter gate 39 and the bit strobe on the pin 22 of the circuit 19. It is carried out by obtaining from the confirmation signal. Inputs 40 and 41 of the bistable circuit 38 are connected to pins 23 of the circuit 19 having a logic value of bits.

When the input bit is 1, the bistable circuitry toggles, and when it is 0, there is no change. However, since the number of 1 should be odd and start from 0, the negative output of the bistable circuit 38 should be 1 unless there is an error. A signal-PRIT of 1 indicates an error.

The reset of the parity check bistable circuit is implemented when the output of the NAND gate 43 is zero, which occurs when the reset is ready to begin counting bits of a new word, where the output of circuit 29 is zero. do. In this case, the outputs 44, 45 and the gate 46 of the circuit 19 erase the pulses of the bistable circuit via the NAND gate 43 (see FIG. 3).

[0]

Again in FIG. 3, when the information of 14 zeros has been stored, the output of the gate 43 is input to the bistable circuit, and the pulse edge for resetting the parity check bistable circuit (the bistable circuit) It is used to store the output state of the counter 24 input by the pin 48 in 47.

The fourteen zero marks remain active until the next word begins, from the start of receiving the first bit of these fourteen zero words.

[Serial / parallel conversion]

In FIG. 3, circuits 40 and 50 constitute a 16-bit shift register, with a clock provided with a bit strobe confirmation pulse from pin 22 of circuit 19, with an input of circuit 50 being provided. It is made from the pin 23 of the circuit 19 by pins 51 and 52. In this way, the logic content of the 14 bits of the word is stored.

The bit corresponding to the address is input to the comparator 53 and compared with the selection signal at the output 54 at the NAND gate 55, the output of which is applied to the SELESP signal that is activated when the address is 1-1-1. Corresponds.

The bits corresponding to the output 56 of the circuit 50 and the output 57 of the circuit 49 are combined at the NOR gate 58, and for all control words CW, the two bits are not only zero, Since it is irrelevant to the following decoding, one of them is 1 to avoid a corresponding error.

[Match signal (MATCH)]

The coincidence signal indicates whether the address included in the control word CW coincides with the address selected by the small switch, and this coincidence signal is obtained at the output of the NOR gate 59 and starts to be activated from the output of the comparator 53 or Or may be activated when specifically selecting the output of the circuit 55.

The comparator 53 has, on the one hand, a bit corresponding to the address of CW generated from the circuit 49, and on the other hand has a value of 1 or 0 selected by the small switch.

The PRIT signal is input by pin 60 of the comparator, causing the signal to zero. A comparison is made by pin 61 when fourteen zero signals arrive, and thus the MATCH signal can be activated only when a word with fourteen zeros preceding and no parity error is received.

Another means of activating the MATCH signal is done by a particular address, in which case all stations are affected and need not be compared.

[Specific choice]

When the control word CW has an address of 1-1-1, the SELESP signal is activated, and four input signals are obtained from the NAND gate 55, three of which are three of the CW addresses generated from the circuit 49. Corresponding to the bit, and the other corresponds to the bit given by the NAND gate 62. Special selection is only possible when 14 zero signals are active and no parity error is present.

2. Decoding and Checking Errors

[EPROM Decoder]

In FIG. 4, the decoding of the control word is performed using the EPROM 63 (see FIG. 4), and the following signal arrives at the address input of the EPROM. That is, the output corresponding to the shift register formed by the circuits 49, 50 and 2 is excluded, and the output of the address is excluded, and is output by the combination of the circuits 64 and 65 by the NOR gate 58. Receive And a signal on pin 66 of the circuit 63 indicating that the word to be decoded is the data ESCR is reached, which is also the specific selection signal SELESP.

The data output from the EPROM can be divided into the following two groups.

a) (67, 68) is a signal with a specific function, b) (69, 70) forms a command or error code stored in the circuit 71.

[Error checking]

With continued reference to FIG. 4, in the decoding process, it is necessary to check to see what type of error, and there are two types of error detection.

a) The first type is an error that the detected value is stored in the circuit 72 and can be read by the processor when interrupted. b) The second type is an interrupt generated when an error occurs and the data output of the EPROM 63 is generated. This is an error coded within (69, 70). The next signal provides a finite value of zero or one, and sets the error and resets the circuit 27. In other words,

TCKI, this signal is input by pin 73 and comes from the output of NAND gate 74. The signal is generated at the output 68 of the EPROM 63, filtered by the STRB signal (word confirmation pulse) and the MATCH signal (address match), to prevent the incorrect control word CW from being input. Used.

TK2, this signal is input by pin 75 and comes from the output of NAND gate 76. The signal is generated at the output 77 of the EPROM 63, filtered by the STRB signal, and used to prevent an incorrect dataword DW from being input.

TKP, this signal is input by pin 78 and comes from the output of NAND gate 79. The signal is generated by a --PRIT parity signal and filtered by a strobe STRB confirmation signal or pulse. It is determined whether fourteen zeros are received (in the case of CW) or data given by the NOR gate 80 (in the case of DW). The signal is also used to prevent the input of words with parity errors that cannot contribute to any particular station.

-AUCK, this signal is input by pin 81 and comes from a circuit that constitutes direct memory access (D.M.A).

-BUCK, this signal is input by pin 82 and is used to clear the error recorded by AUCK.

The address decoder 83 of FIG. 7 generates the signal.

BTCK, this signal is input to the NAND gate 84 where the output is input to pins 85 and 86 of the circuit 72. The signal is used to erase errors recorded by --TCK1, --TCK2 and --TCKP and is generated by the address decoder 83 of FIG. The transmission error is also discarded by the signal BSELES, which is generated by the input of the stored command.

[Record command]

When a write command is recognized in succession in FIG. 4, the necessary operation causes the continuous word to require DMA so that it can be stored in memory, while instructing the EPROM to analyze the continuous word as data. The output 67 of the EPROM 63 is activated by a write command, conveniently filtered by signals STRB and MATCH, and generates a signal -SELES on pin 87 of the circuit 88.

The signal is maintained in circuit 72 when input by pins 89 and 90. To delete the indication, the BSELES signal is used, which is generated at the decoder 83 of FIG. On the other hand, the signal SELE is clocked on pins 93 and 94 of the two bistable circuits 91 and 92, and the bistable circuits 91 and 92 activate the signals WR and ESCR when the pressure is grounded.

The WR signal is used to issue a DMA request via the NAND gate 95 of FIG. 6, and the ESCR signal is input to the EPROM 63 by the pin 66, and is in a state for analyzing a word as a data word DW. To be.

The signal ESCR is deactivated when 14 zeros are reached or reset occurs using the CYORES signal appearing from the NAND gate 96 of FIG. The WR signal is also deactivated by the signal, but may be deactivated by a transmission error via the NAND gate 97.

[Interrupt request]

In order to inform the processor about the input of a new command or to inform the processor of a particular error code, EPROM 63 activates the output 98 shown in FIG. 4 and proceeds to the next two routes for interrupt requests. Let's do it.

a) The first route passes through gate 99 and is filtered by signals STRB and MATCH, which route is a normal route to inform the processor of the arrival of a new instruction or to signal the processor to a specific error at the input of the control word CW. Inform.

b) The second route passes through gate 100 and is filtered by signals ESCR and STRB, which route is used to inform the processor of any particular error code at the input of the dataword DW.

Signal-INTCW on pin 101 of circuit 102 corresponds to the interrupt line, which is activated by the output of NAND gate 103 coupling the input of gates 99 and 100.

The signal -INTCW is inactivated by the -LEST signal generated by the address decoder 104 of FIG.

In addition to the activation of the -INTCHW signal, the output of the NAND gate 103 loads the circuit 71 with the code generated by the EPROM 63 at the outputs 69 and 70 and the information held in the circuit 72. do. Here, when the processor recognizes the interrupt and activates the -LEST signal, it can be read from the connected computer by the output from the circuit 71.

3. Line output

[14 bit acquisition of word]

Communication is implemented as a word with 14 bits, and if the protocol requires the processor to have an 8-bit bus, some address lines are decoded for a single input-output indication in terms of decoding the term. Must be used to generate all bits. In addition, the device itself performs parity calculation.

In order to serialize the 14 bits of a word, parallel inputs and serial outputs formed by circuits 105 and 106 are loaded into the shift registers (see Fig. 5).

The first bit is the start bit and is always 1 and assigned to address line 134. The second bit indicates whether the device status word DSW or data word DW is to be processed and is designated in the address line 133.

In the case of DSW, bits 3 through 10 correspond to the address and status of the station, and in the case of DW, 8 bits of data. The bits are assigned to the data bus from the processor.

In the case of a DSW, the eleventh bit corresponds to a device type instruction, in which case it is fixed to 1, whereas in the case of a DW, it corresponds to a parity bit of eight data bits. In order to generate an appropriate value for the bit, a parity generator 107 and a multiplexer 108 are provided, parity for 8 bits of data input to parity generator 107 using address lines 135 and 136. Or 1 is selected.

In the case of a DSW, the 12th through 13th bits correspond to the identification of the device, which is always 1, whereas in the case of a DW it is always 0. The bits are combined and assigned to address line 133 (see FIG. 5).

The fourteenth bit corresponds to the total parity of the word, and in the case of DW, the value is always fixed, even if the data has its own parity bit and the rest of the value is constant. On the other hand, in the case of DSW, the value depends on parity of 3 to 10 bits. In all cases of DW and DSW, an appropriate value can be obtained when using lines 135 and 136 corresponding to the select input of multiplexer 108.

To transmit the DSW, if the third to ten bits have even parity, the fourteenth parity bit is zero, and if the parity is an odd number, it is one (if corresponding to the output 108 of the circuit 107). The confirmation is based on the fact that the remaining bits which are not input to the parity generating circuit are all ones.

[Amplitude Coding of Bits]

For transmission, each bit is modulated as follows. In other words, the start timing of the bits is fixed. The bit starts at the high level and goes low after a time of 1 or 0.

In order to obtain this type of modulation, the bistable circuit 110 of FIG. 5 is used, and by pins the direct output of the binocular circuit is directed to a line exciter, with three different consecutive positions: Have

a) Firstly, there is a high level and becomes a part that is common to the transmission of 1s and 0s.

b) Secondly, the output depends on the value being sent.

c) Thirdly, it is at the low level and corresponds to the last part that is common to all the bits.

To generate the appropriate time for each state of bistable 110 shown in FIG. 5, a 16-bit shift register with serial input and parallel output is used, which is formed by circuits 112 and 113, where Zero pulses are made to cycle. Edges that occur at multiple outputs of the shift register cause a corresponding change in bistable state. Initially, shift registers 112 and 113 are erased before transmission is initiated. In this way, 1 appears at the inputs 116 and 117 of the shift register 113 through the gates 114 and 115, and when the 1 reaches the pin 118 of the circuit 112, the output of the NAND gate 115 is zero. do. In the next clock, 0 is introduced into the shift register, and the output of the gate 115 becomes 1 (see FIG. 5).

In this way, zero pulses circulate and remain in the circuit formed by the shift register and gates 114 and 115. When zero pulses pass by the outputs 119, 120 of the circuit 113, negative pulses are generated by the gates 124, 125 and operate at the input of the bistable circuit, providing a value of zero or one. When the zero pulse reaches the output 12 of the circuit 113, it provides a clock pulse to the bistable circuit 110, which duplicates the output, and the output value of the shift register 106 appears at this time, the value being at this moment. Corresponds to the bit to be sent to.

When the zero pulse reaches the output 122, 123 of the circuit 112, a negative pulse is generated via the gates 126, 127, 128 that operate the erase input of the bistable circuit.

When zero pulses circulating in the registers 112 and 113 reach the outputs 116 and 117 of the register 113, negative pulses are generated via the rates 114 and 115, which, on the one hand, cause zero pulses to flow into the shift register. On the one hand, the clock impulse is provided to the circuits 105 and 106 so that the value of the next bit is transmitted to be provided in the output 129 of the circuit 106.

[Start transfer]

Transmission start consists of preparing a line generated by the -INTRA signal from the address decoder of the terminal 104 of FIG. The signal causes the bistable circuit 130 to be initiated, and the output of the bistable circuit operates the input of the line driver 131.

The following operation executes a write instruction to the terminal, which is performed for address bits that are redundant in terminal selection and for appropriate values depending on the type of word required to be transmitted. The command activates the -CSRS signal by the gate 132, on the one hand, the loading of the shift registers 105, 106 operating on the input 137, and on the other hand, the synchronization circuit of the transmission clock.

Impulse strings from the transmission clock are introduced by inputs 138 of registers 112 and 113 which form shift registers in which zero pulses circulate. NAND gate 139 allows the impulse column to be advertised. This pass must be allowed at an appropriate moment, so that jittering should not occur at the clock inputs of the registers 112 and 113. The impulse string input of the clock should be allowed when the latter is at a low level.

Activation of the signal CSRS causes the inputs 140 and 141 of the bistable circuit 142 to have values of 0 and 1, respectively. At the next negative edge of CK15M, the bistable circuit resets itself and the subsequent bistable circuit 143 resets itself. NAND gate 144 does not change the output. Because we didn't lock the two inputs to one.

When deactivation of the CSRS occurs, the inputs 140 and 141 of the bistable circuit 142 have values of 0 and 1, respectively. At the next negative edge of CK15M, the bistable starts, and the reset input of the bistable circuit 147 is activated through the gate 144. At the next negative edge of CK15M, bistable circuit 143 is set and the transmission clock is itself enabled.

At the moment the clock is enabled by itself in registers 112 and 113, a 1 (given from gate 115) present on the input of pins 116 and 117 of register 113 is output to outputs 118 and 148 of register 112. It proceeds until it arrives, causing negative pulses flowing in register 113 to continue to circulate in the shift register.

[Transfer process]

Once the command of the input / output terminal is executed, the above-described mechanism is started by the signal CSRS. To send the next word, the processor provides a new indication to the input / output terminal without knowing whether the preceding word has been transmitted in its entirety. During word transfer, the processor activates the WAIT signal across the output 149 of the NAND gate 150. In addition, the possibility of loading the shift registers 105 and 106 via the NAND gate 151 is prohibited.

The signal CSRS is activated in line state provided by the signal ENLIN of pin 152 of bistable circuit 130, the word is transmitted at the clock enabled by gate 139, and WAIT until the transfer processor is finished. The signal is activated.

The input circuit checks the end of the word using the same bit counter used to provide the strobe confirmation pulse of the received word. The counter always starts from state 2, for each transmission must be preceded by reception, and the last bit is loaded to pull up.

When 14 bits of a word were transmitted before zero circulating in the registers 112 and 113 reached the output 148 of the register 112, the input circuit activated the signal CYW, and when the CYW signal was generated, paired one. It is arranged in the input 140 of the stabilizer circuit 142. At the negative edge of the next CK, the 15 gates 139 are closed, interrupting the WAIT signal and initiating the processor for the next transmission that enables reloading of the circuits 105 and 106.

Once all the words in the message have been transmitted and the last word has been transmitted completely, the signal FITRAS appearing from the circuit of the address decoder of the terminal 83 of FIG. 7 is activated. The signal erases the line and initiates a bistable state of the clock synchronizing circuit and the shift register.

4. Line Memory Direct Memory Access (DMA)

[Direct Memory Access (DMA) Request]

A DMA request is generated when a write command is received over the line. In this case, the WR signal is activated as described in the section on decoding. DMA is performed by stealing cycles. That is, a DMA is required for each word entered, and the request is canceled each time it is written.

The -BUSRQ signal requiring DMA starts at pin 153 of bistable circuit 154 (see FIG. 6). Upon receiving the signal, the reset of the bistable circuit by the pin 155 is activated via the NAND gate 95.

In order for the processor to have enough time to recognize the above fact, when the input word bit counter is state 11, the request for DMA is fulfilled.

The signal BITX is generated from the output of the counter 27 of FIG. 3 and the gate 156 of FIG. 2 and used to fulfill the request for DMA while the WR signal is active.

When the processor recognizes a DMA request and activates the signal -BUSAK, the following actions occur:

The processing of the bits corresponding to the data passed through the circuit 158 of FIG. 6 via two successive inverters 157 (FIG. 6) used to strengthen the -BUSAK signal is performed by the shift register 161 (FIG. 5). This is done on the common data connection line for the output of. Similarly, the output of the multiplexer-decoder circuit 159 (FIG. 6) is enabled to generate a control signal of the remaining portion of the circuit that forms the DMA.

The signal BUSACK at pin 160 of inverter 157 is used to separate the lines whose address is used to form a 14-bit word from the common connection, which is intended to reduce noise as shown in detail in FIG. The circuit 161 is used for the purpose.

[Other Types of Data]

Datawords transmitted by lines can be classified into two types according to information to be stored in a place register where information to be stored and information to be stored in an input memory area (buffer). A register is a memory area in which a host controller writes control information related to data.

Data and registers must go to the memory area assigned to them. The writing process always writes to the register first and then stores the data. The register may be written partially but always written continuously. To indicate which register is required, a specific dataword is sent, the contents of which are not intended to be stored, but indicate which register number should be used to write the next dataword DW.

In addition, a pair of registers exists where a start address is recorded, and data arriving at this start address must be stored. The recording processor from the host controller can be combined into the following operations. That is, the recording command is transmitted from the host controller. The interface recognizes the write command and activates the WR signal.

The next word is DW, which indicates from which register it will start being stored. The next DW is a register, starting from the register indicated above and continuously stored. When the data address register is written, a corresponding initialization is performed to accept the data. The next DW is recorded continuously until fourteen zeros have been reached, indicating another command. Three possible DW types (selection of registers, registers and data) are distinguished by the 12th and 13th bits.

[Register of register]

Once the DMA request is fulfilled, the BUSACK signal in circuit 154 (FIG. 6) activates the processor to recognize this and activate the signal BUSACK. This BUSACK signal passes through two inverters 157 and circuit 158. Then, the data bus is transferred to an 8-bit data bus of DW data. Thus, the output of the multiplexer-decoder 159 is set by itself.

The twelfth and thirteenth bits of the same type DW are input by the circuits 162 and 163 to the multiplexer-decoder 159, and the word STPR is also input.

When the DW corresponding to the register selection arrives, the output 164 of the multiplexer-decoder 159 is selected. The output 164 outputs the four least significant bits of the DW to the counter 166 when a strobe check pulse is generated. Pulses at the input 165 of the counter 166 which allows only 16 registers to be loaded).

The arrival of the next DW corresponding to the information about the register causes the output 167 of the multiplexer-decoder 159 to be selected. This activation enables the output of circuits 168 and 169 to pass through the address bus. Circuit 169 is set itself via gate 170.

The circuit 168 places the contents of the counter 166 between the outputs 171 and 172, where the contents are the number of registers desired to be written and zero to the outputs 173 to 174.

Circuit 169 zeroes outputs 175 and 176 and causes NAND gate 177 to have input zero. The signal at output 178 becomes 1 because the signal is an inactive output from multiplexer-decoder 159. Outputs 179 and 180 are fixed at zero. The strobe confirmation pulse causes a pulse to be generated at the output 181 of the multiplexer-decoder 159, which serves two purposes.

a) on the one hand provides selection to the memory 183 in FIG. 7 via the gate 184 in FIG. 7 and on the other hand provides a clock pulse to the bistable circuit 154 which deactivates the -BUSRQ signal. Activating signal SELD across gate 182.

b) Counting pulses are generated by pin 187 of counter 166 via inverters 185, 186 (FIG. 6) to allow the DMA write pointer to pass through the next register.

Although DMA can write 16 registers, in practice the protocol can specify that only register 7 can be written.

When attempting to populate the counter 166 by more than seven, the signal -AUCK is activated via the gates 188, 189 and 190 and held in the error memory circuit 72 of FIG. Similarly, with the clock impulse, the counter becomes 8 and the AUCK signal is activated via gates 188 and 189.

[Record data]

As soon as the register counter 166 passes through three states, when the gates 191, 192, 193 are set to enable the DARL signal, the strobe confirmation pulse is given and the output 181 of the multiplexer-decoder 159 is activated. The DARL signal pulses the inputs of the counters 195 and 196 to 194, which is loaded with eight bits of preceding data from the DW indicating the lower portion of the address where the data should be written.

Likewise, when the register counter passes four states, the DARH signal is enabled, and the four least significant bits of the DW are loaded for the strobe confirmation pulse counter 197. When the DW is received, the output 198 of the multiplexer-decoder 159 is activated to cause the output of the circuits 169, 199 to pass through the designated address bus. The signals on the outputs 200, 201 are the contents of the counters 195, 196, and the signals on the outputs 175, 176 are the last two bits of the counters 175, 176. This is because when the output of the multiplexer-decoder 159 is deactivated, the gate 177 keeps 1 at the other input. The signal at output 178 is zero with respect to output 198 of multiplexer-decoder 159.

When a wordstove confirmation pulse occurs, the output 202 of the multiplexer-decoder 159 is activated to activate the select signal -SELD, and also increments the counter 196 and pulls up in the case of counters 195 and 197. Increased by the transfer of state.

[Direct pointer reading of memory access tax "DMA"]

It is necessary to read the final state of the pointer so that the processor can consider the number of data written by the DMA. To this end, the circuits 203 and 204 pass the states of the counters DMA active signals -PNT0 and -PNT1 and to the designated data bus. The circuit 204 is used to allow the processor to read the signal arriving by the circuits 205, 206, and 207. The circuits 205, 206, and 207 come from the communication memory 4 having an address and a PC bus selected from the small switch msw. Indicates an INHC signal.

5. Central Processing Unit “CPU”

The processor 208 constitutes a central processing unit (CPU) of the apparatus (see seventh). The memory is composed of EPROM chips 209 and 183. The memory selection is performed by the decoder 210, and to make the selection, the signals -RD -WR and -MRQ are used as with the three most significant address lines.

The signal that causes the processor to direct the input or output to the write or read terminal is the output of circuit 104 for "in" and the output of circuit 83 for "out". The enable of the select signal -RD or -WR is used depending on how these signals correspond, and the signal -IORQ is also used, like lines 211 and 212.

The address used to activate the corresponding signal is irrelevant except in the case of the signal -CSRS, and causes the dataword or status word to be transmitted from the device along an address line not used for decoding.

6. Communication with PC Bus

Interface communication with the PC is carried out via the memory 4, which counts to two terminals or data ports and two address ports and is accessed at the same time. Similarly, the element 213 has the characteristic that when it is stored in one position, the output INTL is activated and when it is stored in another position, the output INTR is activated.

Signal INTR is inverted by inverter 214 and is coupled with one of the PC bus interrupt lines. In this way, if the interface wants to communicate, an interrupt may be generated. The signal INTL is directed to the input 215 of the circuit 204 of FIG. 6 and when the processor activates the PNT1 signal, the INTL signal can pass through the databus.

Although access to the common memory can be done at the same time, if access is done on the same bit, there may be conflict. In this case, the signal -BUSYL or -BUSYR of element 213 is activated depending on who first requested access. Signal -BUSYL activates signal -WAIT via gate 216.

The selection of the memory 4 is performed from the interface side by the signal -SELMC, and the input R / WR is activated by the signal -WRC. The memory can be relocated according to the location of the link from the PC bus side. The four most significant bits of the PC address bus are input to one side of the comparator 217, which must match the program value across the two links to allow memory selection.

7. Reset and Clock

The output of comparator 218 provides a reset. One of the inputs of the comparator maintains a reference voltage given by dividers 219 and 220 which maintain an intermediate voltage on the positive input.

When the potential increases, transistor 221 is saturated by the load current of capacitor 222 through resistor 223. The collector of transistor 221 is maintained at a voltage near 5 volts, and transistor 224 is saturated, causing a reset of a voltage of about 1 to 3 volts on the negative input of the comparator. When capacitor 22 is charged to a voltage that does not allow conduction of transistor 22, transistor 224 is cut off and the negative input of the comparator goes down through resistors 225 and 226 to ground. When the potential is lowered, transistor 227 discharges capacitor 228 via resistor 229 to include transistor 224 to cause a reset.

When a connection is made due to fast interruption and reconnection, capacitor 230 conducts transistor 227 to cause a reset.

For the external reset, the capacitor 222 is sufficiently discharged through either the switch or the gate 231.

Transmission and reception of the clock is obtained from oscillator 232 via gate 233, which is held by input 234 connected to 5 volts via resistor 235 so that the clock can be disabled by grounding if necessary. Can be.

The processor clock is obtained by distributing the preceding signal by the bistable circuit 236 shown in FIG. 6, which is obtained via the exciter circuit 237 of FIG.

Claims (7)

An intelligent and non-intelligent terminal for a medium / large computer or controller to combine the personal computer with the personal computer of the three terminals of the set of three terminals by considering the personal computer as a set of three terminals for the logical terminal, the interactive terminal, and the non-interactive terminal. A computer interface board used as an interface between a bus and a communication channel of the personal computer connected to the medium / large computer, which can be replaced by the input memory area 1 and the central memory area according to the functional block diagram. 2), consisting of four functional blocks including a central memory 3 and a communication memory 4, which can also be integrated in the input storage area 1 or are recorded via the processor 6; Block 5 for transmission and reception that can communicate with the remaining functional blocks of the Interface between the communication channel and the bus of the personal computer to process a communication protocol and to maintain the quick response time of the personal computer and at the same time between the three terminals of the workstation Interface board for a computer, characterized in that to handle the separation of. A microprocessor (6) for processing the logic of said communication protocol, operating a fixed program capable of maintaining a dialogue with said personal computer, and having an operating frequency of preferably about 3.75 MHz; It is designed to transmit and receive on the line, and to preliminarily analyze the information by the device.It consists of a small integrated circuit (SSI) and a medium integrated circuit (MSI) circuit and a 4-kilobyte EPROM read-only memory used as a decoder. block ; 8 kilobytes of static random access memory (RAM); An 8 kilobyte EPROM read only memory forming said functional block of said central memory (3); And a 1 kilobyte random access memory (RAM) constituting the communication memory block 4 having two ports capable of accessing the communication mechanism between the interface and the access channel of the personal computer. Interface board for a computer that is characterized. The workstation according to claim 1 or 2, wherein the input storage area shown by the function block (1) is a first receiving device for information, and fixes a maximum length of a block that can be processed by the interface board, and the workstation Interface board for a computer, characterized in that common to the three logic devices forming the. The method of claim 1 or 2, wherein the central memory area shown as the functional block (2) is an intermediate memory area, and the input memory area (1) is duplicated, and the input memory area is quickly and freely. Interface board for a computer, characterized in that shared by the three terminals of the set. The communication memory (4) according to claim 1 or 2, wherein the communication memory (4) possesses two ports for simultaneous access from the interface and the personal computer, and a mechanism is provided for directing signals from one port to another, And an interrupt generated by the personal computer from the interface, which may indicate a need for attention to the interface. The transmission / reception block (5) according to claim 1 or 2, which is configured according to the functional block diagram in two ways, for transmission and reception. There is a condition block (7) for the signal in between, and the transfer destination has a block (9) for the word sequence and a block (8) for parity generation as a transfer destination. 7. The destination of claim 6, wherein the destination is a serial / conversion block (10), an address and parity checking block (11), an error catching block (12), and a pre-decoding block in addition to the corresponding condition block (7). Having a 13-kilobyte EPROM, which is used as a decoder in this pre-decoding block, if the information is control information, it goes through the interrupt block 14 to the processor and writes if the information is data. Interface board for a computer, characterized in that it is sent directly to the block and recorded in the input memory area (1).

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