JPH01227474A - Manufacture of complementary bipolar transistor - Google Patents

Abstract

PURPOSE:To realize the title bipolar transistor operating at high speed by few processes by forming a first transistor in a emitter-base-self-alignment structure and a second transistor in a vertical type structure in which an emitter region is shaped through impurity diffusion from an emitter leading-out electrode composed of silicon crossing on an epitaxial layer and a field insulating film. CONSTITUTION:A first transistor is formed in emitter-base-self-alignment structure and a second transistor in vertical type structure in which an emitter region 16 is shaped through impurity diffusion from one conductivity type silicon emitter leading-out electrode 16 crossing on an epitaxial layer 3 and a field insulating film 7. One conductivity type silicon base leading-out electrode 5A extending on a field insulating film in the first transistor and said emitter leading-out electrode 16A are formed from a common silicon film. Said first transistor is shaped in an N-P-N transistor having emitter-base-self-alignment structure consisting of an emitter 6, a base 5 and a collector 4 and the second transistor in a P-N-P transistor having vertical type structure made lip of the emitter 16, a base 15 and a collector 14.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing complementary bipolar transistors, the aim is to realize high-speed operation with fewer steps. The second transistor has a vertical structure in which the emitter region is formed by impurity diffusion from an emitter lead electrode of silicon of one conductivity type spanning over the epitaxial layer and the field insulating film, and extends over the field insulation field of the first transistor. The existing base lead electrode of one conductivity type silicon and the emitter lead electrode are formed from a common silicon film.

[Industrial application field]

The present invention relates to a method for manufacturing complementary bipolar transistors.

Complementary bipolar transistors are NPN on a common substrate.
) It is a combination of a transistor and a PNP (PNP) transistor, and is used in memory circuits, analog circuits, etc., and is expected to operate at high speed.

[Prior art and problems to be solved by the invention] Bipolar transistors include a vertical structure in which the active parts from the emitter region to the collector region are arranged perpendicularly to the substrate surface, and a horizontal structure in which the active parts are arranged parallel to the substrate surface. , since the latter has a larger base width from a manufacturing standpoint, the former is more suitable for high-speed operation.

In the former case, the operation speed can be further increased by reducing the capacitance between the collector bases. To this end, a structure may be created in which the width of the base region is made small so that the joint area between the collector bases is small.

The emitter-base self-line structure shown in the side view of Fig. 2 is a structure that realizes this purpose.
In the same figure showing the case of a transistor, l is a p- silicon substrate, 2 is an n+- buried diffusion layer, 3 is an n- epi layer, 4 is an n- collector region, 4a is an n+- collector contact region, and 4A is an n+- Polysilicon collector lead electrode,
5 is a base region, 5a and 5b are p-intrinsic base regions and p4-extrinsic base regions in base region 5, 5A is a C-polysilicon base extraction electrode, 6 is an n+-emitter region, and 6A is an n+-polysilicon base region. Emitter extraction electrode, 7 is field insulating film, 7A is element isolation! ! 8 is an interlayer insulating film, and 9 is a wiring. The impurity concentration of the collector lead-out electrode 4^ is particularly high in order to compensate for the distance of the connection portion from the base region 5.

In this structure, the base lead electrode 5A extends over the field insulating film 7, and the field insulating film 7 goes under the connecting portion of the wiring 9 connecting to the base region 5, so that the base region 5 is wide. This makes it more suitable for high-speed operation than a normal vertical structure.

From this, in order to speed up the operation of the complementary bipolar transistor, both the NPN transistor and the PNP transistor should have an emitter-base self-line structure.

However, in such a complementary bipolar transistor, it is unavoidable that the conductivity types of the collector region, base region, and emitter region are reversed between both transistors, and the collector lead electrode, base lead electrode Since the conductivity types of the electrodes and the emitter extraction electrodes are reversed between both transistors, there is a disadvantage that the manufacturing steps are significantly more than in the case of an NPN or PNPI transistor alone.

For this reason, in the past, one of the transistors had a horizontal structure to avoid increasing the number of steps, and the desired speed-up was not achieved.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to realize a method for manufacturing a complementary bipolar transistor that operates at high speed with fewer steps.

[Means to solve the problem]

・The above purpose is to configure the first transistor with an emitter-base-self-line structure and the second transistor with impurity diffusion from the emitter extraction electrode of silicon of one conductivity type, where the emitter region straddles the epitaxial layer and the field insulating film. A manufacturing method of the present invention in which a base lead electrode of one conductivity type silicon extending on a field insulating film of a first transistor and the emitter lead electrode are formed from a common silicon film. achieved by

[For production]

The first transistor has an emitter-base self-line structure and is suitable for high-speed operation.

Further, the second transistor has a vertical structure, and since the connecting portion of the wiring connected to the emitter region can be placed on the field insulating film, the base region is drawn out close to the emitter region. It is possible to reduce the width of the transistor, and as with the first transistor, it is suitable for high-speed operation than a normal vertical structure.

In a complementary bipolar transistor in which the first and second transistors are combined, the base lead electrode of the first transistor and the emitter lead electrode of the second transistor are formed from a common p+- or n+-silicon film. Therefore, fewer manufacturing steps are required.

〔Example〕

Embodiments of the present invention will be described below with reference to side views (a) to (e) of FIG. 1 showing the steps thereof.

FIG. 1 shows a case where the first transistor on the left side is an NPN transistor and the second transistor on the right side is a PNP transistor, and FIG. 1(e) shows the completed state.

The first transistor has the emitter-base self-line structure described in FIG. 2, and the second transistor has the
This is a vertical structure in which the emitter region is formed by impurity diffusion from an emitter extraction electrode spanning over the epitaxial layer and the field insulating film. Therefore, as mentioned above, both transistors and transistors are suitable for high-speed operation, and a complementary bipolar transistor in which they are combined is capable of high-speed operation.

In FIG. 1, the same symbols as in FIG. 2 indicate the same objects, 14 is a p-collector region, 14a is a p+-collector contact region, 14A is a p+-polysilicon collector extraction electrode, and 15 is an n-base region. , 15A is an n+-polysilicon base extraction electrode, 16 is a p+-emitter region, and 16A is a p+-polysilicon emitter extraction electrode.

The procedure of the embodiment of the manufacturing method shown in FIG. 1 is as follows. That is, with reference to Figure (a), (1) a buried diffusion layer 2 is formed in the substrate l by a known method.

(2) Grow epitaxial layer 3 by CVD method.

(2) A field insulating film 7 is formed by the LOCO3 method.

(2) Form an element isolation insulating region 7A by a known method. This divides the epitaxial layer 3 and forms the collector region 4.

(2) Form collector contact region 4a by ion implantation.

(2) The collector region 14 and the base region 15 are formed by two ion implantations using different masks.

1) Form a first polysilicon film on the entire surface by CVD method, and form collector lead electrode 4A, base lead electrode 5A, and emitter lead electrode 16A+ by LOCO3 method.
Collector extraction electrode 14. Form a pattern A (a portion above the intrinsic base region 5a and the emitter extraction electrode 1).
6A and the collector lead-out electrode 14A is left as a polysilicon layer).

■ By performing ion implantation twice using separate masks, the collector extraction electrode 4A is changed to n+, the base extraction electrode 5A, the emitter extraction electrode 16A, and the collector extraction electrode 14A.
Set to 1. At this time, the implantation concentration of C is made higher than p+.

Referring to Figure (C), (1) silicon dioxide is deposited on the entire surface by CVD method to form a glabellar insulating film 8;

[Phase] By etching using a mask, the parts from the glabella insulating film 8 to the base extraction electrode 5A pattern and the emitter extraction electrode 16A+collector extraction electrode 14A pattern are penetrated and removed, and the base window for the intrinsic base region 5a and the base region 15 are etched. Open the base window. The latter base window separates the emitter lead electrode 16A and the collector lead electrode 14A, forming each into a predetermined pattern.

Then, the intrinsic base region 5a is formed by ion implantation while masking the latter base window.

■ After depositing silicon dioxide on the entire surface including the side surfaces of the base window using the CVD method, a silicon dioxide film is left on the side surface of the base window using the RIE (reactive ion etching) method, and an intrinsic base region is formed at the bottom of each base window. 5a or base region 15 is exposed. The remaining silicon dioxide film becomes a part of the glabellar insulating film 8, and the window above the intrinsic base region 5a becomes an emitter window.

Referring to Figure (d), a second polysilicon film is formed on the entire surface by filling the emitter window and the base window by the CVD method, and after making it n+ by ion implantation, the emitter window and the base window are The emitter extraction electrode 6A and the base extraction electrode 15A are formed by patterning so that the remaining electrodes remain.

Referring to FIG.
interlayer insulation between collector window and base window for connecting
Formed at IJ, 8.

[Phase] Through the heat treatment for emitter drive, the n-type impurity of the emitter extraction electrode 6A is converted into the intrinsic base region 5a.
emitter region 6 and emitter extraction electrode 1
An emitter region 16 formed by diffusing 6A of n-type impurity into the base region 15, an external base region 5b formed by diffusing the n-type impurity of the base extraction electrode 5A into the collector region 4 and connecting to the intrinsic base region 5a, and a collector extraction electrode. 14^
At the same time, a collector contact region 14a is formed by diffusing n-type impurities into the collector region 14.

(2) Aluminum is deposited by sputtering and patterned to form wiring 9.

Looking at the above steps, all steps except step (1) are necessary when manufacturing the first transistor having an emitter-base self-line structure, that is, the transistor shown in FIG. 2, alone.

Therefore, a high-speed complementary bipolar transistor can be realized with a small number of steps in which only step (1) needs to be added, that is, the increase in steps is approximately the same as in the case where the second transistor has a horizontal structure. This is because the formation of the collector extraction electrode 14^ on the base extraction electrode 5A and the emitter extraction electrode 16, and the formation of the emitter extraction electrode 6^ and the base extraction electrode 15A are performed by using a common polysilicon film and performing ion implantation and patterning. This was made possible by commonality.

In the embodiment, the first transistor is an NPN transistor, but it goes without saying that the process is similar if the first transistor is a PNP transistor.

〔Effect of the invention〕

As explained above, according to the configuration of the present invention, regarding the manufacturing method of complementary bipolar transistors, it is possible to share the process of forming a plurality of extraction electrodes, and it is possible to realize high-speed operation with fewer steps. It has the effect of

[Brief explanation of the drawing]

1 is a side view showing the process of the embodiment, and FIG. 2 is a side view of the emitter-base self-line structure. In these figures, 1 is a p-silicon substrate, 2 is an 01-buried diffusion layer, and 3 is a n-epi layer, 4 is an n-collector region, 4a is an n+-collector contact region, 4A is an n+-polysilicon collector extraction electrode, 5 is a base region, 5a is a p-intrinsic base region in 5, 5b is a p-intrinsic base region in 5 p+-external base region, 5A is a p+-polysilicon base extraction electrode, 6 is an n"-emitter region, 6A is an n+-polysilicon emitter extraction electrode, 7 is a field insulating film, 7A is an element isolation insulation region, 8 is an interlayer insulating film, 9 is a wiring, 14 is a p-collector region, 14a is a p+-collector contact region, 14^ is a p+
- Polysilicon collector extraction electrode, 15 is n- base region, 15A is n+- polysilicon base extraction electrode, 16
is a p+-emitter region, and 16^ is a p+-polysilicon emitter extraction electrode. 1st Figure 1 Pig・■-λ・Selfarai-/a Shoume page 11 ID No. 2I21

Claims (1)

[Claims] The first transistor has an emitter-base self-line structure, and the second transistor has a vertical emitter region formed by impurity diffusion from an emitter extraction electrode of one conductivity type silicon spanning over the epitaxial layer and the field insulating film. A complementary bipolar transistor having a type structure, wherein the base lead electrode of one conductivity type silicon extending on the field insulating film of the first transistor and the emitter lead electrode are formed from a common silicon film. Production method.