JPH0581191B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having an integrated injection logic circuit (hereinafter referred to as I ² L) and a normal bipolar transistor on the same substrate.

[Conventional technology]

FIG. 4 shows a cross-sectional view of the structure of an integrated circuit conventionally considered in which I ² L and bipolar transistors coexist. Part A is I ² L, and part B is a normal bipolar transistor that coexists with I ² L. That is, a P type semiconductor substrate 1 has two N ⁺ type first buried layers 2, and an N ^- type epitaxial layer 4 is formed thereon, and this epitaxial layer 4 has a P ⁺ type separation layer that reaches the P type semiconductor substrate 1. Region 5 is divided into a plurality of island regions. In part A, an N ⁺ type collar region 7 is formed to reach the N ⁺ type first buried layer 2, and a P layer is formed in the epitaxial layer therein so as to include at least the internal base region of the reverse operation NPN transistor. A mold first base region 6a is formed.

A P+ type injector region 8a, a P ⁺ type second base region 8b serving as an external base region, and a P ⁺ type second base region 8b on the surface of the epitaxial layer 4 in the A section, and the epitaxial layer 4 in the B section.
P ⁺ -type base regions 8c of ordinary NPN transistors are simultaneously formed on the surfaces of the transistors. Here, the first base region 6a is the injector region 8a, the second base region 6a is
The base region 8b and the base region 8c are formed with lower concentration and deeper. Note that the first base region 6a is formed inside the surface _S1 of the second base region 8b that faces the injector region 8a. Further A
The part B contains the N ⁺ type emitter collector region 9a of the reverse operation NPN transistor, the N ⁺ type collector region 9b of the same transistor, and the B part contains the N + type emitter region 9c of the normal NPN transistor, and the N ⁺ type emitter region 9c of the same transistor.
An N ⁺ type collector contact region 9d is formed.

Note that 10 is an oxide film formed on the surface, 11 is an injector electrode pattern, and 12, 13, and 14 are I ² L
The emitter/base/collector electrode pattern of the
Reference numerals 15, 16, and 17 are emitter-base-collector electrode patterns of a normal NPN transistor.

Conventional I ² L has the following advantages.

(1) Operates inversely to the common emitter current amplification factor (hereinafter referred to as _hFE ) of a normal NPN transistor.
The current amplification factor (hereinafter referred to as β _up ) when the injector of the NPN transistor is open can be highly controlled.

(2) Since the first base region of the reverse-acting NPN transistor is formed with a low concentration, the emitter-base junction capacitance (hereinafter referred to as C _eb ) and collector-base junction capacitance (hereinafter referred to as C _cb ) are small, resulting in particularly low current. The operating speed can be improved.

(3) Since the first base region of the transistor is formed deeply, the effective epitaxial thickness (hereinafter referred to as W _epi ) between the first base region and the first buried layer becomes small, which reduces the accumulation of holes in the epitaxial layer. can be reduced and the operating speed can be improved.

[Problem that the invention seeks to solve]

As described above, the conventional I ² L has advantages, but it has limitations when aiming for higher speeds, particularly at higher speeds at large currents. The reason for this is that in conventional I ² L, the emitter of a normal NPN transistor
This is because the low concentration first base region of the reverse operation NPN transistor cannot be formed deep enough to reach W _epi 0 under process conditions that ensure collector-to-collector breakdown voltage (hereinafter referred to as BV _CEO ). In other words, since the first base region cannot reach the first buried layer, W _epi does not become 0, and holes accumulate in the epitaxial layer directly under the first base region of the reverse operation NPN transistor, which limits the operation speed. will occur.

[Means for solving problems]

The present invention has been devised to solve these problems, and is an improvement on ordinary bipolar transistors.
An object of the present invention is to provide a semiconductor device that achieves an improvement in I ² L operating speed, especially at large currents, without reducing BV _CEO .

The semiconductor device of the present invention is a semiconductor device having an I ² L and a bipolar transistor on the same substrate. A bipolar transistor having a collector, a base, and an emitter, and a region of one conductivity type in the first island, which has an epitaxial layer in the second island as a base region, and is formed on the surface of the epitaxial layer so as to be spaced apart from each other in the lateral direction. A lateral transistor having a first region and a second region of one conductivity type formed to the same depth as the emitter region and a collector region, respectively, and an epitaxial layer in the second island as an emitter region and a second region as an external base region. , a third region of one conductivity type, which is formed at a lower concentration and deeper than the second region, and which is formed inside at least a surface of the second region facing the first region, is formed as an internal base region in the third region. a vertical transistor whose collector region is at least one fourth region of another conductivity type formed therein;
It is characterized by having a second buried layer of one conductivity type formed immediately below the third region on the first buried layer in the island and in contact with the third region.

〔Example〕

The present invention will be explained below with reference to the drawings.

FIG. 1 is a structural sectional view showing one embodiment of the present invention. First, for example, Sb or As is diffused from the back surface of a 10 ¹⁴ to 10 ¹⁶ cm ^-3 P ^- type substrate 1 to form an N ⁺ type first buried layer 2 of 10 to 30 Ω/□. An impurity having a larger diffusion coefficient than the impurity forming the I ² L region, such as B or BCl ₃ , is diffused or ion-implanted from the surface of the first buried layer directly under the first base region 6a, which will be described later, in the I 2 L portion.
A P-type second buried layer of 0.1 to 1 kΩ/□ is formed. In this case, in order to increase β _up , it is desirable that the concentration be as low as possible. Further, the second buried layer 3 may be formed as a part of the isolation region. Then 1~5x
N ^- type epitaxial layer 4 of 5-10 μm at 10 ¹⁵ cm ^-3
For example, from the surface of the epitaxial layer 4,
P ⁺ type isolation region 5 of 10-20Ω/□ by diffusing BCl ₃
After that, for example, B is ion-implanted from the surface of the epitaxial layer 4 in the I ² L portion to form a P-type first base region 6a of 1 to 5 kΩ/□ so as to include at least the internal base region of the reverse operation NPN transistor. form. Next, for example, POCl ₃ is diffused from the surface of the epitaxial layer 4 in the I ² L portion to form an N ⁺ type collar region 7 of 10 to 30 Ω/□. Note that the steps for the first base region 6a and the color region 7 may be replaced. Next, ions of B, for example, are implanted from the surface of the epitaxial layer 4 to form a P ⁺ type injector region 8a in the I ² L portion with a high concentration and a shallow depth of 100 to 300 Ω/□ compared to the first base region 6a, and a P ⁺ type. The second base region 8b and the normal
A P ⁺ type base region 8c of the NPN transistor is formed at the same time. The first base region 6a is formed so as to be in contact with the second buried layer 3, and is also formed inside the surface _S1 of the second base region 8b that faces the injector region 8a. Next, epitaxial layer 4
For example, by diffusing POCl ₃ from the surface, the resistance of 5 to 15 Ω/□
N ⁺ type emitter contact region 9a and N ⁺ type collector region 9b of the reverse operation NPN transistor in the I ² L section
Also, an N ⁺ type emitter region 9c and an N ⁺ type collector contact region 9d of a normal NPN transistor are formed at the same time. Then the injector area of I ² L part,
Emitter-base of reverse-acting NPN transistor
The oxide film 10 in the collector region and the predetermined contact opening regions of the emitter, base, and collector regions of a normal NPN transistor is etched, and aluminum is sputtered or vapor-deposited to form each electrode pattern 11,1.
2, 13, 14 and 15, 16, 17 are formed. In this manner, a semiconductor device according to an embodiment of the present invention is manufactured.

FIG. 2 shows the concentration profile at the A-A' cross section in FIG.

FIG. 3 is a structural sectional view showing another embodiment of the present invention. A P-type second injector region 6b, which is formed deeper than the injector region 8a, is formed at least inside the surface _S2 of the injector region 8, which faces the second base region 8b, at the same time as the first base region 6a. It is characterized by having a P-type second buried layer 3 directly below the second injector region 6b on the first buried layer. In addition, if there is a second buried layer, the second
The injector region does not need to be formed at the same time as the first base region, and may be formed in a separate process, for example, at the same time as the separation region. The other manufacturing steps are the same as in the case of FIG. 1, and will therefore be omitted.

〔Effect of the invention〕

According to an embodiment of the present invention, in the I ² L portion, a first buried layer of the same conductivity type as the first base region is provided in the first buried layer immediately below the first base region of the reverse operation NPN transistor so as to be in contact with the first base region. Since two buried layers are formed, the second buried layer also becomes part of the base area.
W _epi becomes 0. Therefore, the accumulation of holes in the epitaxial layer immediately below the first base region is significantly reduced, and the operating speed, particularly at high currents, is improved. Also, since the horizontal injector PNP transistor has a second buried layer, the horizontal injector
As the depth of the collector region of the PNP transistor increases, the rate at which holes injected from the injector region reach the collector region increases. As a result, the common base current amplification factor α _PNP of the lateral injector PNP transistor increases, and the operating speed at low currents improves.

Furthermore, according to another embodiment of the present invention, since the second injector region and the second buried layer are formed in contact with each other, the depth of the emitter region (injector region) of the lateral injector PNP transistor is increased, and holes in the lateral direction are formed. injection becomes effective. Furthermore, since the bottom part of the emitter region is in contact with the N ⁺ type first buried layer, hole injection from the bottom part is reduced. Therefore, α _PNP of the lateral injector PNP transistor becomes even higher, and higher speeds can be achieved at lower currents. In this embodiment, only the second injector region is formed, and there is no need to form the second buried layer, and the same effect can be obtained in that case.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and the same effect can be obtained even if the polarity is changed, for example.

[Brief explanation of the drawing]

Figure 1 shows an embodiment of the present invention, I ² L and ordinary
2 is a cross-sectional view of the structure of an integrated circuit in which NPN transistors coexist; FIG. 2 is a concentration profile taken along the line A-A' in FIG. 1; and FIG. 3 is a cross-sectional view of a similar integrated circuit showing another embodiment of the present invention. 4 are structural cross-sectional views of an integrated circuit in which a conventional I ² L and a normal NPN transistor coexist. DESCRIPTION OF SYMBOLS 1... P ^- type semiconductor substrate, 2... N ⁺ type first buried layer, 3... P type second buried layer, 4... N ^- type epitaxial layer, 5... P ⁺ type isolation region , 6a...I ² L
P-type first base region, 6b... P-type second injector region, 7... N ⁺ type color region, 8a...
P ⁺ type injector region, 8...P ⁺ type second base region of ^I2L , 8c...P type base region of a normal NPN transistor, 9a...N ⁺ type emitter contact region of ^I2L , 9b ...N ⁺ type collector region of I ² L, 9c...N ⁺ type emitter region of a normal NPN transistor, 9d...N ⁺ type collector contact region of a normal NPN transistor, 10...Divided film, 11... ...Injector electrode pattern, 12,
13, 14...I ² L emitter-base-collector electrode pattern, 15, 16, 17... Normal
Emitter-base-collector electrode pattern of NPN transistor.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of another conductivity type formed on the semiconductor substrate, and an epitaxial layer of one conductivity type that separates the epitaxial layer into first and second islands. a first buried layer of another conductivity type formed in a boundary region between the semiconductor substrate and the epitaxial layer in the first and second islands, and a first buried layer formed in the first island. a bipolar transistor in which the epitaxial layer, a region of one conductivity type, and a region of the other conductivity type serve as a collector, a base, and an emitter, respectively; the epitaxial layer in the second island serves as a base region; A first region and a second region of one conductivity type formed laterally apart from each other on the surface of the layer are emitters, respectively.
a lateral transistor having a collector region; the epitaxial layer in the second island being an emitter region; the second region being an external base region; A third region of one conductivity type formed inside the surface facing the first region is an internal base region, and at least one fourth region of another conductivity type formed within the third region is an internal base region. a vertical transistor serving as a collector region, a transistor of one conductivity type formed immediately below the third region on the first buried layer in the second island and in contact with the third region; A semiconductor device characterized by having two buried layers. 2. A fifth region of one conductivity type formed deeper than the first region at least inside the surface of the first region facing the second region in the second island;
formed directly under the fifth region, and furthermore, the fifth region
2. The semiconductor device according to claim 1, further comprising a second buried layer of one conductivity type in contact with the region.