JPS61263149A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the manufacture of a semiconductor device, in which a first vertical transistor and a second vertical transistor are integrated without damaging each characteristic, by deeply forming a section just under a collector region of a base region in the first vertical transistor as a low concentration layer, shallowly shaping an external base region and a base region in the second vertical transistor simultaneous ly and forming the external base region and the second vertical transistor in compara tively high concentration. CONSTITUTION:Ions are implanted into an active base region just under a collector region in an I<2>L section to form p<-> layers 71, 72. Heat treatment at a high temperature is executed for a fixed time, thus making p<+> layers 4 to reach a p<-> -Si substrate 1, each making n<+> layers 5, 6 to reach n<+> layers 21, 22 and bringing the p<-> layers 71, 72 to low concentration layers in diffusion depth of approximately 3-3,5mum. The n<+> layers 21, 22 are also floated into an n layer 3 and the p<-> layers 71, 72 are brought into contact with the n<+> layer 21 at that time. A p layer 8 as an emitter region in a p-n-p lateral transistor form an injector in the I<2>L section, a p layer 9 as an external base region surrounding the collector region and a p layer 10 as a base region in a bipolar transistor are shaped in comparatively high concentration so as to form diffusion depth of approximately 2mum through methods such as the simultaneous implantation and diffusion of boron ions.

Description

[Detailed Description of the Invention] The present invention is an integrated circuit that does not require much withstand voltage and operates at high speed with low power consumption.
The present invention relates to a method for manufacturing a semiconductor device that integrates a conventional bipolar transistor (-ejection logic) and a normal bipolar transistor that requires a high breakdown voltage.

I"L is a vertical transistor with an inverse structure in which a collector region serving as a signal output end region is provided on the surface of a semiconductor substrate, and a complementary type transistor whose collector region and base region are shared with the base region and emitter region of the vertical transistor, respectively. I''L is attracting attention as a logic element that allows high density operation because it does not require isolation between elements, and operates with low power consumption.

I''L also has the advantage that it can be easily integrated on the same semiconductor substrate with regular bipolar transistors.

By the way, when I"L and a normal bipolar transistor are integrated on the same substrate in the same manufacturing process, I"L
If you try to maintain the high speed of I"L by increasing the current amplification factor of the reverse structure vertical transistor in the section, the withstand voltage of the bipolar transistor will become extremely small. Conversely, if you try to increase the withstand voltage of the bipolar transistor, the I"L will increase. The problem is that the high-speed performance of the system is impaired. Several methods have been proposed to solve this problem, but at present none are sufficient.

This invention was made in view of the above points, and I”L
The present invention provides a method for manufacturing a semiconductor device in which a conventional bipolar transistor and a conventional bipolar transistor are integrated without impairing their respective characteristics.

That is, the present invention provides a semiconductor device in which an I"L having a first vertical transistor having an inverted structure and a second vertical transistor which is a normal bipolar transistor is integrated, in which a part of the base region of the first vertical transistor is integrated. It is characterized in that at least a region immediately below the collector region is deeply formed as a low concentration layer, and the external base region surrounding the collector region and the base region of the second vertical transistor are simultaneously shallowly diffused to form a relatively high concentration layer.

The present invention will be described in detail below with reference to the drawings. FIGS. 1(a) to (8) show the manufacturing process of one embodiment, in which an I2L having an inversely structured npn vertical transistor (first vertical transistor) and pnp lateral transistor is used as a logic element, and a second This is an example in which normal npn bipolar transistors are integrated as vertical transistors. To explain this according to the manufacturing process, the I''L part and the bipolar transistor part of the P"'-8i substrate 1 include n+10 layers, 2. After diffusing and forming, an n layer 3 is epitaxially grown on the entire surface (a)
Next, the entire surface of this substrate is oxidized, a predetermined diffusion window is opened, and a p+10 layer for element isolation and an n layer, which will be the grounding end of the I''L part, are formed.
+10 layers and an n+10 layer for extracting the collector of the bipolar transistor section are formed by diffusion, and then ions are implanted into the active base region directly under the collector region of the I2L section to form a p layer. ,,7. (b). Next, by applying a high-temperature heat process for a predetermined period of time, the p-soil layer 4 becomes p--8.
So that the i-substrate 1 is reached, the n-soil layers 5 and 6 reach the n-soil layers 21 and 2□, respectively, and the p-layers 7□ and 7□.
Sheet resistance 3000~5000Ω/mouth, diffusion depth 3~
3. Make it a low concentration layer of about 5- (C),
At this time, the n+10 layer 1.2□ also floats up into the 1st layer 3 so that the p1 layer 7□, 7□ comes into contact with the n soil layer 2□. Next, the second layer 8. The collector region of the lateral transistor, that is, the inverter floating structure np
Two layers 9 surrounding the collector region of the n-vertical transistor serve as the external base region and two layers 10 serve as the base region of the bipolar transistor.

For example, boron ion implantation and diffusion are performed at the same time to form a relatively high mK so that the sheet resistance is 80 to 180 Ω/hole and the diffusion depth is about 2 mm (d), and then.

The output end region of the I''L section, that is, the n-soil layer 11..11° that will become the collector region of the inverted vertical transistor, and the n-soil layer 12 that will become the emitter region of the bipolar transistor are simultaneously diffused to a depth of 1.3 to 2. .0p, and finally by vapor deposition and patterning of Al1, I2L
Signal input terminal electrode IN, signal output terminal electrode OUT,
, 0UT2, ground electrode GND, external power supply electrode +VI
IEI! Then, an emitter electrode E, a base electrode B, and a collector electrode C of a bipolar transistor are formed (e). In addition, n soil layer 11. , 11° and the n soil layer 12 have different diffusion depths due to the difference in their respective base region concentrations. For example, when the former is about 1.7-, the latter is about 1.4 μs.
becomes.

In the device thus obtained, the inverter floating structure npn vertical transistor in the I2L section has a low concentration layer in the active base region directly under the collector, so that the current amplification factor is low even if the base width is 1 to 2 IJM. By making the low concentration layer in the large active base region of the parenthesis deep so that it touches the n soil layer 2□ and by providing a relatively high concentration external base region surrounding the active base region, high speed can be achieved. operation is possible, and one I”
It becomes possible to take a large amount of fan-out with the L gate. Also, if we look at the bipolar transistor section, we can see that this np
The base region of the n vertical transistor is the n soil layer 2□
Since the 0 layer 3 with a thickness of 1 to 1.5 is left, a high breakdown voltage between the collector and emitter is ensured. Furthermore, due to the difference in base concentration between the I''L part and the bipolar transistor part,
The fact that the emitter region diffusion of the bipolar transistor section is shallower than the collector region diffusion of the I''L section means that the base region diffusion of the bipolar transistor section can be made shallower, which further increases the breakdown voltage of the pievorous silane transistor. It is advantageous to do so.

FIG. 2 shows another embodiment of the present invention corresponding to FIG. 1 (8). Portions corresponding to those in FIG. 1(a) are given the same reference numerals and detailed explanations will be omitted.

In this embodiment, the p layer 7', which is the low concentration base region of the I"L portion, is formed by diffusion not only directly under the collector but also over the entire base region, and its diffusion end is in contact with the n+10 layer □, and From above the first layer 7', a pf 19 surrounding the collector region is again formed with a relatively high concentration and is diffused to be shallower than the p first layer 7' at the same time as the second layer 10 which becomes the base region of the bipolar transistor section. Compared to the previous embodiment, since the 0 layer 3 is not left under the 2 layer 9 which is the high concentration base region of the I2L portion, I”
Carrier accumulation in the emitter region of the L part decreases, and I'L
can operate faster.

As described in detail above, according to the present invention.

To provide a method for manufacturing a semiconductor device useful for various logic circuit configurations in which a logic element I"L capable of high-speed operation and sufficient fan-out and a bipolar transistor requiring high breakdown voltage are integrated without impairing their respective characteristics. be able to.

[Brief explanation of drawings]

FIGS. 1(a) to 1Ce) are diagrams showing the manufacturing process of one embodiment of the present invention, and FIG. 2 is a diagram showing another embodiment corresponding to FIG. 1(a). 1-P'''-5i-5i substrate il 2.'''n ten layers...8 layers 4...P layer (for element isolation) 5
...n soil layer (for grounding) 6...n soil layer (for collector extraction) 7,,7. , 7'...p single layer (low concentration base region)
8...p layer (emitter region of injector) 9...
2 layers (high concentration base region) 10...p layer (high concentration base region) 11□, 112...n soil layer (collector region) 12...
・N soil layer (emitter area) Agent: Patent attorney: Nori Chika, Yudo, Kikuo Takehana ((L) Cb)! (C)! Figure 1

Claims (1)

[Claims] a first vertical transistor having an inverse structure in which a collector region serving as a signal output end region is provided on the surface of a semiconductor substrate; and a first vertical transistor having a collector and a base region shared with the base and emitter regions of the first vertical transistor, respectively. When manufacturing a semiconductor device in which a logic element consisting of a complementary type transistor is integrated on the same semiconductor substrate with a second vertical transistor whose emitter region is provided on the surface of the semiconductor substrate, A semiconductor substrate is formed by forming a low concentration layer of a second conductivity type through a high concentration buried layer of a second conductivity type, and the high concentration buried layer is formed immediately below the collector region of the first vertical transistor. to form a bottom-concentrated active base region, and shallowly diffuse around the collector region to form a relatively highly doped external base region to constitute a base region of the first vertical transistor; A method of manufacturing a semiconductor device, characterized in that the external base region of the first vertical transistor is shallowly diffused and formed at a relatively high concentration at the same time as the base region of the second vertical transistor.