JPH0477459B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a vertical bipolar transistor mainly for high-speed logic operation and analog circuits in a high frequency region, and particularly relates to a method for manufacturing a vertical bipolar transistor for high-speed logic operation and analog circuits in a high frequency region. A method for forming a desired impurity profile in the lateral direction.

(Prior art) As a bipolar transistor for high-speed logic operation or analog circuits in the high frequency range,
Further improvement of the cutoff frequency is desired. Conventionally, attempts have been made to improve the cutoff frequency by controlling the vertical impurity profile, such as by forming a shallow emitter-base junction or reducing the base width.
However, with current ion implantation technology and technology such as diffusion from polycrystalline silicon, it is not easy to control the above-mentioned vertical impurity profile, and the improvement of the cutoff frequency is approaching its limit.

On the other hand, HJYIM and others reported that they succeeded in improving the cutoff frequency by forming a lateral impurity profile in the base region of bipolar transistors using a focused ion beam.
ELECTRON DEVICE LETTERS，VOL.EDL
−7.No.11, NOVEMBER1986, pages 621 and 622. The structure of this transistor is as shown in FIGS. 3a and 3b, with a base region 32
As shown in FIG. 4, the concentration of boron, which is a P-type impurity, is high at the lateral ends and low at the center. Such a lateral impurity profile reduces emitter crowding and the associated high-injection effects, thereby increasing the collector current region where the cut-off frequency peaks and the cut-off frequency drops occur. . In addition, in FIGS. 3a and 3b, 30 is an N ⁺ buried layer, 31 is an N-type epitaxial layer for taking out the collector electrode, 3
2 is a P type base region, 33 is an N type emitter region,
34 is a SiO ₂ film, 35 is a base electrode, 36 is an emitter electrode, 37 is a base contact region, 38
is the emitter contact area.

However, the conventional method of using a focused ion beam to form the above-mentioned lateral impurity profile has problems due to the performance of current focused ion beam implantation equipment.
The problem is that it is difficult to obtain fine elements and requires special and expensive equipment, resulting in high manufacturing costs.

(Problems to be Solved by the Invention) The present invention has been made to solve various problems associated with forming the lateral impurity profile in the base region using a special focused ion beam technique, as described above. By using a simple method, the above lateral impurity profile can be formed in a minute base region, and a high-speed bipolar transistor with improved peak cutoff frequency and collector current range where its drop occurs can be manufactured at low cost. An object of the present invention is to provide a method for manufacturing a bipolar transistor that can be obtained.

[Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a bipolar transistor according to the present invention is to fabricate polycrystalline silicon containing a high concentration of impurities in the periphery of a region where an emitter is to be formed on the surface of a semiconductor substrate. After forming the base electrode extension part, impurity-free polycrystalline silicon is deposited on the upper surface of the substrate including the area where the emitter is to be formed, and then the impurity-free polycrystalline silicon is deposited from the base electrode extension part by thermal diffusion. The method is characterized in that impurities are diffused so as to form a lateral impurity profile in the semiconductor substrate, and further, impurities on the emitter formation region and the base electrode extension portion are diffused into the semiconductor substrate by thermal diffusion.

(Function) When impurities having a lateral profile on the emitter formation area and impurities in the base electrode lead-out part diffuse into the substrate, the lateral center of the base region has a low concentration and the periphery has a high concentration impurity profile. Isles will begin to form.

The above manufacturing method can be performed relatively easily without requiring special equipment such as a focused ion beam implanter, and can form a lateral impurity profile in a fine area of about 1 μm on a plane. Therefore, a high-speed bipolar transistor with an improved peak value of cut-off frequency and a collector current region where the cut-off frequency decreases can be realized at low cost.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1a to 1h show part of the process for forming a bipolar NPN transistor in a semiconductor integrated circuit. That is, as shown in FIG. 1a, first, an N ⁺ buried layer is formed on a P-type semiconductor substrate, an N-type epitaxial layer 1 is grown, and a silicon oxide film 2 of, for example, about 1000 Å thick is formed on the surface of the N + buried layer. A silicon film 2' having a thickness of, for example, about 1000 Å is sequentially formed to form an insulating layer. Next, a hole is formed in a portion of the silicon oxide film 2 and silicon nitride film 2' corresponding to the base electrode extraction region, and a P-type impurity such as boron is injected at a high concentration (for example, 1×10 ²⁰ A first polycrystalline silicon film 3 containing a polycrystalline silicon film 3 (approximately cm ^-3 ) is formed. Next, this polycrystalline silicon film 3 is patterned to leave a predetermined base electrode extraction portion 3'. At this time, the polycrystalline silicon film above the area where the emitter is to be formed is etched off. Next, as shown in FIG. 1b, a silicon oxide film 4 is formed over the entire surface of the polycrystalline silicon by selective thermal oxidation using a silicon nitride film. At this time, oxidation does not proceed because the silicon nitride film exists on the area where the emitter is to be formed. Next, by removing the silicon nitride film 2' and the silicon oxide film 2 on the area where the emitter is to be formed, as shown in FIG. ) is exposed, and
An exposed surface of the polycrystalline silicon of the base electrode lead-out portion 3' is formed so as to surround this exposed surface. In this case, the width of the area where the emitter is to be formed is formed to be approximately 1 μm.

Next, as shown in FIG. 1d, a second polycrystalline silicon film 5 without addition of impurities is deposited on the entire surface of the substrate to a thickness of, for example, about 500 Å. next,
For example, by annealing at 800°C for a short time (for example, only loading and unloading the semiconductor wafer into a processing chamber at 800°C), as shown in FIG. The P-type impurity diffuses laterally in the second polycrystalline silicon film 5 on the region where the emitter is to be formed, and this portion comes to have a lateral P-type impurity profile. Next, by selective etching using hydrazine or the like, the portions of the impurity-free polycrystalline silicon film 5 into which the impurities have not diffused are removed.
As shown in FIG. 1f, polycrystalline silicon 5' remains with a lateral impurity profile over the region where the emitter is to be formed. Furthermore, when thermal oxidation is performed, the first
As shown in FIG. g, a silicon oxide film 4' is formed on the entire surface of the substrate, and the P-type impurity on the substrate surface is diffused into the epitaxial layer 1, forming a P-type base region 6. In this case, the P-type base region 6 includes an external base region ₆₂ containing a high concentration of P-type impurities diffused from the polycrystalline silicon of the base electrode extraction portion 3', and a polycrystalline silicon 5' on the emitter formation area. The lateral impurity profile of _the internal base region 6 ₁ is as shown in FIG.
The concentration is low in the horizontal center and high in the periphery. Next, as shown in _FIG . 7
form.

That is, according to the method for manufacturing a bipolar transistor as described above, a lateral impurity profile is formed by thermal diffusion in the impurity-free polycrystalline silicon deposited on the region where the emitter is to be formed, and this is oxidized. The method is characterized in that a base region having a lateral impurity profile with a low concentration in the center and a high concentration in the periphery is formed in the epitaxial layer. As a result, it is possible to manufacture a high-speed bipolar transistor with a high peak value of cut-off frequency and a high collector current range in which the drop occurs. Moreover, the impurity profile can be formed in a minute region by a simple method without the need for special equipment such as a focused ion beam implanter, and the transistor can be manufactured at low cost. .

In the above embodiment, polycrystalline silicon to which no impurities have been added was subjected to lateral diffusion and then removed, but it is not necessary to remove the polycrystalline silicon. However, if it is not removed, the lateral impurity profile will change due to further lateral diffusion during thermal oxidation after the lateral diffusion, which will reduce the controllability of the profile. It is preferable to do so.

Furthermore, the shape shown in FIG. 1c can be formed not only by the steps shown in FIGS. It is possible.

Furthermore, although the above embodiments have shown a method for manufacturing an NPN transistor, it goes without saying that a PNP transistor can also be manufactured in accordance with this method.

[Effects of the Invention] As described above, according to the method for manufacturing a bipolar transistor of the present invention, a lateral impurity profile can be formed in the base region by a simple method, and the peak value of the cutoff frequency and its drop can be reduced. A high-speed bipolar transistor with an improved collector current range can be manufactured at low cost.

[Brief explanation of the drawing]

1a to 1h are cross-sectional views showing some steps in the method for manufacturing a bipolar transistor of the present invention, and FIG. 2 is a diagram showing a lateral impurity profile in the base region of the transistor of FIG. 1h,
Figures 3a and 3b are cross-sectional views and planar pattern diagrams showing an example of a bipolar NPN transistor;
The figure shows the lateral impurity profile in the base region of the transistor of FIG. 3a. 1...N-type epitaxial layer, 2...Silicon oxide film, 2'...Silicon nitride film, 3'...Base electrode extension material (polycrystalline silicon film), 4, 4'...
...Silicon oxide film, 5...Polycrystalline silicon film without addition of impurities, 5'...Polycrystalline silicon having lateral impurity profile, 6...Base region, 6
₁ ... Internal base area, 6 ₂ ... External base area,
7...Emitsuta area.

Claims (1)

[Claims] 1. A step of selectively forming a base electrode extension portion made of a first polycrystalline silicon film containing a high concentration of impurities on the surface of a semiconductor substrate, and A step of depositing a second polycrystalline silicon film without addition of impurities on the surface, and diffusing impurities laterally from the first polycrystalline silicon film into the second polycrystalline silicon film by thermal diffusion to form a predetermined amount. A lateral diffusion step that forms a lateral impurity profile, followed by thermal diffusion to diffuse impurities from the impurity-containing polycrystalline silicon on the substrate surface into the substrate, with a low concentration in the center and a high concentration in the periphery. a base region forming step of forming a base region having a lateral impurity profile. 2. Between the lateral diffusion step and the base region forming step, further comprising a step of removing by selective etching a portion of the impurity-free second polycrystalline silicon film in which the impurity has not been diffused. A method for manufacturing a bipolar transistor according to claim 1, characterized in that: