JPH01222617A - Digital relay - Google Patents

Abstract

PURPOSE:To detect a failure of the power line in high speed, by sampling the electricity from the power line with two microprocessor, on which the sampling timing is time-shifted and the detected and processed data are stored in common memory. CONSTITUTION:The data from the power line are converted by an input converter 1(PT, CT) and given to the CPU1, CPU2 respectively through the A/D converter 2. The interrupt signal of CPU1, CPU2 is controlled by an interrupt control circuits 10, 12. The sampling timing of CPU1, CPU2 is shifted and the samplings are carried out by both machine. The sampled data and processed data are stored in a common memory 13. In case the failure happened on the power line, the processed result of the main relay processing by CPU1, CPU2 are output to the output interface circuit 4 and the fail safe processing results are output the output interface 5. And-circuit 6 triggers the trip signal if the both circuits give the error outputs. By this reason, high speed shut down can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital relay device that outputs a shutdown command as necessary when an accident in an electric power system is detected.

[Conventional technology]

Figures 5 and 6 are, for example, "Electric Cooperative Research" Vol. 41, No. 4.
This is a hardware configuration diagram and relay processing time chart of a conventional digital relay device shown in No. P34 and PI3 (published by the Electric Cooperative Research Association on January 21, 1986). 2 is an input converter that inputs current and voltage from the power system, and 2 supplies analog signals of current and voltage input by this input converter 1 to an analog/digital converter via a filter, a sampling holder, and a multiplexer. An analog/digital converter (hereinafter referred to as A/D converter) 3 that converts into a digital signal uses the data converted by the A/D converter 2 to perform main relay processing and fail-safe relay processing. A microprocessor, 4 is a main relay output interface circuit that outputs the judgment output of the main relay processing of the microprocessor 3, and 5 is a fail-safe relay output interface that outputs the judgment result of the fail-safe relay processing of the microprocessor 3. A circuit 6 is an output circuit which performs an AND operation between the main relay output interface circuit 4 and the fail-safe relay output interface circuit 5 and outputs an output to the outside of the digital relay device.

Next, the operation will be explained. The current and voltage of the power system taken into the digital relay device by the input converter 1 are converted into digital signals via the A/D converter 2.

After receiving the interrupt signal, the microprocessor 3 reads the digital signal and performs main relay processing and fail-safe relay processing. When an accident occurs in the power system, an output signal is output from the microprocessor 3 to each of the main relay output interface circuit 4 and the fail-safe relay output interface circuit 5. If both the main relay and the fail-safe relay detect an accident in the power system, the output circuit 6 outputs a shutdown command to the outside of the digital relay device.

Next, a time chart of the relay processing performed by the microprocessor 3 will be explained based on FIG.

In this example, the operation at time 11 will be explained. After the current and voltage of the power system are A/D converted at sampling timing, the input data is read into the microprocessor 3 by a CPU interrupt. The data input is then processed and
This data is stored in the memory as data at time point 11, and the relay physiognomy is processed using this data and other data such as current and voltage data at time to that was stored in the memory at the previous sampling timing. After that, relay B phase processing is carried out, and these series of calculation results are stored in memory, and comparison and sequence processing are performed with this stored result and the previously stored result, etc., and judgment is made at the current timing. It is determined whether or not to output. For example, in the case of a method that outputs after checking twice, the output timing is 11 if it is determined that the relay is to operate (a trip command should be issued) at time tQ, and then 11 if it is determined that the relay is to operate at time 11.
It is determined to be a judgment output at this point. In this way, all the processing is completed, and the next 12 points in time arrive, and the same processing is repeated. One micro processor like this? 3 for the main relay and for the fail-safe relay.
L'-can perform processing functions. Furthermore, the microprocessor 3 constantly performs monitoring processing within one sampling interval. That is, for example, in a memory monitoring thumb check, the program memory is monitored for defects by adding up all the stored contents of the read-only memory, which is the program memory, and verifying whether the addition result matches a predetermined value. ing.

[Problem to be solved by the invention]

Conventional digital relay devices are configured as described above, so in order to detect power system faults at high speed and shut down the system, it is necessary to shorten the sampling interval. Since main relay processing and fail-safe relay processing are performed in the system, there is a limit to how short the sampling interval can be shortened depending on the processing capacity of the microprocessor. Furthermore, although the microprocessor itself checks itself in order to prevent unnecessary responses due to hardware and software defects, there is a problem in that defects cannot be completely detected.

This invention was made in order to solve the above-mentioned problems, and when an accident occurs in the power system, it is possible to detect the accident at high speed, shut down the system, and improve the reliability of the microprocessor. The purpose of this invention is to obtain a digital relay device.

[Means to solve the problem]

The digital relay device according to the present invention has a multi-unit configuration in which two microprocessors are provided, the sampling timings for taking in data are staggered, and a memory for storing data and calculation results is shared.

[For production]

The two microprocessors in this invention independently read the current and voltage of the power system at different sampling timings, and store a series of data necessary for processing in a memory shared by the two microprocessors. Then, unique processing is performed using this series of data, and the uniquely processed calculation results are stored in a shared memory, compared with the past, and sequenced, and whether the judgment should be output at the current timing. Decide whether or not. It's a moat, hardware.

By storing constant software monitoring data in a shared memory, the microprocessors of the other party are mutually monitored.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same or equivalent components as in FIG. 5 are given the same reference numerals, and redundant explanation will be omitted. In Figure 1,
10 is an interrupt control circuit that outputs an interrupt signal to the microprocessor (CPU 1) 3; 11 is a microprocessor that uses the data converted by the A/D converter 2 to perform main relay processing and fail-safe relay processing; Processor (
The CPUs 2) and 12 are interrupt control circuits for outputting interrupt signals to the microprocessor 11, and 13 is a common memory circuit for storing data and results processed by the microprocessors 3 and 11.

In the fourth example, ST1 is a monitoring determination step of the microprocessor 3, s'r2il-1: common memory circuit 13
ST3 is a step of storing defective data in the common memory circuit 13. ST4 is a step of reading data of the microprocessor 11 (CPU2 data) from the common memory circuit 13. ST5 is a step of reading the data of the microprocessor 11 (CPU2 data) from the common memory circuit 13.
Step ST6 is a step of determining whether or not the CPU 2 data matches the normal data.
This step is determined to be defective.

Next, the operation will be explained. 1. According to input converter 1)
The electric current and voltage of the power system introduced into the digital relay device are converted into digital signals by the A/D converter 2. The microprocessor 3 receives the interrupt signal from the interrupt control circuit 10, and the microprocessor 11 reads the digital signal from the A/D converter 2 and performs main relay processing and fail-safe processing. Perform relay processing. The input data used for these relay processes and the determination results of the relay processes are stored in the common memory circuit 13.

When an accident occurs in the power system, the determination results of the main relay processing by the microprocessors 3 and 11 are output to the main relay output interface circuit 4. Furthermore, the determination results of the fail-safe relay processing by the microprocessors 3 and 11 are output to the fail-safe output interface circuit 5. When both the main relay and the failsafe relay detect an accident in the power system, the output circuit 6 outputs a cutoff command to the outside of the digital relay device.

Next, a time chart of the main relay processing and the 7 fail safe relay processing processed by the microprocessor 3.11 will be explained based on FIG. In this example 1
The operation at one point in time will be explained. First, the current and voltage of the power system are A/D converted at sampling timing, and then the CPU1 interrupt signal is sent to the microprocessor 3 (CPU1
input data is read in (processing). The data input is then processed and stored in the common memory circuit 1 as 11 point data.
3 is stored. The common memory circuit 1 uses this 11 point data and the microprocessor 11 (CPU 2 processing).
Relay A phase is processed using a series of data at point 10101 stored in step 3. Thereafter, processing of relay B phase, relay C phase, etc. is carried out, and the results of these series of calculations are stored in the common memory circuit 13, and the results stored in this common memory circuit 13 and the microprocessor 11 (C
In 1) U2 processing), comparison with the calculation results stored in the common memory circuit 13 and sequence processing are performed, and it is determined whether or not a judgment should be output at the current timing.

For example, in the case of double verification, the output timing is at time 101 when the microprocessor 11 (CPU2 processing) determines that the relay is operating, and then at time 11 when the microprocessor 3 (CPUl processing) determines that the relay is operating, the output timing is at the 11th time. Microprocessor 3 with interrupt (CPU 1 processing)
It is determined that the output is a failure judgment output. In the conventional technology, judgment output was performed at twice the conventional one sampling interval, but in this invention, the data sampling interval is 1/2 of the conventional one, so the time equivalent to 1.5 times the conventional one sampling interval is output. This enables high-speed operation.

After completing all the processing as described above, the next time point 111 arrives, and the microprocessor 11 (CPU2 processing)
The same process is repeated. For the above-mentioned relay processing, the microprocessors 3 and 11 are separately provided for main relay and fail-safe relay.

Next, a time chart of the constant monitoring process performed by the microprocessors 3 and 11 and a flow of the constant monitoring process of the microprocessor 3 will be explained based on FIGS. 3 and 4. In this example, the operation at time t1 will be explained. First, microprocessor 3 (CPU processing)
At step 5Tl, the microprocessor 3 itself performs a CPU1 monitoring determination (step 5Tl), and if the determination result is normal, it is stored in the common memory circuit 13 as CPU1 data (
step ST), if it is defective, the common memory circuit 13 is
It is stored as PU2 data (step ST3).

Next, microprocessor 11 (
CPU2 data, which is the determination result of CPU2 monitoring determination by CPU2 processing), is read by the common memory circuit 13 (
Step 8T4), determine whether the CPU2 data matches normal data (CPU2 data determination) (
Step 8T5). If the determination results do not match, it is determined that the microprocessor 11 is defective and is output (step 5T6). In this way, microprocessor 3
The constant monitoring process (CPUl process) is finished, and the next 111
At the time, microprocessor 11 (CPU 2 processing)
The same process is repeated. In this way, the CPU
They are configured to mutually monitor each other for defects.

In the above embodiment, the judgment outputs of two microprocessors are output to two output interface circuits, but it is possible to combine the output interface circuits into one.
It may also be configured to receive the output of one microprocessor.

1. In the above embodiment, the sampling timings are shifted so that the current and voltage of the power system are independently read into the two microprocessors as data, but one microprocessor reads the current and voltage of the power system at each sampling timing. When the data is read and one microprocessor finishes processing, this one microprocessor issues an interrupt instruction to the other microprocessor that is not related to the sampling timing, reads the power system current and voltage data, and starts processing. K to start
You may.

In addition, in the above embodiment, two microprocessors read the current and voltage data of the power system, but one microprocessor reads the current and voltage data of the power system at its own electric station, and the other microprocessor reads the current and voltage data of the power system at its own electric station. The microprocessor may also receive data from other electrical stations via an information transmission line.

〔Effect of the invention〕

As described above, according to the present invention, the arithmetic processing section of the digital relay device is configured with two microprocessors, the sampling timing of data input to the microprocessor is shifted, and the data storage location is configured with two microprocessors. Since the system is configured so that the microprocessors of the system are shared, it is possible to detect an accident in the power system at high speed, shut down the system, and protect the system, and also to improve reliability.

[Brief explanation of the drawing]

Fig. 1 is a hardware configuration diagram of a digital relay device according to an embodiment of the present invention, Fig. 2 is a time chart of the relay processing shown in Fig. 1, Fig. 3 is a time chart of the constant monitoring processing, and Fig. 4 is a FIG. 5 is a processing flowchart of the constant monitoring processing, FIG. 5 is a hardware configuration diagram of a conventional digital relay device, and FIG. 6 is a time chart of the relay processing of FIG. 5. In the figure, 3.11 is a microprocessor, and 13 is a common memory circuit. Patent applicant: Mitsubishi Electric Corporation Procedural amendment (voluntary) 1. Description of the case Japanese Patent Application No. 63-46394 2 Title of the invention Digital relay device 3 Person making the amendment 6 Contents of the amendment (1) The specification is amended as follows. (2) Figure 4 is corrected as shown in the attached sheet. 7. One or more documents containing the amended Figure 4 of the attached documents

Claims (1)

[Claims] In a digital relay device that protects the power system by outputting a shutdown command by detecting an accident in the power system, the amount of electricity in the power system is alternately taken in at each sampling timing and arithmetic processing is performed, A digital relay device comprising two of the above microprocessors, each of which performs its own processing using a series of data stored in a common memory circuit that stores the above electrical quantities and calculation results.