JP2006320101A - Digital relay device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a digital relay device that secures reliability against a malfunction by a simple circuit that minimizes the increase of a hardware quantity in a single memory element. <P>SOLUTION: In this digital relay device provided with an A-D converter that takes in a system current, and a protective arithmetic processing portion composed of an A-D conversion data reading-in processing portion, a protection element calculation portion, and a protection logic portion and that detects an abnormality of the system to perform trip operation by operating the protection calculation processing portion, at least one of a calculation memory and a fixed data memory used at the protective arithmetic processing portion is structured in duplex by separating a memory region in the single memory element. Each memory region is alternately used at each conversion sampling by the A-D converter. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention includes a protection arithmetic processing unit that converts analog data of a power system into digital data, stores the digital data in a memory, and uses the data to perform calculation and determination processing necessary for system protection. The present invention relates to a digital relay device.

  In the conventional digital relay device, various double protection processes are performed in order to improve the accident detection accuracy in the power system. For example, as disclosed in Japanese Patent Application Laid-Open No. 2002-186162 (Patent Document 1), the amount of electricity in the power system is taken into the protection arithmetic processing unit and the control processing unit via the A / D conversion unit, and the protection function and the control processing unit Some have realized double protection by taking the logical product with the accident detection function. This is because when a trip signal is output as an output signal from a single hardware, there is a risk of erroneous output due to hardware failure.

  However, since the protection arithmetic processing unit and the control processing unit are separated from each other in hardware, the above-mentioned Patent Document 1 causes an increase in the size of the device using a plurality of LSI chips and an increase in manufacturing cost. In addition, the purpose of duplicating the arithmetic processing unit hardware is based on the idea of lowering the probability of malfunction due to component failure, but the probability that it will not operate when it should operate due to component failure at the time of hardware duplication, That is, there is a problem that the failure rate increases due to an increase in the malfunction probability or an increase in the amount of hardware itself.

  Moreover, even if the component is not defective, countermeasures have been taken to duplicate the subsequent operation including the AD converter for the malfunction caused by temporary garble of the AD converter output digital data. In addition, it has the disadvantages of increasing the amount of hardware and the resulting increase in the component defect rate. Furthermore, when fixed data such as settling data used for output judgment of the arithmetic processing unit becomes abnormal, the arithmetic processing unit output may be erroneous output, and this erroneous output is caused because the fixed data is used forever. Are continuously output. Normally, this erroneous output cannot be directly output as a logical product with the accident detection unit of the control processing unit, but the accident detection of the control processing unit is highly sensitive so that it can be operated even in an external accident outside the protection range of the normal system. Therefore, there is a problem that a logical product is established and a trip signal may be erroneously output when an accident is detected by the control processing unit in the event of an external failure while the above state continues.

  On the other hand, in Japanese Patent Application Laid-Open No. 2004-336830 (Patent Document 2), the protection arithmetic processing unit and the control processing unit are built on one chip, and a single computer has a dual protection processing function. However, it is necessary to build the protection processing unit and control processing unit separately on the chip, which increases the chip area, and malfunctions due to hardware or software failure of the one-chip computer. In order to prevent this, there is a problem in that it is necessary to externally install a pattern determination circuit that outputs pattern data in which a protection output is encoded from a digital output circuit and compares / determines this pattern data with a reference pattern.

JP 2002-186162 A (refer to claim 1 and FIG. 1) JP 2004-336830 A

By the way, as a defective object to be considered by the present invention,
(1) Prevention of malfunction due to temporary bit corruption of digital data output from the AD converter.
(2) Prevention of malfunction due to a partial failure of the CPU memory for executing the protection operation,
(3) To prevent malfunction caused by a partial failure of a memory that stores fixed data such as settling data used for operation output determination in the protection arithmetic processing unit.

  The reason for the temporary bit corruption of the AD converter in the item (1) is that, conventionally, a method of checking the digital data by inputting a specified voltage every sampling period as a fault detection of the AD converter. Although it is possible to detect a permanent failure due to a defective AD converter quickly, digital data of a voltage other than the periodic sampling of the specified voltage is not detected. This is because the data used for is not monitored and the temporary bit corruption was unprotected.

In addition, the reason for targeting the partial failure of the CPU arithmetic memory in the item (2) can be confirmed to some extent by a sampling check of only a specific memory element (region) at present for the failure over the entire memory area, Although it was possible to detect relatively quickly, an entire area check is necessary to detect a defect in a partial area of the target memory for this time, and this entire area check requires a check from the CPU burden to several samplings. This is because the protection element is inappropriate for a device that requires high-speed operation and is unprotected to prevent malfunction.

  Furthermore, fixed data such as setting data in (3) is usually stored in a non-volatile memory, duplicated on this non-volatile memory, and stored in the operation memory via coincidence detection when used. For this reason, it is possible to prevent a malfunction from occurring when the nonvolatile memory is abnormal. However, if the arithmetic memory is also duplicated, it is necessary to detect coincidence each time it is used, which is a burden on the CPU processing, which is a disadvantage of the duplication of the arithmetic memory. Here, as in the item (2), a partial failure of the arithmetic memory is targeted.

The present invention has been made in order to solve the above-described problems. A first object of the present invention is to provide a single protection arithmetic processing hardware (not separated for main detection and accident detection). It is an object of the present invention to realize a digital relay device capable of ensuring reliability against malfunctioning with a simple circuit in which an increase in amount is minimized.
The second purpose is that the AD converter output is temporarily garbled, the memory element chip for operation is abnormal (partial failure), or the memory element chip that contains fixed data such as settling data (partial failure) It is possible to obtain a digital relay device that can prevent malfunction due to the above.
Furthermore, a third object of the present invention is to realize a digital relay device having a hardware configuration in which a malfunction / probability probability and a malfunction probability are balanced.

  The digital relay according to the present invention includes an AD converter that captures a system current, and a protection operation processing unit that includes an AD conversion data reading processing unit, a protection element operation unit, and a protection logic unit, and executes the protection operation processing unit. In a digital relay device that detects a system fault and performs a trip operation, the memory area is separated in a single memory element for at least one of the arithmetic memory and fixed data memory used in the protection arithmetic processing unit. In this configuration, each memory area is alternately used for each conversion sampling of the AD converter.

  In the present invention, the area of the memory element that stores the digital data is divided in a configuration that suppresses the increase in the amount of hardware, or the memory element itself is duplicated and used alternately so that the AD converter output is temporarily It is possible to prevent erroneous output due to a bit error, an abnormality (partial failure) of a memory element chip for calculation, and an abnormality (partial failure) of a memory element chip storing fixed data such as settling data.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing an embodiment of a digital relay device according to Embodiment 1 of the present invention. In the figure, 100 indicates a system to be protected, 1 is a CT for capturing the system current (PT for capturing a voltage is omitted in this figure), 2 is a digital relay device, and 3 is the system described above. An AD converter 4 for digitally converting the input in the relay is a protection arithmetic processing unit composed of a CPU, a memory element, and the like. The protection arithmetic processing unit 4 is a switching circuit 7 that outputs digital data of the AD converter 3 alternately to two routes for each AD sampling by a control signal (not shown), and a first circuit that forms the two routes. The protection arithmetic processing unit 10 and the second protection arithmetic processing unit 20 are included.

  The first protection arithmetic processing unit 10 receives the data of the first read processing unit (R1) 111 that receives an AD output signal, which is one of the switching circuit outputs of the switching circuit 7, as input. A first protection element calculation unit (A1) 121 that uses the protection element calculation to determine an element operation output and uses a first protection logic unit (L1) 131 that receives the output of the first protection element calculation unit 121 as an input. Has been. On the other hand, the second protection arithmetic processing unit 20 is similarly composed of a second read processing unit (R2) 112, a second protection element arithmetic unit (A2) 122, and a second protection logic unit (L2) 132. Yes.

  Furthermore, 141 is a first calculation memory M1, 151 used in the first protection calculation processing unit 10, and first fixed data memories S1, 142 such as settling data used for the calculation of the first protection calculation processing unit 10 are The second calculation memories M2 and 151 used for the calculation of the second protection calculation processing unit 20 are a second fixed data memory S2 such as settling data used for the calculation of the second protection calculation processing unit 20.

  The calculation memory 141 used by the first calculation processing unit 10 and the calculation memory 142 used by the second calculation processing unit are configured by clearly dividing an area in a single memory element. Similarly, the fixed data memory 151 used by the protection element calculation unit 121 and the protection logic unit 131 and the fixed data memory 152 used by the protection element calculation unit 122 and the protection logic unit 132 are also included in a single memory element. The area is clearly divided.

  Reference numeral 51 denotes an auxiliary relay driver with a latch circuit that receives the output of the first protection logic unit 131 as an input, and latches and outputs the signal of the 131 until the output in the next sampling. 61 is an auxiliary relay driven by 51, 52 is an auxiliary relay driver with a latch circuit that receives the output of the second protection logic unit 132, 62 is an auxiliary relay driven by the 52, and 61 is a trip output. , 62 are connected in series to form a logical product, and the trip line 200 is activated when the contacts x1, x2 are simultaneously closed.

  The operation of the first embodiment will be described based on the calculation flowchart of the protection calculation processing units 10 and 20 in FIG. First, the calculation route is selected by the switching circuit 7 (FIG. 1). That is, the route 1 (execution of the first protection arithmetic processing unit 10) and the route 2 (execution of the second protection arithmetic processing unit 20) of the protection arithmetic processing units 10 and 20 are switched alternately. It is done. First, if route 1 is selected (step S1), AD data is read by the first reading processing unit R1 111 and stored in the memory M1 141 (step S2). The protection element calculation unit A1 121 executes relay calculation of the protection element using the M1 data (step 3).

  The settling data is read from the memory S1 151 (step S4), and the data is used to perform comparison judgment processing with the relay calculation result, or after collating with the previous judgment result as necessary, the result is output as a protection element. Is stored in the M1 memory 141 (step S5). Next, the settling data used for the logic operation in the protection logic unit L1 is read from the memory S1 of 151 (step S6), and the logic operation is executed together with the protection element output data in the M1 memory (step S7). The result is stored in the memory M1 141 and the DO signal is output (step S8).

  That is, if the determination result is detected as abnormal, a signal for operating one contact x1 constituting the logical product is output. At the next timing, the route is set to 2 in order to calculate the route 2 side (step S9). Similarly, the same processing (steps S2 ′ to S9 ′) as that of the route 1 is performed on the route 2 side. In this case, the memory used is 142 memory M2 and the settling data is 152 memory S2. At the end of the process, the route is set to 1 at the next timing, and the process ends (step S9 ').

FIG. 3 is a time chart for explaining the operation of the digital relay device shown in FIG.
In the figure, (a) shows the digital data conversion timing of the AD converter 3, (b) shows the processing time of the first protection arithmetic processing unit 10, and (c) shows the processing time of the second protection arithmetic processing unit 20. The horizontal axis is time. Assuming that the processing times of the protection arithmetic processing units 10 and 20 are T1 and T2, the AD conversion timing is controlled so that T1, T2, T1, and T2 are continued. That is, the first read processing unit (R1) 111, the protection element calculation (A1) 121, and the protection logic unit (L1) 131 of the first protection calculation processing unit 10 are executed in the T1 time, and the second read in the T2 time. The second read processing unit (R2) 112, the protection element calculation (A2) 122, and the protection logic unit (L2) 132 of the protection calculation processing unit 20 are executed. Then, the first and second protection arithmetic processing units 10 and 20 are executed in time T (= T1 + T2), which corresponds to the sampling interval of the conventional relay.

  In this way, even if the CPU element itself is single, the memory area to be used is divided by the first protection arithmetic processing unit 10 and the second protection arithmetic processing unit 20, so that the temporary conversion of the AD converter output digital data is garbled. If the AD data fetched on the route 2 side is correct even if the computation (first protection computation processing unit) output in the route 1 malfunctions, the route 2 (first protection computation processing unit) Will be correct and will eventually prevent malfunction. Further, even if a partial failure occurs in the CPU operation memory that is executing the protection operation, a partial failure occurs in, for example, M1 (first protection operation processing unit memory) in the case of a partial memory element failure. However, although there is a possibility of erroneous output in the route 1, similarly, if the memory of the route 2 is normal, the output of the route 2 is correct and finally malfunction is prevented.

Furthermore, even if a partial failure occurs in the memory that stores fixed data such as settling data used for operation output determination in the protection arithmetic processing unit, the malfunction is finally prevented in the same manner as described above.
Further, the first and second arithmetic processes are executed during the normal AD conversion timing, and the output is logical product so that the operation time of the relay is not affected.
In the above description, the memory element is divided into areas in a single memory, but it may be a separate memory element if the hardware configuration permits.

Embodiment 2. FIG.
In the first embodiment, the first and second protection operation processing units are provided, and the digital data after AD conversion is alternately stored in different areas on the memory element, and the first and second data are used by using the data. In the second embodiment, the protection arithmetic processing is alternately executed by using different memory areas, and the logical product of the outputs is taken as a trip signal. In the second embodiment, the digital data after AD conversion is The calculation data R1 in the first protection element calculation unit A1 and the calculation data R2 in the second protection element calculation unit A2 are stored in the divided memories M1 and M2, respectively, and alternately according to the AD conversion timing. The protection logic unit commonly processes the data alternately processed at the AD conversion timing. Also, fixed data such as settling data used in the protection logic unit is obtained alternately from different memory areas S1 and S2 in accordance with AD conversion.

  In FIG. 4, reference numeral 13 denotes a protection logic unit L which alternately inputs the outputs of the first and second protection element calculation units 121 and 122 in accordance with the AD conversion timing via the switching circuit 16. The calculation is performed using the memory M. 17 is for inputting fixed data such as settling data used for the calculation of the protection logic unit 13 alternately in the first fixed data memory S1 and the second fixed data memory S2 in accordance with AD conversion timing. It is a switching circuit. Reference numeral 5 denotes an output driver with a latch circuit that receives the output of the protection logic unit 13, and reference numeral 6 denotes an auxiliary relay that receives the output of the output driver 5 as an input, and this output constitutes a trip signal. Next, the operation will be described with reference to the calculation flowchart of FIG.

  In FIG. 5, first, AD data reading is executed in the protection arithmetic processing section (step 10). At this time, the first reading process R1 111 and the second reading process R2 112 are performed and stored in M1 of the memory 141 and M2 of the memory 142, respectively. Thereafter, the calculation route is selected so that route 1 (execution of the first protection element calculation processing unit 10) and route 2 (execution of the second protection element calculation processing unit 20) are executed alternately ( Step 11). First, route 1 will be described. The protection element calculation unit A1 121 executes relay calculation of the protection element using the M1 data read in R1 (step 12).

  The settling data is read from the memory S1 of 151 (step 13), and the data is used to perform the comparison judgment processing with the relay calculation result (after checking with the previous judgment result if necessary) as M1 of 141 as a protection element output. The data is stored in the 14 memory M that is shared with the memory (step S14). At the next timing, the route is set to 2 in order to calculate the route 2 side (step S15). Next, the settling data used in the logic unit in the protection logic unit L is read from the memory S1 of 151 (step S16) (Here, it is assumed that the data is read from S2 in the case of Route 1 and from S1 in the case of Route 2. This is because the route is changed so that the route can be switched in the next sampling after the A2 processing), and the logic operation is executed together with the protection element output data in the M1 memory (step S17), and the result is shared. It is stored in the memory 14 and outputs a DO signal (step S18).

  FIG. 6 is a time chart for explaining the operation of the second embodiment of the present invention. In FIG. 6, (a) is a digital data conversion timing of the AD converter 3, and (b) is a first protection element calculation unit ( A1) 121 processing time, (c) indicates the processing time of the second protection element calculation unit (A2) 122, (d) indicates the operation timing of the protection logic unit 13, and the horizontal axis indicates time. The AD data is fetched by both the first read processing unit (R1) 111 and the second read processing unit (R2) 112, but the protection element calculations 121 and 122 are executed at alternate sampling periods. The logic operation L is executed using the data stored in the common memory 14. The settling data used at that time is fetched from the storage memories (S1) 151 and (S2) 152 in which the memory area is divided for each sampling.

In this embodiment, by alternately taking in AD data, it is possible to prevent malfunctions from temporary bit corruption of the AD converter. Furthermore, since the duplicated settling data is used alternately, it is possible to prevent malfunctions due to partial defects in the settling data storage memory. In addition, since the calculation memory is duplicated and alternately used for the protection element calculation, malfunction can be prevented against a partial abnormality of the protection element calculation memory.
Note that the memory area of the protection logic unit (L) 13 is not divided and is single (processed in common), so that there is a possibility of malfunction due to an abnormality in the memory used for logic operation compared to the first embodiment. However, this can be solved by taking the following measures.

  That is, since the logic operation result is performing an operation such as logical product or logical sum, 1 (ON) and 0 (OFF) results can be indicated, and 1 (ON) and 0 (OFF) are patterned. By doing so, it is possible to detect memory abnormalities. In other words, it can be distinguished from a normal memory abnormality by setting ‘1’ = 1010 −−−−−− 10 (for example, 16-bit data). In addition, by setting the operating side output as certain pattern data and the non-operating side output as non-pattern data, the probability of becoming the operating side pattern data determined at the time of memory abnormality is extremely low, so the memory area should be separated. And malfunction can be prevented. As described above, the logic operation unit can achieve the same effect as that of the first embodiment without separating the memory area, and the increase of the memory area can be suppressed as compared with the first embodiment.

Embodiment 3 FIG.
In the first and second embodiments, the digital data after AD conversion is stored in different memory areas and the protection element calculation is performed individually. However, in the third embodiment, the calculation memory used in the protection calculation processing unit is stored. Instead of duplication, fixed data such as settling data is duplicated in different areas and used alternately at AD conversion timing.
AD converter output digital data and protection calculation memory are updated sequentially with AD conversion data, so even if there is a temporary instantaneous data abnormality, output verification processing can be performed multiple times in the protection element calculation unit, so comparison of trip times Trip output can be prevented for long protection relays.

On the other hand, for fixed data, even if there is an instantaneous memory error, if it is changed to abnormal data once, it will not be updated and the abnormal state may continue forever. May not be resolved. For this reason, in the case of an element that does not have a large memory element area, an increase in memory is suppressed as a system in which only fixed data such as settling data is duplicated and used alternately.
In FIG. 7, reference numeral 14 denotes an AD data read processing unit R 11, protection element calculation unit A 12, and protection logic unit L 13, which are calculation memories M and 17 are the AD conversion timings described in the second embodiment. The first and second fixed data memories S1 and S2 of 151 and 152 are switched and used.

Next, the operation will be described with reference to the flowchart of FIG.
In FIG. 8, at the beginning of the protection calculation processing unit, calculation is performed so that route 1 (using the first fixed data memory S1) and route 2 (using the second fixed data memory S2) are alternately executed. A route is selected (step 20), and the next route is set so that the route is switched at the next sampling. Thereafter, the AD data is read by the 11 reading processing unit R and stored in the memory M 14 (step S23). The protection element calculation unit A of 12 executes relay calculation of the protection element using the M data (step 24).

Next, the settling data used in the logic operation in the protection logic unit L of 13 is read from the memories S1 and S2 of 151 and 152 (step S27) (here, the data is obtained from S2 for Route 1 and from S1 for Route 2. Read out), the logic operation is executed together with the protection element output data in the M memory (step S28), the result is stored in the memory of the common memory 14, and the DO signal is output (step S29).
As can be seen from the time chart of FIG. 9, in accordance with the AD conversion timing of (a), fixed data such as the first and second settling data of (b) is used for the protection element calculation unit and the logic unit. Timing is shown. When the protection element calculation (A) 12 and the logic calculation (L) 13 are executed every cycle, S1 and S2 are alternately used.

  As described above, relays with a relatively long relay operation time are updated at every sampling, so transient errors can be prevented by the time circuit for transient abnormalities, but for fixed data such as settling data, etc. Even if it is a transient abnormality, it may be fixed, but according to this embodiment, this type of malfunction is prevented by duplicating fixed data and using them alternately. This can be prevented with a simple and inexpensive configuration.

Embodiment 4 FIG.
In the third embodiment, fixed data such as settling data is duplicated to prevent erroneous output due to abnormality of the fixed data. However, in the fourth embodiment, AD conversion data and fixed data are duplicated and other data is output. The arithmetic memory is configured to be used from a single memory data. In the third embodiment, it has been described that the AD conversion data can be erroneously output by the multiple verification processing of the protection element calculation output for the abnormality. However, multiple verifications more than the time that can be prevented are necessary. Thus, it is effective only with a protection element having a relatively slow operation time. Therefore, a protection element that requires a short operation time has a risk that the number of comparisons that can prevent erroneous output cannot be secured. Therefore, the data after AD conversion is stored in duplicate.

As described above, in this embodiment, malfunction can be prevented with respect to a temporary abnormality of AD converter output data, and malfunction can be prevented with respect to an abnormality with respect to fixed data such as settling data. Further, an increase in the memory area can be suppressed as compared with the third embodiment, and a circuit configuration can be realized with a small memory.
In FIG. 10, 111 is a first AD conversion data read processing unit (R1), 112 is a second AD conversion data read processing unit (R2), 141 is an AD data storage unit (M1), and 142 is AD data. The storage units (M2), 17, and 18 are switching circuits (SW3) (SW4).

The operation will be described with reference to the calculation flowchart of FIG.
In FIG. 11, first, AD data reading is executed by the protection arithmetic processing unit (step S30). At this time, the first read process R1 111 and the second read process R2 112 are performed and stored in the memory (M1) 141 and (M2) 142 in which the areas are divided. Thereafter, a calculation route is selected so that route 1 (using the first fixed data memory S1) and route 2 (using the second fixed data memory S1) are alternately executed (step 31). Set the next route so that route switching is performed during sampling.

In the protection element calculation unit A of 12, the relay operation of the protection element is executed using data from R1 (M1) in the case of Route 1 and from R2 (M2) in the case of Route 2 (step 34).
Next, the settling data used in the logic operation in the protection logic unit L of 13 is read from the memories S1 and S2 of 151 and 152 (step S35) (here, the data is obtained from S2 at the time of Route 1 and from S1 at the time of Route 2. Read out), the logic operation is executed together with the protection element output data in the M memory (step S38), the result is stored in the memory of the common memory 14, and the DO signal is output (step S39).

FIG. 12 is a time chart illustrating the operation of the fourth embodiment of the present invention. In the figure, (a) is the digital data conversion timing of the AD converter 3, (b) is the processing time of the first AD data storage unit 141, (c) is the processing time of the second AD data storage unit 142, ( d) shows the processing timing of the protection element calculation unit A and the logic unit L of the protection calculation processing unit. The time chart which shows use of fixed data, such as 1st and 2nd settling data according to AD conversion timing, to a protection element calculating part (A) and a logic part (L) is shown. The AD data is taken in both the first AD conversion data read processing unit (R1) and the second AD conversion data read processing unit (R2) within the same sampling period, and the data is alternately used for each sampling. The protection element calculation A and the logic calculation L are executed using the data stored in the common memory 14 as the calculation memory. The settling data used at that time is fetched from the storage memories 151 (S1) and 152 (S2) in which the memory areas are divided by the sampling by the selection circuit (SW3) 17.
Even in this embodiment, the protection element calculation unit and the logic calculation unit can bring about the same effect as in the first embodiment without separating the memory area. Can be suppressed.

1 is a block diagram of a digital relay device showing Embodiment 1 of the present invention. It is an operation | movement flowchart figure explaining Embodiment 1 of this invention. It is a time chart figure explaining operation | movement of Embodiment 1 of this invention. It is a block diagram of the digital relay apparatus which shows Embodiment 2 of this invention. It is an operation | movement flowchart figure explaining Embodiment 2 of this invention. It is a time chart figure explaining operation | movement of Embodiment 2 of this invention. It is a block diagram of the digital relay apparatus which shows Embodiment 3 of this invention. It is an operation | movement flowchart figure explaining Embodiment 3 of this invention. It is a time chart figure explaining operation | movement of Embodiment 3 of this invention. It is a block diagram of the digital relay apparatus which shows Embodiment 4 of this invention. It is an operation | movement flowchart figure explaining Embodiment 4 of this invention. It is a time chart figure explaining operation | movement of Embodiment 4 of this invention.

Explanation of symbols

1 CT for electric power,
2 Digital relay device,
3 AD converter,
4 Protection arithmetic processing unit 5, 51, 52 Auxiliary relay driver,
6, 61, 62 Auxiliary relay,
7, 16, 17, 18 switching circuit,
10 1st protection arithmetic processing part,
20 second protection arithmetic processing unit,
11 AD data reading processing unit,
111 a first reading processing unit,
112 a second reading processing unit;
12 Protection element calculation part,
121 a first protection element calculation unit,
122 second protection element calculation unit,
13 Protection logic part,
131 a first protection logic unit;
132 second protection logic part;
14 arithmetic memory,
141 first calculation memory;
142 second arithmetic memory,
15 fixed data memory,
151 first fixed data memory;
152 Second fixed data memory.

Claims (5)

  An AD converter that captures system current, and a protection operation processing unit that includes an AD conversion data read processing unit, a protection element operation unit, and a protection logic unit, and detects abnormalities in the system by executing the protection operation processing unit. In a digital relay device that performs tripping operation, at least one of the calculation memory and fixed data memory used in the protection calculation processing unit has a double memory configuration in which a memory area is separated in a single memory element. A digital relay device characterized in that the areas are alternately used for each conversion sampling of the AD converter.   The protection calculation processing unit is configured to be duplicated for all of the AD conversion data reading processing unit, the protection element calculation unit, and the protection logic unit, and the calculation memory and fixed data memory of the redundant protection calculation processing unit 2. The digital relay device according to claim 1, wherein each of the memory areas is separated into a double structure, and each memory area is alternately used for each conversion sampling of the AD converter.   The protection calculation processing unit is configured by duplicating the AD conversion data reading processing unit and the protection element calculation unit by separating the memory area, and the protection logic unit is configured in common. The memory area of the processing unit of the processing unit and the memory area of the fixed data memory are separated to form a duplex structure, and each memory area is alternately used for each conversion sampling of the AD converter. Digital relay device.   Each of the protection calculation processing units is composed of a single AD conversion data read processing unit, a protection element calculation unit, and a protection logic unit, and separates the memory area of the fixed data memory for the protection calculation processing into a duplex configuration. 2. The digital relay device according to claim 1, wherein each memory area is alternately used for each conversion sampling of the AD converter.   The protection calculation processing unit is configured to be doubled by separating the memory area for the AD conversion data reading processing unit, and the protection element calculation unit and the protection logic unit are configured in a single configuration. 2. The memory according to claim 1, wherein the memory area for storing the conversion data and the fixed data are separated from each other in the memory area, and the data is alternately used for each conversion sampling of the AD converter. Digital relay device.

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