CN116010148A

CN116010148A - Method, equipment and medium for cross checking data on different CPUs

Info

Publication number: CN116010148A
Application number: CN202211711329.XA
Authority: CN
Inventors: 蒋红军; 路飞; 石文昊; 张金洋; 甘庆鹏
Original assignee: Casco Signal Ltd
Current assignee: Casco Signal Ltd
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2023-04-25

Abstract

The invention relates to a method, equipment and medium for cross checking data on different CPUs, which reads in software mirror images and data in a memory after a train control center is electrified and started, and checks the data after the read-in, wherein the checking comprises checking the reliability of the data in the CPUs and checking the cross reliability of the data among the CPUs. Compared with the prior art, the invention has the advantages of avoiding abnormal system function execution caused by data errors and the like.

Description

Method, equipment and medium for cross checking data on different CPUs

Technical Field

The invention relates to a train signal control system, in particular to a method, equipment and medium for cross checking data on different CPUs.

Background

Along with the continuous development of social economy in China, the demand for railway transportation is also continuously increased. The CTCS-2 level train control system is a train control system which is widely applied in China at present. The train control center equipment is used as an important component of a CTCS-2 level train control system and is also a core of ground safety equipment, and plays a vital role in the stability and safety of train operation.

The logical function operation of the LKD2-KA type column control center is realized through a logical operation board card VLE, each VLE board card consists of two different CPUs, and the 2-out-of-2 safety function is realized through the two different CPUs. Software programs executing on different CPUs and running application data are different. The LKD2-KA type column control center performs system architecture design according to software and data separation, the software is universal for various application scenes, and the data can be independently configured and generated according to different application scenes, so that high requirements on data safety and accuracy are provided.

Therefore, how to avoid abnormal system function execution caused by data errors, thereby affecting the safety of field operation of the equipment, and the method is a technical problem to be solved.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide a method, equipment and medium for cross checking data on different CPUs.

The aim of the invention can be achieved by the following technical scheme:

according to a first aspect of the present invention, there is provided a method for cross-checking data on different CPUs, the method reads in software images and data in a memory after a train control center is powered on, and checks the data after the reading in, wherein the checking includes checking data reliability in the CPUs and checking data reliability cross-checking between the CPUs.

As a preferable technical scheme, the data of each station is generated by a train control data preparation tool, and two binary files, i.e. info1.Dat and info2.Dat, are generated.

As a preferable technical scheme, the binary files respectively generate 32-bit CRC of one binary file and 32-bit CRC of the other binary file and store the 32-bit CRC of the other binary file in a designated memory area.

As a preferred solution, the binary files info1.Dat and info2.Dat are written into two different CPUs, namely into CPU1 and CPU2, respectively.

As a preferred technical solution, the method specifically comprises the following steps:

step S1, powering up and starting a column control center, powering up a logic operation board VLE, and enabling a CPU to enter self-checking;

step S2, after the CPU self-checking of the VLE board is successful, starting to read data;

s3, after the data is successfully read, checking the data validity and the integrity of the CPU aiming at each CPU;

step S4, after the data of the CPU is successfully checked, binary data CRC32 calculated by the CPU is sent to another CPU through the shared memory area, the other CPU continues to check the CRC32, if the data check fails, the system records, and the CPU is restarted;

and step S5, after the verification is successful, the CPU performs a normal running state, and each running period repeatedly performs the step S3 and the step S4 to perform period verification on the validity of the data.

As a preferable technical solution, the step S3 specifically includes:

the CPU calculates the CRC32 of the data in the CPU on line, then compares the CRC32 with the CRC32 stored in the data, considers the data to be normal after the comparison is passed, the CPU can continue to operate, otherwise, the data check is considered to be failed, the system records, and the CPU is restarted.

According to a second aspect of the present invention, there is provided a cross-checking apparatus for data on different CPUs, comprising:

the self-checking module is used for powering on and starting the column control center, powering on the logic operation board VLE, and enabling the CPU to enter self-checking;

the data reading module is used for starting to read data after the CPU self-check of the VLE board card is successful;

the data reliability checking module in the CPU is used for checking the data validity and the integrity of the CPU aiming at each CPU after the data is successfully read;

the inter-CPU data reliability cross checking module is used for sending binary data CRC32 calculated by the CPU to another CPU through the shared memory area after the data check of the CPU is successful, and the other CPU continuously checks the CRC32, if the data check fails, the system records, and the CPU is restarted;

and the periodic checking module is used for carrying out normal running state by the CPU after successful checking, and carrying out periodic checking on the validity of the data in each running period.

As an optimal technical scheme, the specific working process of the data reliability checking module in the CPU is as follows:

As an optimal technical scheme, the data checked by the data reliability checking module in the CPU is generated by a train control data preparation tool.

As a preferable technical scheme, the 32-bit CRC of the data is generated according to the appointed memory region.

According to a third aspect of the present invention there is provided an electronic device comprising a memory and a processor, the memory having stored thereon a computer program, the processor implementing the method when executing the program.

According to a fourth aspect of the present invention there is provided a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the method.

Compared with the prior art, the invention has the following advantages:

1. the 2-out-of-2 safety processing of the train control center not only is performed on the software of the double CPUs, but also is performed on the operation data of the double CPUs, so that the hidden danger of a data common mode is eliminated;

2. the invention checks the validity and the integrity of the data, not only reflects the internal processing of each CPU, but also performs periodic check among the CPUs, and performs multi-level protection check on the reliability of the data;

3. the problem that the system cannot normally operate due to data errors can be intuitively observed in the engineering project implementation stage, and defects in the data production process are avoided, so that the data are output to a station site to influence actual operation.

Drawings

FIG. 1 is a flow chart of the method of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

The invention provides a method for checking the cross reliability of data on different CPUs, which avoids abnormal system function execution caused by data errors, thereby influencing the safety of field operation of equipment.

And the train control center is electrified and started, software images and data in the memory are read in, and the data are checked after the software images and the data are read in, wherein the checking comprises checking of data reliability in the CPU and checking of data reliability cross between the CPUs.

The data of each station is generated by a column control data preparation tool, two binary files, i.e. info1.Dat and info2.Dat, are generated, a 32-bit CRC of the binary file and a 32-bit CRC of the other binary file are respectively generated in the binary files and are stored in a designated memory area, and the binary files, i.e. the info1.Dat and the info2.Dat, are respectively written into two different CPUs, i.e. are respectively written into the CPU1 and the CPU 2.

A specific process flow of the method is shown with reference to fig. 1. The method comprises the following steps:

and step S3, after the data is successfully read, checking the data validity and the integrity of the CPU aiming at each CPU. After the comparison, the data is considered normal, the CPU can continue to operate, otherwise, the data verification is considered to be failed, the system records, and the CPU is restarted;

The overall process flow includes data generation, CRC32 storage, data reading, CRC32 validity checking, periodic checking, error data recording, and CPU restarting. The main implementation code is as follows:

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the invention provides a method for checking the cross reliability of data on different CPUs, which avoids abnormal system function execution caused by data errors, thereby influencing the safety of the field operation of equipment. Based on the method, the problem that the system cannot normally operate due to data errors can be intuitively observed in the engineering project laboratory debugging stage, and the defect existing in the data manufacturing process is avoided, so that the data are output to a station site to influence actual operation.

The above description of the method embodiments further describes the solution of the present invention by means of device embodiments.

The invention also provides a device for cross checking the data on different CPUs, comprising:

The specific working process of the data reliability checking module in the CPU is as follows:

And the data checked by the data reliability checking module in the CPU is generated by a train control data preparation tool. And generating the 32-bit CRC of the data according to the appointed memory region.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the described modules may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again.

The electronic device of the present invention includes a Central Processing Unit (CPU) that can perform various appropriate actions and processes according to computer program instructions stored in a Read Only Memory (ROM) or computer program instructions loaded from a storage unit into a Random Access Memory (RAM). In the RAM, various programs and data required for the operation of the device can also be stored. The CPU, ROM and RAM are connected to each other by a bus. An input/output (I/O) interface is also connected to the bus.

A plurality of components in a device are connected to an I/O interface, comprising: an input unit such as a keyboard, a mouse, etc.; an output unit such as various types of displays, speakers, and the like; a storage unit such as a magnetic disk, an optical disk, or the like; and communication units such as network cards, modems, wireless communication transceivers, and the like. The communication unit allows the device to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processing unit performs the respective methods and processes described above, for example, the methods S1 to S5. For example, in some embodiments, methods S1-S5 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device via the ROM and/or the communication unit. When the computer program is loaded into RAM and executed by the CPU, one or more steps of the methods S1 to S5 described above may be performed. Alternatively, in other embodiments, the CPU may be configured to perform methods S1-S5 in any other suitable manner (e.g., by means of firmware).

The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), and the like.

Program code for carrying out methods of the present invention may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. A method for cross checking data on different CPUs is characterized in that after a train control center is electrified and started, software images and data in a memory are read in, and the data are checked after the software images and the data are read in, wherein the checking comprises checking of data reliability in the CPUs and checking of data reliability cross between the CPUs.

2. The method of claim 1, wherein the data for each station is generated by a column control data preparation tool to generate two binary files info1.Dat and info2.Dat.

3. The method for cross-checking data on different CPUs according to claim 2, wherein the binary files respectively generate a 32-bit CRC of one binary file and a 32-bit CRC of another binary file and store the 32-bit CRCs in a designated memory area.

4. A method of cross-checking data on different CPUs according to claim 2, wherein the binary files info1.Dat and info2.Dat are written to two different CPUs, respectively, namely CPU1 and CPU2, respectively.

5. A method for cross-checking data on different CPUs according to claim 1, comprising the steps of:

6. The method for cross-checking data on different CPUs according to claim 5, wherein the step S3 specifically comprises:

7. A device for cross-checking data on different CPUs, comprising:

8. The device for cross checking of data on different CPUs according to claim 7, wherein the specific working procedure of the data reliability checking module in the CPU is as follows:

9. The device for cross-checking data on different CPUs according to claim 7, wherein the data checked by the data reliability checking module in the CPU is generated by a column control data preparing tool.

10. The apparatus of claim 9 wherein the 32-bit CRC of the data is generated according to a specified memory region.

11. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program, characterized in that the processor, when executing the program, implements the method according to any of claims 1-6.

12. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method according to any one of claims 1-6.