JP4582047B2 - Digital protection controller - Google Patents

Description

  The present invention relates to a digital protection control device, and more particularly to a digital protection control device configured to always collate output results, including monitoring results of analog circuits.

  As a conventional digital protection control device, for example, as described in the chapter “4-2 Improvement of Automatic Monitoring Method” in “Electrical Joint Research Vol. 50, No. 1, Second Generation Digital Relay”, an analog input unit, A digital arithmetic processing unit including a human interface unit, an input / output unit, and a communication interface such as PCM communication are provided.

  In order to check the soundness of the hardware, the conventional devices normally have CPU self-diagnosis processing (known fixed program operation check, invalid check), memory check, parity check, illegal address monitoring, multi-CPU monitoring, etc. The monitoring process is always performed by software. Also, monitoring processing such as analog monitoring and input circuit monitoring, set value comparison check, etc., such as differential current monitoring of analog signals taken from outside, differential voltage circuit monitoring, and the like is executed.

  Also, in the conventional digital relay, as described in JP-A-2-223329, completely different hardware (separately) is used for main detection and accident detection so as not to cause unnecessary operation due to failure of a single component. Printed circuit board).

  As described above, in the conventional apparatus, the failure of hardware is implemented by software that is constantly monitored, and the volume of the constantly monitored process is large in addition to the protection control calculation that is an application.

  As a matter of course, a confirmation test is necessary to confirm the function of continuous monitoring, and an evaluation test is necessary every time the software configuration is different (each device type).

  In addition, since the hardware is completely separated during main detection and accident detection to prevent unnecessary operation due to a single component failure, it is a matter of course compared with the case of a single CPU system. And the hardware scale was getting bigger.

JP-A-2-223329 Electric Joint Research Vol.50 No.1 2nd Generation Digital Relay

  The first problem in the prior art is that the hardware scale is increased because the hardware is completely separated during main detection and accident detection so as not to cause unnecessary operation due to a single component failure. .

  The second problem is that a hardware defect is detected by constant monitoring processing, so that the volume of constant monitoring processing is increased in addition to the protection control calculation that is an application, and the constant monitoring function. The number of confirmation tests for confirming this is increased.

  Further, when a defect occurs in an area that is not actually used as in memory monitoring, it is a problem that an abnormality is detected even if it does not actually affect.

  The present invention solves the above-mentioned problems, and its purpose is to detect a hardware defect instantaneously with redundant hardware and before issuing an erroneous trip command that causes unnecessary operation. An object of the present invention is to provide a digital protection control device that can be detected by hardware so that the device is locked without relying on constant monitoring processing.

In the present invention, in order to achieve the above object, constantly applying a harmonic superimposed signal to the analog signal processing circuit, an output of said analog input signal processing circuit converts A / D, to the data duplex configuration the CPU type is the result of extracting harmonic superimposed signal for each computation cycle obtained by so as to match in hardware.

  Further, as another configuration of the present invention, the same processing is executed with a time difference between the CPUs configured in a duplex manner, and the results of both are collated for each sampling, thereby confirming the soundness of the collation circuit. It is a thing.

  According to the digital protection control device of the present invention, the configuration in which the hardware (printed circuit board) has been completely separated at the time of main detection and accident detection can be mounted on the same board. While maintaining the reliability, it is possible to achieve a significant reduction in size, cost and power consumption. In addition, by detecting hardware defects with a verification circuit added as a redundant circuit, the functions previously implemented in software can be implemented in hardware, so hardware monitoring can be standardized. There is an advantage that the processing burden on the wear can be reduced.

  The digital protection control apparatus of the present invention will be described below based on the illustrated embodiments.

  FIG. 1 is a block diagram showing a first embodiment of the digital protection control apparatus of the present invention.

Although not shown, the digital protection control apparatus shown in FIG. 1 converts a voltage signal from a power system through an input converter (PT, CT) and takes it in, and takes the acquired signal into an analog filter for preventing a folding error by sampling ( AF) 1a performs signal processing, inputs it to a multiplexer (MPX) 1b, and converts it into a digital quantity by an analog / digital converter (A / D) 1c.

  In order to confirm the soundness of the hardware after the AF described above, the signal 100b from the timing control circuit 1e is applied to the superimposed signal generation 1f, and a harmonic superimposed signal is generated and superimposed on the AF.

  The digital values converted by the A / D 1c are stored in the memory means (MEM1 and MEM2) 1d, respectively. The same data is stored in the memory means at the same timing. A signal for storage is applied from the timing control circuit 1e.

The activation signal 100f is applied to the CPU # 1 and CPU # 2 indicated by 1g from the timing control circuit 1e. CPU # 1 and CPU # 2 each have a CPU bus 1h,
A ROM such as 1i, a work memory (RAM) indicated by 1j, and a device such as an EEPROM which is a non-volatile memory for storing a set value are respectively connected. This 1i
Processing is sequentially executed by a program stored in the ROM in advance, and the calculation result and trip output result are output to the collating circuit 1l every calculation cycle. At this time, the CPUs # 1 and # 2 are configured to execute exactly the same program, including the operation of extracting the superimposed harmonic signal.

  The collation result 100h of the collation circuit 1l is applied to the logical product (AND) means 1n and the timer means 1m, and the logical product (AND) means 1n takes the logical product of the trip output signals 100i and 100g and the collation result 100h. Then, it is applied to the relay driver means 1o and driven to drive the auxiliary relay 1p. That is, it is configured to satisfy the condition for driving the trip contact under the condition that the calculation collation results of the CPUs # 1 and # 2 match. This condition is a condition output including confirmation of normal operation of circuits after the analog filter (AF).

The timer means 1m checks the timer under the condition that the collation result 100h does not match, applies the signal to the relay driver means 1r and drives the signal to drive the auxiliary relay 1q for the device failure contact,
The result of the inconsistency between CPUs # 1 and # 2 is reported to the outside. As a matter of course, momentary inconsistency starts as trip lock, but device failure has a time limit until the failure is confirmed. The system is configured to issue an alarm for a serious failure.

  Next, the operation in the system of FIG. 1 will be described.

  FIG. 2 is a flowchart describing the entire processing procedure for explaining the operation of the system of FIG.

  In FIG. 2A, a processing unit 200 is executed by CPU # 1, a processing unit 201 is executed by CPU # 2, and a part 202 is executed by hardware other than the CPU calculation unit.

  First, data obtained as a result of A / D conversion of 2i is stored in memory means as 2j. After data storage, the processes indicated by 200 and 201 are performed at the same timing by the CPU # 1 and the CPU # 2, respectively. In CPU # 1 and CPU # 2, each process of 2a-2g shall be performed.

  First, the analog input data stored in the memory means is fetched. This analog input signal includes a superimposed harmonic signal.

  Next, a digital filter operation (DF1) for removing low-order harmonic components unnecessary for the protection operation is performed. A protection calculation is executed using the signal after the filter calculation to detect the presence or absence of a system fault. Although not shown in this figure, as a matter of course, the description will be made assuming that the settling value necessary for the protection calculation is taken in before the calculation.

Next, an operation of a digital filter (DF2) that extracts only the harmonic signal superimposed on the analog filter is executed, and an effective value of the extracted harmonic component is obtained. Next, a constant monitoring process related to input / output is executed. After that, in the format as shown in FIG. 2B, the four digital filter calculation results (DF2) and the protection calculation result (RY) from time t-3 to time t executed in DF2 are synthesized. As the output data, the calculation results of the CPUs # 1 and # 2 are output to the verification circuit 2k. The collation circuit collates the computation results for each computation cycle of the CPUs # 1 and # 2, and applies the collation results to the output circuit means for taking a logical product.

  The series of processes described above are operated by CPU # 1 and CPU # 2 so as to be repeated, for example, every 30 electrical degrees. Further, the calculation cycle is not limited to every electrical angle of 30 °, and for example, when data such as an electrical angle of 15 ° is necessary, it corresponds to this.

  As described above, the calculation result of the digital filter DF2 and the RY calculation result are merged into one data, output, and collated, so that the hardware after the analog filter, particularly the deterioration of the characteristics of the analog circuit and the A / D conversion means Since it is possible to detect faults, etc., it is possible to constantly monitor the analog filter from the single system to the A / D conversion means without any blind spots, and confirm the normality of CPU # 1 and CPU # 2. Therefore, the efficiency of abnormality detection can be improved.

  As described above, when the RY output and the output of the digital filter DF2 are merged, for example, when the memory unit becomes abnormal on the data “0” side, if the RY output is originally a result of “0”, in this state, Since there is a possibility that an abnormality cannot be found, there is an advantage in that this blind spot can be eliminated by comparing this RY output with the output of DF2 whose value changes for each calculation. Naturally, since the digital filter DF2 is originally necessary for monitoring the analog circuit, this result can be used effectively.

  FIG. 3 is a diagram for explaining a timing example of the present invention.

  The analog signal is sampled at an electrical angle of 7.5 °, A / D converted, and converted data is written to the memory means MEM1 and MEM2 every 7.5 °.

  In CPU # 1 and CPU # 2, the calculation start signal is applied at the same timing every 30 electrical degrees. In the CPUs # 1 and # 2, the input process T1, the digital filter calculation process T2, the protection control calculation process T3, the analog monitoring calculation process T4, and the output process T5 are executed within 30 °. The verification circuit verifies whether the calculation results are the same each time data is written in the output process T5. If the collation results match, data “H” is set, and if they do not match, data “L” is set. That is, by collating every 30 ° electrical angle that is the computation cycle, the result of each computation can be validated or invalid, and an unnecessary output is generated. There is no danger.

  FIG. 4 is a diagram conceptually showing the processing flow of the analog signal of the present invention.

The input signal and the harmonic signal are added by the adding means 4a, applied to the analog filter, and converted into a digital value by the A / D converter 4d via the MPX 4c. The converted data is converted into DF1 (4e) and DF2 (4f) of CPU # 1, DF1 (4g) and DF2 of CPU # 2.
The calculation is performed by each means of (4h), and the result of each DF2 is compared by the comparison means 4k. Further, the output result of DF2 is detected by the effective value detection means 4l and 4j, and determined by the determination means 4i and 4m, so that abnormality due to deterioration of the analog circuit or the like is also detected.

  FIG. 5 shows an example of the signal flow of the digital filters DF1 and DF2.

In FIG. 5, 5a, 5b, 5c, 5d and 5e are multiplication blocks, 5f and 5g are delay circuit blocks, and 5h, 5i, 5j and 5k are addition circuits. The transfer function of the second-order biquad IIR filter, which is an example of the digital filter shown in FIG.
(IIR: Infinaite Inpulse Response Recursive Filter)

（Ａ１，Ａ２，Ｂ１，Ｂ２，Ｈ_o はフィルタ係数を表す）

(A1, A2, B1, B2 , H o represents the filter coefficient)

The A1, A2, B1, B2, H o in the transfer function of the filter by timely design, those that can achieve the desired filter characteristics.

FIG. 6 shows the output waveform of the analog filter when (1) superimposes the 12th harmonic signal f12 of the fundamental wave as a harmonic signal, and (2) shows a waveform example of the f12 signal extracted by the digital filter DF2. Indicates.

  Since the output value of the f12 signal after passing through the digital filter DF2 fluctuates positively and negatively, the output value is not fixed to “H” or “L”. Therefore, the operation result of one CPU is “H” or “L” “This means that even if the robot falls to the fixed side, it is possible to reliably detect a mismatch in the time of the calculation cycle.

  Considering the case where only the trip output of the result of RY calculation is collated and the calculation result of one CPU is fixed at "L" and fails, the difference between CPU # 1 and CPU # 2 will occur unless a system fault occurs Therefore, there is a concern that the detection time of an inherent hardware failure is delayed.

  For this reason, it is possible to increase the possibility of detecting a hardware failure in the above-described case by collating with the signal obtained by merging the f12 signals after passing through the digital filter DF2 according to the present invention.

  With this configuration, it is possible to detect a hardware failure at a high speed without relying on the CPU system constant monitoring process that has been conventionally performed. Further, according to the present invention, in order to confirm the normal operation of the A / D conversion means, the A / D accuracy is monitored by inputting a known DC voltage using two input channels. Since the processing can be replaced by the monitoring processing of the present invention, downsizing can be achieved, and the monitoring processing by software can be deleted, so that there is an advantage that resources for arithmetic processing can be allocated to the application.

  FIG. 7 shows a modification of the present invention. This modification is basically based on the configuration described with reference to FIG. 1, but differs in the following points.

That is, in FIG. 7, the output of the A / D conversion means 1c is stored in the FIFO (First IN First OUT) buffer shown in the memory means MEM1 and 7a, and data of the same content is stored in the memory means MEM2 with a time difference. It is the point which is doing. As a matter of course, the timing control circuit for providing these time differences is also different. CPU # 1 and CPU # 2 are the same as those shown in FIG. 1 described above, except that the operation is controlled with a time difference.

  Since the result of the collation circuit 1l has a time difference in the output result, the state of coincidence and non-coincidence in the normal state is repeated at regular intervals of operation. By monitoring the result with the timer means 7b, it is possible to detect whether the hardware is normal or abnormal.

  FIG. 8 shows a timing example of a modification of the present invention.

  The difference from the timing example in FIG. 8 is that the timing for writing A / D conversion data in (4) in FIG. 8 is shifted, and the activation timing of CPU # 2 in (7) is shifted with respect to CPU # 1. It is a point.

  As a result, since the collation result in the collation circuit repeats matching and mismatching alternately, by monitoring this periodicity with a timer, it is possible to detect a hardware defect including the collation circuit. In other words, when a hardware failure occurs, the time during which CPU # 1 and CPU # 2 cannot be matched and does not match continues. Therefore, when the timer for checking the periodicity times out, the abnormality is determined.

  In the present invention, if the collation circuit is defective, the periodicity is lost, so that the operation including the soundness of the collation circuit can be confirmed. As the timer, a timer as an integration operation of an analog circuit, a timer for digital counting, a method for rectifying the waveform itself, or the like can be applied.

  Further, in the arithmetic circuit unit 10a of CPU # 1 and CPU # 2 shown in FIG. 1 of the present invention, high-density mounting has become possible due to recent progress in semiconductor process technology. Also in the controller, a method of improving performance at a low clock frequency by mounting a plurality of CPU cores in the same chip has been taken.

In the present invention, on the basis of the above technical trend, it is possible to achieve miniaturization and high reliability by mounting a verification circuit in the same semiconductor chip. Of course, it goes without saying that the CPU # 1 and the CPU # 2 are configured so that the defective portions of each other are not affected.

In FIG. 1 or FIG. 7, CPU # 1 and CPU # 2 execute exactly the same program and the trip signal of the calculation result has been described as a matching condition. However, as another application example,
It is possible to increase the degree of freedom of processing in the CPU by executing different programs on the CPU # 1 and the CPU # 2 and using only the output signal of the digital filter DF2 from which the harmonic superposition signal is extracted as the matching condition. For example, CPU # 2 can be applied as a stopper element as a system.

  In this way, not only the reliability of hardware can be improved, but also the reliability can be improved systematically.

  A harmonic superposition signal is constantly applied to the analog signal processing circuit, A / D conversion is performed on the output of the analog input signal processing circuit, and this data is input to a duplicated CPU, and a harmonic superposition signal is extracted at each calculation cycle. By comparing the result of the operation and the protection operation / sequence processing result to be tripped together with hardware, a hardware failure is detected instantaneously with redundant hardware, and an erroneous trip command that causes unnecessary operation is issued. Before the device is locked, it can be detected by hardware without relying on constant monitoring processing.

It is a block block diagram which shows one Example of the digital protection control apparatus of this invention. It is a figure which shows the processing flow in one Example of the digital protection control apparatus of this invention. It is a figure which shows the example of a timing of this invention. It is a figure which shows the processing flow of the analog signal of this invention. It is a figure which shows an example of the signal flow of the digital filter of this invention. It is a figure which shows the example of a waveform which superimposed the harmonic superimposed signal of this invention, and the waveform which extracted the harmonic superimposed signal with the digital filter. It is a block block diagram which shows the modification of the digital protection control apparatus of this invention. It is a figure which shows the example of a timing in the modification of the digital protection control apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... Analog filter, 1b ... Multiplexer, 1c ... Analog / digital converter, 1d ... Memory means, 1e ... Timing control circuit, 1f ... Superimposition signal generation, 1h ... CPU bus, 1i ... ROM, 1j ... RAM, 1l ... Collation Circuit, 1n ... AND means, 1m ... timer means, 1o, 1r ... relay driver means, 1p, 1q ... auxiliary relay.

Claims (7)

Analog filter means for taking in the analog AC electricity quantity of the power system and synthesizing and taking in the analog AC electricity quantity a harmonic signal that is an integral multiple of the fundamental wave;
Analog / digital conversion means for converting the output signal of the analog filter means into a digital quantity;
A store to Rume memory means the output of the analog / digital conversion means,
ROM means for storing a program, RAM means for storing data, non-volatile memory means, two sets of CPU computing means, which are a set of CPU means,
Collation means for collating the output of the digital filter calculation means that has extracted the harmonic signal and the trip output data of the two sets of CPU calculation means;
And logical product means for obtaining a logical product of the output and the CPU computation means collating means,
A digital protection control device that drives trip contacts connected in series with each output. The digital protection control device according to claim 1, wherein
A digital protection control device comprising a plurality of CPU arithmetic means mounted with the same arithmetic program, wherein the CPU arithmetic means are operated and collated at the same timing. Digital protective control apparatus smell of claim 1 wherein Te,
Before SL digital protective control apparatus output of the digital filter operation means, characterized in that a plurality of operation result of over-samples. The digital protection control device according to claim 1, wherein
A digital protection control apparatus characterized in that the CPU calculation means and the verification means are stored in the same semiconductor chip. Analog filter means for taking in the analog AC electricity quantity of the power system and synthesizing and taking in the analog AC electricity quantity a harmonic signal that is an integral multiple of the fundamental wave;
Analog / digital conversion means for converting the output signal of the analog filter means into a digital quantity; memory means for storing the outputs of the analog / digital conversion means at the same time in a plurality of memory means at different storage times;
Two sets of CPU computing means including a ROM means for storing a program, a RAM means for storing data, a non-volatile memory means, and a CPU means are arranged in parallel, and the two sets of CPU computing means are operated with different driving times. Checking means for checking the output of the CPU calculation means;
A timer means is provided at the subsequent stage of the collating means, and two sets of AND means for taking an AND with the output of the timer means are provided, and trip contacts connected in series with each output are driven. Digital protection control device. The digital protection control device according to claim 5 , wherein
A digital protection characterized in that a separate arithmetic program is installed in each of the CPU arithmetic means provided in plural, and collation is performed only with the respective digital filter output data for extracting the harmonic superimposed signal of the CPU arithmetic means. Control device. Analog filter means for taking in the analog AC electricity quantity of the power system and synthesizing and taking in the analog AC electricity quantity a harmonic signal that is an integral multiple of the fundamental wave;
Analog / digital conversion means for converting the output signal of the analog filter means into a digital quantity;
A plurality of memory means for simultaneously storing the outputs of the analog / digital conversion means;
ROM means for storing a program, RAM means for storing data, non-volatile memory means, CPU arithmetic means comprising a set of CPU means in two sets in parallel,
The two sets of CPU calculation means are mounted with different calculation programs, respectively, and collation means for collating only the respective digital filter output data for extracting the harmonic superimposed signal of the CPU calculation means,
Two sets of logical product means for taking the logical product of the output of the verification means and the CPU arithmetic means,
A digital protection control device that drives trip contacts connected in series with each output.

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