JPH01222495A - Chip carrier board packaging structure - Google Patents

Chip carrier board packaging structure

Info

Publication number
JPH01222495A
JPH01222495A JP4799188A JP4799188A JPH01222495A JP H01222495 A JPH01222495 A JP H01222495A JP 4799188 A JP4799188 A JP 4799188A JP 4799188 A JP4799188 A JP 4799188A JP H01222495 A JPH01222495 A JP H01222495A
Authority
JP
Japan
Prior art keywords
chip carrier
board
carrier board
pattern
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4799188A
Other languages
Japanese (ja)
Inventor
Shigeo Sasaki
茂雄 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP4799188A priority Critical patent/JPH01222495A/en
Publication of JPH01222495A publication Critical patent/JPH01222495A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To obtain a packaging structure excellent in reliability through a simple operation by a method wherein a chip carrier board is placed in an opening formed in a chip carrier packaging board and terminals and a pattern are soldered nearly on the same plane. CONSTITUTION:A chip carrier board 2 is placed in an opening formed in a chip carrier packaging board 1, and terminals 6 are soldered to a pattern 7 on a plane. Moreover, if a corner of the chip carrier board 2 is processed like a beveled corner 5, the chip carrier board 2 can be placed in the opening formed in the chip carrier packaging board 1 without a directional positioning error. And, the connection of the chip carrier board 2 with the chip carrier packaging board 1 is made by bridging the terminals 6 and the pattern 7 with solder, and if the chip carrier board 2 is formed of the same material as the chip carrier packaging board 1, the terminal 6 and the pattern 7 are made to be on the same plane. By these processes, the soldering operation is facilitated and the moisture resistant property can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、チップキャリア基板を半田付けする際の実装
構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mounting structure for soldering a chip carrier board.

（従来の技術〕 従来のチップキャリア基板の実装構造は、第２図である
。第２図に於いて、２２はチップキャリア基板、２１は
被チップキャリア実装基板、２６は端子、７はパターン
であり、被チップキャリア基板上にチップキャリア基板
を載せ実装することが知られ【いた。(Prior art) The mounting structure of a conventional chip carrier board is shown in Fig. 2. In Fig. 2, 22 is a chip carrier board, 21 is a chip carrier mounting board, 26 is a terminal, and 7 is a pattern. It has been known to mount a chip carrier substrate on a chip carrier substrate.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、前述の従来技術では、チップキャリアの端子と
被チップキャリア基板のパターンを合わせる作業が容易
でないこと、又チップキャリア基板と被チップキャリア
基板との間に、半田付は時に使用する７ラツクス等が流
入してしまい、耐湿特性の劣化をまねいていた。そこで
本発明はこの様な問題点を解決するもので、その目的と
するところは、簡°易作業で信頼性のあるチップキャリ
ア実装構造を提供するところくある。However, with the above-mentioned conventional technology, it is not easy to match the terminals of the chip carrier with the pattern of the chip carrier substrate, and the soldering process, such as the 7 lacs, which is sometimes used, is difficult to do between the chip carrier substrate and the chip carrier substrate. This caused the moisture resistance to deteriorate. The present invention is intended to solve these problems, and its purpose is to provide a reliable chip carrier mounting structure that is easy to work with.

〔課題点を解決するための手段〕[Means for solving problems]

本発明のチップキャリア基板実装構造は、チップキャリ
ア基板を被チップキャリア実装基板にあけた六に落し込
み、端子とパターンを平面で半田付けすることを特徴と
する特 〔実施例〕 以下、本発明について実施例に基づき詳細に説明する。The chip carrier board mounting structure of the present invention is characterized in that the chip carrier board is dropped into a hole in the chip carrier mounting board, and the terminals and patterns are soldered on a flat surface. will be described in detail based on examples.

第１図（１）は、チップキャリア基板２が被チップキャ
リア基板ＩＫ落し込まれている構造を示す、尚、チップ
キャリア基板２を被チップキャリア基板１に落し込む際
、チップキャリア基板２０片隅な面トリ５の様な形状に
処理しておけば、チップキャリア基板２の方向な誤りた
向きに落し込むことは絶対に起こらない。FIG. 1 (1) shows a structure in which the chip carrier board 2 is dropped into the target chip carrier board IK. When dropping the chip carrier board 2 into the target chip carrier board 1, one corner of the chip carrier board 20 is If it is processed into a shape like the surface trimming 5, it will never occur that the chip is dropped in the wrong direction, such as the direction of the chip carrier substrate 2.

又、実際のチップキャリア基板２と被チップキャリア基
板との接続は、第１図（ｂ）の様に、端子６とパターン
７の上に半田を載せてやる。つまり半田で端子６とパタ
ーン７とをブリッジさせることにより行う、尚この際チ
ップキャリア基板２と被チップキャリア基板の材厚を同
一のもＯＫしておけば、端子６とパターン７は同一平面
上となり作業性が非常に向上する。そして第１図（Ａ）
の８は、半田により端子６とパターン７とが接続された
様子を示すものである。Further, for actual connection between the chip carrier substrate 2 and the chip carrier substrate, solder is placed on the terminals 6 and the patterns 7, as shown in FIG. 1(b). In other words, this is done by bridging the terminals 6 and the pattern 7 with solder.At this time, if the material thickness of the chip carrier substrate 2 and the chip carrier substrate are the same, the terminals 6 and the pattern 7 are on the same plane. This greatly improves work efficiency. And Figure 1 (A)
8 shows how the terminal 6 and the pattern 7 are connected by solder.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、被チップキャリア基板
にあけた六に、チップ中ヤリア基板を落し込み半田付け
をするという開学な構造により、チップキャリア基板の
半田付は作業の容易に出来かつ、耐湿特性の向上が可能
となる。As explained above, the present invention has an innovative structure in which the carrier board inside the chip is dropped into the hole drilled in the chip carrier board and soldered, making it possible to easily solder the chip carrier board. Moreover, it is possible to improve moisture resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明にかかるチップキャリア実装構造図、
第２図は、従来のチップキャリア実装構造図である。 １・・・・・・・・・被チップキャリア実装基板２・・
・・・・・・・チップキャリア基板５・・・・・・・・
・配線パターン ４・・・・・・・・・モールド剤 ５・・・・・・・・・面トリ ６・・・・・・・・・端　子。 ７・・・・・・・・・パターン ８・・・・・・・・・半田付は部 ｕ　１　図FIG. 1 is a diagram of a chip carrier mounting structure according to the present invention;
FIG. 2 is a diagram of a conventional chip carrier mounting structure. 1... Chip carrier mounting board 2...
......Chip carrier board 5...
・Wiring pattern 4...Molding agent 5...Face trim 6...Terminal. 7・・・・・・・・・Pattern 8・・・・・・Soldering is part u1 Fig.

Claims (1)

【特許請求の範囲】[Claims] チップキャリア基板を被チップキャリア実装基板にあけ
た穴に落し込み、端子とパターンをほぼ平面で半田付け
することを特徴とするチップキャリア基板実装構造。A chip carrier board mounting structure characterized by dropping a chip carrier board into a hole drilled in a chip carrier mounting board, and soldering terminals and patterns on a substantially flat surface.
JP4799188A 1988-03-01 1988-03-01 Chip carrier board packaging structure Pending JPH01222495A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4799188A JPH01222495A (en) 1988-03-01 1988-03-01 Chip carrier board packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4799188A JPH01222495A (en) 1988-03-01 1988-03-01 Chip carrier board packaging structure

Publications (1)

Publication Number Publication Date
JPH01222495A true JPH01222495A (en) 1989-09-05

Family

ID=12790787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4799188A Pending JPH01222495A (en) 1988-03-01 1988-03-01 Chip carrier board packaging structure

Country Status (1)

Country Link
JP (1) JPH01222495A (en)

Similar Documents

Publication Publication Date Title
US4775917A (en) Thermal compensated circuit board interconnect apparatus and method of forming the same
IE39666B1 (en) Improvements in or relating to circuit boards
JPH01222495A (en) Chip carrier board packaging structure
JPH05226803A (en) Mounting circuit board
JPS6334936A (en) Mounting structure of tape carrier
JP2000031358A (en) Power semiconductor module
JPS617692A (en) Method of securing conductor pin and printed circuit board secured with conductor pin
JPH0527810Y2 (en)
JPS62142338A (en) Package for semiconductor device
JPS6314474Y2 (en)
JPH02125646A (en) Chip carrier substrate mounting structure
JPS6038291Y2 (en) Printed wiring board for chip mounting
JPH01208851A (en) Mounting structure for electronic part
KR960028716A (en) Fanol double-sided board and its double-sided method
JPH0311693A (en) Circuit substrate for semiconductor device
JP2543867Y2 (en) SIP type electronic components
JPS63153847A (en) Earth connection of microwave integrated circuit substrate
JPH0528917B2 (en)
KR100609760B1 (en) Multi-Layer Ceramic Semiconductor Device and Method thereof
JPS6369694A (en) Screen
JPS61225825A (en) Ic mounting structure
JPS60213083A (en) Method of mounting semiconductor device
JPS61232693A (en) Hybrid integrated circuit device
JPS56116646A (en) Semiconductor device
JPH0483355A (en) Packaging method of semiconductor element