JPH01220294A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To obtain a sense amplifier circuit without impairing speediness by providing a potential detection circuit consisting of an inverter, and a data line stabilizing transistor circuit where an NMOS transistor whose gate terminal is connected to the output of a current detection circuit is connected between the output of the potential detection circuit and a data line. CONSTITUTION:The title circuit is provided with the potential detection circuit consisting of the inverter 7 to input the data line 1 to which a bit line 4 that is the output line of a memory cell 3 is connected via a selection circuit, the current detection circuit where a load device for detecting potential is connected in series to the NMOS transistor 8 for detecting a current whose gate terminal is connected to the output of the potential detection circuit and whose source terminal to the data line 1, and the data stabilizing transistor circuit connecting the NMOS transistor 9 whose gate terminal is connected to the output of the current detection circuit between the output of the potential detection circuit and the data line 1. By such constitution, since discharge is performed via the memory cell and the data line stabilizing transistor when the overcharge state of the data line is generated, the readout of data can be performed without impairing the speediness.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a sense amplifier circuit in a semiconductor memory device.

<Prior Art> Generally, in a semiconductor device in which each memory cell is composed of one MOS transistor, data is written into the memory cell by changing the threshold voltage of the MOS transistor that is the memory cell. . Then, the data written in the memory cell is converted into a voltage by the sense amplifier circuit based on the current capacity of the memory cell and the current capacity of the load MO9 transistor, and is detected.

As such a sense amplifier circuit, there is a conventional one as shown in FIG. In this sense amplifier circuit, a bit line 34, which is an output line of a memory cell 33, is connected to a data line 31 via a column selector 32.

Now, when the potentials of column decoder 35 and word line 36 reach Vdd, memory cell 33 is selected. When the threshold voltage of the memory cell 33 is high, almost no current flows through the memory cell 33, so when the data line 31 (bit line 34) is in the "Low" level state, the first inverter 37 and the second inverter 38 detects the potential of the data line 31 and sets its output to "High" level.

Then, charging is performed via the NMOS transistors 41, 42, 43, and when the data line 31 (bit line 34) reaches the potential Va, the NMOS transistors 42, 43
is turned off. Then, charging continues through the NMO9 transistor 41, and the data line 31 (bit line 3
When the potential of 4) reaches vb, the NMOS transistor 41
is also turned off, and as a result, the potential of the data line 31 (V da
ta) becomes “High” level at vb and stabilizes, and V
out outputs a “High” level. Here, the first
The inversion level of the inverter 37 is set slightly higher than the inversion level of the second inverter 38.

On the other hand, when the memory cell 33 has a low threshold voltage, if the data line 31 (bit line 34) is at a "High" level, it is discharged by the memory cell 33, and the data line 31 (bit line 34) becomes "Low". If level, inverter 37
．． 38 through NMOS transistors 41, 42, and 43. As a result, the potential of data line 31 (bit line 34) is changed to inverter 37, 38 and PM
The voltage is stabilized at the potential Vc determined by the O9 load transistors 44, 45, and 46. At this time, the current of the memory cell 33 is P
The flow is divided by the capacity ratio of the MOS load transistors 44, 45, and 46. Here, the ability of the PMOS load transistor 46, which is a current detection load transistor, is as follows:
At this time, Vout is set to be at the "Low" level.

Taking all the above into consideration, the characteristics of this sense amplifier circuit are as shown in FIG. That is, when the memory cell 33 has a high threshold voltage, a current flows through the data line 31 as shown in current characteristics (A), and the potential of the data line 31 V d
ata changes from Va to vb and becomes stable. Then, the output voltage Vout becomes Vdd and stabilizes according to the voltage characteristic (a). On the other hand, when the memory cell has a low threshold voltage, the potential of the data line 31 is stabilized at the potential Vc at the intersection of the above current characteristic (A) and the memory cell current characteristic (T) at a low threshold voltage.

<Problems to be Solved by the Invention> By the way, in the conventional sense amplifier circuit described above, the data line 31
In order to obtain a certain value for the noise margin (ΔVh=Vb-Va) when the bit line 34 is at the "High" level, the inverter 37 is used, which has a slightly higher inversion level than the inverter 38. However, there are problems in that the current consumption increases, the occupied area increases, and the dependence of Δvh on manufacturing variations increases. Also,
When the data line 31 (bit line 34) is overcharged, only the memory cells are discharged, resulting in a problem that high speed performance is impaired.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sense amplifier circuit that consumes less current, occupies a smaller area, is less dependent on manufacturing variations in Δvh, and does not impair high speed performance.

Means for Solving the Problems In order to achieve the above object, a sense amplifier circuit of the present invention includes an inverter whose input is a data line connected to a bit line, which is an output line of a memory cell, through a selection circuit. a current detection circuit in which a current detection load device is connected in series to a current detection NMo5 transistor whose gate end is connected to the output of the potential detection circuit and whose source end is connected to the data line; The present invention is characterized by comprising a data line stabilizing transistor circuit in which an NMO9) transistor whose end is connected to the output of the current detection circuit is connected between the output of the potential detection circuit and the data line.

<Function> With the above configuration, when a memory cell is selected, when the potential of the data line is at the "Low" level, the potential detection circuit
The data line is charged via the current detection NMO8 transistor which outputs a "High" level and receives this "High" level at the gate end.On the other hand, the memory cell is at a low threshold voltage and the potential of the data line is When it is at the “High” level, it is discharged by the memory cell.Also, when the data line is in an overcharged state, it is discharged through the memory cell and data line stabilizing transistor circuit.In this way, only one inverter is required. This reduces current consumption, occupies a small area, and reduces the dependence of Δvh on manufacturing variations.In addition, when the data line is overcharged, the Since it is discharged, high speed performance is not impaired.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 is a circuit diagram of this embodiment, in which a bit line 4, which is an output line of a memory cell 3, is connected to a data line 1 via a column selector 2.

Now, when the potentials of column decoder 5 and word line 6 reach Vdd, memory cell 3 is selected.

When memory cell 3 has a high threshold voltage, almost no current flows through memory cell 3, so data line 1 (bit line 4
) is at the "Low" level, the inverter 7 detects the potential of the data line 1 and sets the output to the "High" level. Then, charging continues via the NMOS transistor 8.9, and when the data line 1 (bit line 4) reaches the potential Va, the NMOS transistor 8.9 is turned off. At this time, V out<V dd level,
Charging continues through the stabilizing transistors to, 11, and when the potential of the data line 1 (bit line 4) reaches vb, charging from the stabilizing transistor 10.2 ends, and as a result, the potential of the data line l (V data) is “High” in vb.
h” level and stable, and Vout is at the Vdd level.

On the other hand, when the memory cell 3 has a low threshold voltage, the data line l
If the (bit line 4) is at the "High" level, it is discharged by the memory cell 3, and the data line l (bit line 4) is "High" level.
If it is “Low” level, it is charged by the inverter 7 via the NMOS transistor 8.9. As a result, the potential of the data line ! (bit line 4) is
It stabilizes at the potential Vc determined by MO8 load transistors 12 and 13.

At this time, the current in the memory cell 3 flows while being divided by the capacity ratio of the PMO9 load transistors 12 and 13. Here, the ability of the PMO9 load transistor 13, which is a current detection load transistor, is such that V out is “Low” at this time.
``It is set to be the level.

Taking all the above into account, the characteristics of this sense amplifier circuit are as shown in FIG. That is, when the memory cell 3 has a high threshold voltage, a current flows through the data line 1 as shown in the current characteristic (A), and the potential of the data line 1 V data
becomes stable from Va to vb. And the output voltage V
out becomes Vdd and stabilizes according to the voltage characteristic (B). On the other hand, when the memory cell has a low threshold voltage, the data line l
is the potential Vc at the intersection of the above current characteristic (A) and the memory cell current characteristic (C) at low threshold voltage.
becomes stable.

In this way, the number of inverters can be reduced by one compared to the conventional example, so the current consumption is reduced and the area occupied can be reduced. Further, in the conventional example, Δvh depends on the characteristics of the inverters 37 and 38 and the NMO9 transistors 41, 42, and 43, but in this embodiment, the inverter 7 and the
Since it only depends on the S transistor 8.9, Δv
The dependence of h on manufacturing variations can be reduced. Furthermore, when the data line l (bit line 4) is in an overcharged state, the memory cell 3 and the stabilizing transistor 10°11
Since the data is discharged through the memory, data can be read without sacrificing high speed.

<Effects of the Invention> As is clear from the above, the sense amplifier circuit of the present invention requires only one potential detection circuit consisting of an inverter.
Current consumption and occupied area can be reduced, and Δvh
dependence on manufacturing variations can be reduced. Further, when the data line is in an overcharged state, it is discharged through the memory cell and the data line stabilizing transistor circuit, so data can be read without impairing high speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the sense amplifier circuit of the present invention, FIG. 2 is a diagram showing the characteristics of the above embodiment, FIG. 3 is a circuit diagram of a conventional sense amplifier circuit, and FIG. 4 is a circuit diagram of the conventional sense amplifier circuit described above. It is a figure which shows the characteristic of an example. l...Data line, 2...Column selector, 3...
Memory cell, 4...bit line, 7...inverter,
8.9.11...NMOS transistor! 0.1
2.13...PMOS transistor. Patent applicant: Sharp Corporation Agent
Patent attorney Maeda Ao and 2 others)

Claims (1)

[Claims] (1) A potential detection circuit consisting of an inverter whose input is a data line connected to a bit line, which is an output line of a memory cell, via a selection circuit; a gate end connected to the output of the potential detection circuit; and a source end connected to the potential detection circuit. A current detection circuit in which a current detection load device is connected in series to a current detection NMOS transistor connected to the data line, and an NMOS transistor whose gate end is connected to the output of the current detection circuit.
A sense amplifier circuit comprising: a data line stabilizing transistor circuit having an S transistor connected between the output of the potential detection circuit and the data line.