JPH02146189A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the peak value of a discharged current flowing through a GND power source at the time of reading and to suppress the rocking of the GND circuit by providing an element having a potential drop in an output transistor (TR) circuit. CONSTITUTION:An element E having the potential drop commonly connected with a drain terminal and a gate terminal in an output circuit D is provided. First, when '1' information is read, and a sense amplifier output signal SAOUT becomes an H according to memory cell information, the outputs of inverter circuits A1 and A2 become an L, a P type MOS (TR) T1 is turned on, an N type MOS T2 is turned off, and load capacity C is charged up to the voltage level, which is lower than a VCC voltage by a threshold voltage, through the element E and the MOS T1. In the same way as above, when '0' information is read, and the signal SAOUT becomes the L, the circuits A1 and A2 become the H, the MOS T1 is turned off, the T2 is turned on, and the charge of the capacity C is discharged through the MOS T2 to the GND power source. That is, a data output signal DOUT reads the '0' information.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to an output transistor circuit.

[Conventional technology]

Next, the conventional semiconductor integrated circuit is an output transistor circuit shown in FIG. 2, which includes inverter circuits A 1 and A 2 to which the sense amplifier output signal 5AOUT is input, and a P-type MOS transistor T 1 connected to the inverter circuits AI and A 2. and an N-type MOS transistor T2, and a load capacitor C connected to a midpoint N of both MOS transistors, and is configured to send out a data output signal DOIJT from this midpoint N. ing.

First, the operation of reading out "1" information will be explained.

When the sense amplifier output signal 5AOUT goes to the "H" level according to the memory cell information, the output signals of the inverter circuits AI and A2 go to the "L" level, so the P-type MOS transistor T is turned on and the N-type MO3) transistor T2 is turned on. is OFF and the load capacitance C is the P-type MOS transistor T1.
is charged to the Vcc voltage via the Vcc voltage. That is, the data output signal DOUT reads out 1" information. On the other hand, the operation of reading out "0" information is also performed using the sense amplifier output signal 5A.
When OUT goes to "L" level according to the memory cell information, the output signals of inverter circuits A1 and A2 become "H"
level, so the P-type MOS transistor T1 is OF
The F, N-type MOS transistor T2 is turned on, and the charge of the load capacitance C charged to the cc voltage is discharged to the GND power source via the N-type MOS transistor T2.

[Problem to be solved by the invention]

Generally, semiconductor integrated circuits have a load capacitance C of several tens of P on the output side.
It has a large capacity of F, and especially when reading “0”, the GN
The peak value of the discharge current flowing into the D power supply increases, and as a result, the fluctuation of the GND power supply increases, so that fluctuations in the GND power supply may cause various problems such as deterioration of the actual value of the input "H" level voltage at the first input stage. A problem occurs. Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor integrated circuit in which the GND power supply is less likely to fluctuate.

[Means to solve the problem]

In the semiconductor integrated circuit of the present invention, the Vc of the output transistor circuit
It is constructed by connecting the c power supply terminal to the cc power supply via an element having a potential drop in which the drain terminal and gate terminal of a P-type or N-type MOS transistor are commonly connected.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, this embodiment includes inverter circuits Al and A2 that input sense amplifier output signals, and P connected to these.
An output circuit having a type MO8) transistor T1 and an N type MOS transistor T2, a load capacitance C connected to the midpoint N of this MOS transistor, and an element with a potential drop connected to the output circuit. have. In addition,
Element E with a potential drop is a P-type MOS transistor T
3 or an N-type MOS transistor T4. In one embodiment of the present invention, the output circuit is composed of a P-type MOS transistor T1 and an N-type MOS transistor F2. . The point is that an element E having a potential drop is inserted between the supply terminal and the cc power supply. In addition, the element E having this potential drop has P as shown in Fig. 1(b) and (C).
It is constructed by connecting the gate terminal and drain terminal of a type MOS transistor T3, or by connecting the gate terminal and drain terminal of an N type MOS transistor T4. That is,
With these two configurations, the Vcc power supply terminal of the output circuit has a voltage lower than the Vcc voltage by the threshold voltage of the MOS transistor.

Next, the read operation of this embodiment will be explained. First, when reading "1" information, when the sense amplifier output signal 5AOUT goes to the IHn level according to the memory cell information, the output signals of the inverter circuits Al and A2 go to the "L" level.
Therefore, the P-type MOS transistor T1 is ON, and the N-type MOS transistor T1 is ON.
) The transistor T2 is turned off, and the load capacitor C is charged to a voltage level lower than the Vcc voltage by the threshold voltage of the MOS transistor via the element having a potential drop and the P-type MOS transistor Tl. That is, the data output signal DOUT reads out "1" information.

On the other hand, in the operation of reading "OIT information," the sense amplifier output signal 5AOUT is "L" according to the memory cell information.
” level, the output signal of the inverter circuits A and A2 becomes “H” level, so the P-type MOS transistor T1 is turned off and the N-type MOS transistor T2 is turned on, and the load capacitance C is increased by the threshold value from the cc voltage. The charges charged to a lower voltage are discharged to the GND power supply via the N-type MOS transistor T2.

That is, the data output signal DOUT reads out "0" information, so it is clear that the embodiment of the present invention also performs the read operation in the same manner as the conventional example.

〔Effect of the invention〕

As explained above, in the present invention, by providing an element having a potential drop in the output transistor circuit, ■cc
Since the voltage level of the power supply terminal is lower than the Vcc voltage by the threshold voltage, G
It is possible to reduce the peak value of the discharge current flowing into the ND power supply, which has the effect of suppressing fluctuations in the GND power supply.

[Brief explanation of the drawing]

Fig. 1(a) is a plot diagram showing an embodiment of the present invention, Fig. 1(b) is a circuit diagram showing an element having a potential drop composed of P-type MoS transistors, and Fig. 1(c) is a plot diagram showing an embodiment of the present invention. Similarly, a circuit diagram showing an element having a potential drop made up of N-type MOS transistors, and FIG. 2 is a circuit diagram showing a conventional output transistor circuit. T1.T, . . . P-type MOS transistors, T2゜T4
...N-type MOS transistor, A! ~A2...Inverter circuit, 5AOUT...Sense amplifier output signal,
DOUT...Data output signal, C...Load capacitance, D
...Output circuit, E...Element with potential drop.

Claims (1)

[Claims] 1. A semiconductor integrated circuit characterized in that a Vcc power supply terminal of an output transistor circuit is connected to a Vcc power supply via an element having a potential drop in which the drain and gate of a P-type or N-type MOS transistor are connected to the Vcc power supply.