JP2690554B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a digit line termination circuit.

[Conventional technology]

Conventionally, a semiconductor memory device of this type has a static type memory cell 1 having first and second input / output terminals and a pair of first and second digit lines as shown in FIG. 2 as an example. DL _1, and DL _2, when the memory cell 1 is in a selected state word for connecting the first and second input and output terminals of the memory cell 1 first and second corresponding to the digit line DL _1, DL ₂ Line W
L _{1 is connected} between the power supply line (power supply voltage V _CC ) and the first and second digit lines DL ₁ and DL ₂ , respectively, and the first and second lines are connected before the memory cell 1 enters the selected state. Digit line terminating circuit 2 _A having first and second MOS transistors M ₁ and M ₂ for holding the digit lines DL ₁ and DL _{2 of the same} at the same potential;
And a digit sense amplifier 3 for amplifying the potential difference between the second digit lines DL ₁ and DL ₂ and transmitting it to the next stage, and MOS transistors M ₈ and M ₉ .

Next, the read operation of this circuit will be described.

First, before the read operation is started, that is, before the memory cell is in the selected state, the digit lines DL ₁ and DL ₂ are lower than the power supply voltage V _{CC by} the threshold voltage V _{TN of the} MOS transistors M ₁ and M ₂ , etc. Hold on to voltage.

When the word line WL ₁ and the digit line selection signal DS ₁ become high level and the memory cell 1 and the digit sense amplifier 3 are selected, the data held in the memory cell 1 causes a difference potential between the digit lines DL ₁ and DL _2. .

As described above, since the digit sense amplifier 3 normally composed of the MOS transistors M _{5 to} M ₇ is required to operate at high speed, the initial voltage of the digit lines DL ₁ and DL ₂ which is the input of the digit sense amplifier 3 is required. Is set to the optimum value.

In this example, the initial voltage is set to (V _CC -V _TN ), whereby the potential difference between the digit lines DL ₁ and DL ₂ is amplified at the highest speed and transmitted to the next stage.

[Problems to be solved by the invention]

The conventional semiconductor memory device described above has a configuration in which the digit lines DL ₁ and DL ₂ are held at the same potential by the MOS transistors M ₁ and M ₂ of the digit line termination circuit 2 _A before the memory cell 1 is brought into the selected state. Therefore, for example, if the power supply voltage V _CC temporarily rises by V _A , the potentials of the digit lines DL ₁ and DL ₂ are raised to (V _CC + V _A −V _TH ), and even if it returns to V _CC thereafter. , And the MOS transistors M ₁ and M ₂ are turned off, there is no path for discharging the charges of the digit lines DL ₁ and DL ₂ , and (V
_CC + V _A -V _TH ) remains held, and there is a drawback that the optimum operating point of the digit sense amplifier 3 shifts and the operating speed decreases.

In recent years, the decrease in operating speed increases as the demand for low-voltage operation (for example, 3V) of semiconductor memory devices increases, and the operation guaranteed voltage range expands.

An object of the present invention is to provide a semiconductor memory circuit capable of increasing the operation speed when the power supply voltage changes.

[Means for solving the problem]

The semiconductor memory device of the present invention includes a memory cell having first and second input / output terminals, a pair of first and second digit lines, and a first of the memory cells when the memory cell is in a selected state. And a second input / output terminal corresponding to the first and second digit lines, and a memory cell connected between a power supply line and the first and second digit lines, respectively. To hold the first and second digit lines at the same potential before the first and second digit lines are selected.
A MOS transistor and the first and second digit lines, which are connected between the power supply line and the first and second digit lines, respectively.
Power supply line applied to the MOS transistor of
Third and fourth MOS transistors which are turned on when the voltage of the first and second digit lines has a height relation opposite to the voltage when the first and second MOS transistors are turned on A digit line termination circuit including a transistor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing one embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory device in that
The digit line terminating circuit 2 has a conventional first and second
In addition to the MOS transistors M ₁ and M ₂ , connected between the power supply line (normal power supply voltage V _CC ) and the digit lines DL ₁ and DL ₂ , respectively, and applied to the MOS transistors M ₁ and M _2. When the voltage of the power supply line and the digit lines DL ₁ and DL ₂ has a height relation opposite to that of the voltage when the MOS transistors M ₁ and M ₂ are turned on, the third state is turned on. The fourth
The point is that MOS transistors M ₃ and M ₄ are provided.

 Next, the operation of this embodiment will be described.

During normal operation in which the power supply voltage V _CC does not fluctuate, the MOS transistors M ₃ and M ₄ are in the off state, and therefore the operation is similar to the conventional one.

When the power supply voltage rises from V _CC by V _A , the digit line D
The potentials of L ₁ and DL ₂ are raised to (V _CC + V _A −V _TH1 ) when the threshold voltage of the MOS transistors M ₁ and M ₂ is V _TH1 .

Then, when the power supply voltage returns to V _CC , the MOS transistor M ₁
~ The relationship of the voltage applied to M ₄ is reversed, so the MOS
The transistors M ₁ and M ₂ are off, the MOS transistors M ₃ and M ₄ are on, and the threshold voltage of the MOS transistors M ₃ and M ₄ is V _TH2.
Then, the potentials of the digit lines DL ₁ and DL ₂ are (V _CC + V _TH2 ).
Down to

Therefore, when the power supply voltage fluctuates, the deviation from the optimum operating point of the digit sense amplifier 3 can be reduced, and the operating speed can be made faster than in the conventional example.

〔The invention's effect〕

As described above, according to the present invention, in addition to the conventional first and second MOS transistors in the digit line termination circuit, the third and third MOS transistors having the opposite on / off relationship with the first and second MOS transistors are provided. By connecting the fourth MOS transistor in parallel with the first and second MOS transistors, it is possible to reduce the deviation from the optimum operating point of the digit sense amplifier when the power supply voltage changes. Therefore, the operation speed can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional semiconductor memory device. 1 ... Memory cell, 2,2 _A ... Digit line termination circuit, 3
...... Digit sense amplifier, DL ₁ , DL ₂ ...... Digit line, M _{1 to} M ₉ ...... MOS transistor, WL ₁ ...... Word line.

Claims (1)

(57) [Claims] 1. A memory cell having first and second input / output terminals, a pair of first and second digit lines, and first and second memory cells when the memory cell is in a selected state.
A word line connecting the input and output ends of the first digit line and the second digit line, a power supply line, and the first and second digit lines.
First and second MOS transistors which are respectively connected between the first and second digit lines and are held at the same potential before the memory cell is brought into a selected state, and the power supply line. The voltages of the power supply line and the first and second digit lines connected to the first and second digit lines and applied to the first and second MOS transistors are And a digit line termination circuit including third and fourth MOS transistors that are turned on when the voltage has a relationship opposite to that of the voltage when the second MOS transistor is turned on. And semiconductor memory device.