JPH0738278B2 - Sense amplifier circuit - Google Patents

Description

The present invention relates to a sense amplifier circuit in a semiconductor memory device.

<Prior Art> Generally, in a semiconductor device in which each memory cell is composed of one MOS transistor, data is written in the memory cell by changing the threshold voltage of the MOS transistor which is a memory cell. . Then, the data written in the memory cell is voltage-converted by the sense amplifier circuit according to the current capacity of the memory cell and the current capacity of the load MOS transistor to be detected.

As such a sense amplifier circuit, there is a conventional one as shown in FIG. This sense amplifier circuit is
A bit line 34, which is an output line of the memory cell 33, is connected to 31 through a column selector 32.

Now, the potentials of the column decoder 35 and the word line 36 are
When it reaches Vdd, the memory cell 33 is selected. When the memory cell 33 has a high threshold voltage, almost no current flows through the memory cell 33, so that the data line 31 (bit line 34) is "Low".
In the level state, the first inverter 37 and the second inverter 38 detect the potential of the data line 31 and bring its output to the "High" level. Then, the NMOS transistor 4
Charging is performed via 1,42,43 and data line 31 (bit line 3
When 4) reaches the potential Va, the NMOS transistors 42 and 43 are turned off. Then, charging is continued through the NMOS transistor 41, and when the potential of the data line 31 (bit line 34) reaches Vb, the NMOS transistor 41 is also turned off, and as a result, the potential (Vdata) of the data line 31 is Vb. It becomes stable at "High" level, and Vout outputs "High" level. Here, the inversion level of the first inverter 37 is set slightly higher than the inversion level of the second inverter 38.

On the other hand, when the memory cell 33 has a low threshold voltage, the data line 31
If (bit line 34) is at "High" level, memory cell 33
Is discharged by the data line 31 (bit line 34) is "Low"
If it is at a level, it is charged by the inverters 37, 38 via the NMOS transistors 41, 42, 43. As a result, the potential of the data line 31 (bit line 34) is changed by the inverters 37, 38 and P.
It stabilizes at the potential Vc determined by the MOS load transistors 44, 45, 46. At this time, the current of the memory cell 33 flows by being divided according to the capacity ratio of the PMOS load transistors 44, 45, 46. Here, the capacity of the PMOS load transistor 46, which is a current detection load transistor, is set so that Vout is at a "Low" level at this time.

Summarizing the above, the characteristics of this sense amplifier circuit are as shown in FIG. That is, when the memory cell 33 has a high threshold voltage, a current flows through the data line 31 as shown by the current characteristic (A), and the potential Vdata of the data line 31 becomes stable from Va to Vb. Then, the output voltage Vout becomes Vdd according to the voltage characteristic (a) and becomes stable. On the other hand, when the memory cell has a low threshold voltage, the potential of the data line 31 is stabilized at the potential Vc at the intersection of the current characteristic (a) and the memory cell current characteristic (c) at the low threshold voltage.

<Problems to be Solved by the Invention> By the way, the conventional sense amplifier circuit described above has a data line 31
To obtain the noise margin (ΔVh = Vb−Va) when the (bit line 34) is at “High” level, a certain value
Although the inverter 37 having an inversion level slightly higher than that of 38 is used, this causes a problem that current consumption increases, an occupied area increases, and a dependency of ΔVh on manufacturing variation increases. In addition, when the data line 31 (bit line 34) is overcharged, only the memory cell is discharged, which impairs high speed.

Therefore, an object of the present invention is to provide a sense amplifier circuit that consumes less current, occupies a smaller area, and has less dependence on the manufacturing variation of ΔVh, and that does not impair high speed.

<Means for Solving the Problems> In order to achieve the above object, the sense amplifier circuit of the present invention is composed of an inverter having a data line connected to a bit line, which is an output line of a memory cell, through a selection circuit as an input. A potential detection circuit, a current detection circuit in which a gate end is connected to the output of the potential detection circuit, a source end is connected to the data line, and a current detection load device is connected in series to the current detection NMOS transistor, and a gate A data line stabilizing transistor circuit having an NMOS transistor whose end is connected to the output of the current detection circuit and connected between the output of the potential detection circuit and the data line is provided.

<Operation> With the above configuration, when the memory cell is selected and the potential of the data line is at the “Low” level, the potential detection circuit becomes “Hig.
The data line is charged through the current detection NMOS transistor and the charging NMOS transistor, which outputs the "h" level and receives the "High" level at the gate end. On the other hand, the memory cell has a low threshold voltage. When the potential of the data line is "High" level, it is discharged by the memory cell, and when the data line is overcharged, it is discharged through the memory cell and the data line stabilizing transistor circuit. Since only one inverter is required, the current consumption is low,
The occupied area is reduced, and the dependence of ΔVh on manufacturing variations is reduced. Further, when the data line is overcharged, it is discharged through both the memory cell and the data line stabilizing transistor circuit, so that high speed performance is not impaired.

<Example> Hereinafter, the present invention will be described in detail with reference to illustrated examples.

FIG. 1 is a circuit diagram of this embodiment, in which a bit line 4 which is an output line of a memory cell 3 is connected to a data line 1 via a column selector 2.

Now, the potentials of the column decoder 5 and the word line 6 are
When it reaches Vdd, the memory cell 3 is selected. When the memory cell 3 has a high threshold voltage, almost no current flows through the memory cell 3. Therefore, when the data line 1 (bit line 4) is in the “Low” level state, the inverter 7 changes the potential of the data line 1. Detect and set output to "High" level. Then,
Charging is continued via the charging NMOS transistor 8 and the current detecting NMOS transistor 9, and when the data line 1 (bit line 4) reaches the potential Va, the NMOS transistors 8 and 9 are turned off. At this time, Vout becomes Vdd level, and charging is continued via the stabilizing transistors 10 and 11, and the data line 1
When the potential of the (bit line 4) reaches Vb, the charging from the stabilizing transistors 10 and 11 is completed, and as a result, the potential (Vdata) of the data line 1 stabilizes at "High" level at Vb, and Vout
Is at Vdd level.

On the other hand, when the memory cell 3 has a low threshold voltage, the data line 1
If (bit line 4) is at "High" level, memory cell 3
Is discharged by data line 1 (bit line 4) is "Low"
If it is a level, the inverter 7 will turn on the NMOS transistor 8,
Charged through 9. As a result, data line 1
The potential of (bit line 4) stabilizes at a potential Vc determined by the inverter 7, the PMOS load transistor 12 as a charging load device and the PMOS load transistor 13 as a current detecting load device. At this time, the current of the memory cell 3 flows divided according to the capacity ratio of the PMOS load transistors 12 and 13. Here, the capacity of the PMOS load transistor 13, which is a current detection load transistor, is set so that Vout is at a "Low" level at this time.

Summarizing the above, the characteristics of this sense amplifier circuit are as shown in FIG. That is, when the memory cell 3 has a high threshold voltage, a current flows through the data line 1 as shown in the current characteristic (A), and the potential Vdata of the data line 1 becomes stable from Va to Vb. Then, the output voltage Vout becomes Vdd according to the voltage characteristic (B) and becomes stable. On the other hand, when the memory cell has a low threshold voltage, the potential of the data line 1 is stabilized at the potential Vc at the intersection of the current characteristic (A) and the memory cell current characteristic (C) at the low threshold voltage.

As described above, the number of inverters can be reduced by one compared with the conventional example, so that the current consumption is reduced and the occupied area can be reduced. In addition, ΔVh is the inverter 37, 38 and NMO in the conventional example.
Although it depends on the characteristics of the S transistors 41, 42, 43, in the present embodiment, it depends only on the inverter 7 and the NMOS transistors 8 and 9, so that the dependence of ΔVh on the manufacturing variation can be reduced. Furthermore, data line 1 (bit line 4)
In the overcharged state, the data is discharged through the memory cell 3 and the stabilizing transistors 10 and 11, so that the data can be read without impairing the high speed.

<Effects of the Invention> As is apparent from the above, the sense amplifier circuit of the present invention requires only one potential detection circuit composed of an inverter, so that the current consumption and the occupied area can be reduced, and Δ
It is possible to reduce the dependency of Vh on manufacturing variations. Further, when the data line is overcharged, the data line is discharged through the memory cell and the data line stabilizing transistor circuit, so that data can be read without impairing the high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the sense amplifier circuit of the present invention, FIG. 2 is a diagram showing characteristics of the above embodiment, FIG. 3 is a circuit diagram of a conventional sense amplifier circuit, and FIG. It is a figure which shows the characteristic of an example. 1 ... Data line, 2 ... Column selector, 3 ... Memory cell,
4 ... bit line, 7 ... inverter, 8,9,11 ... NMOS transistor, 10,12,13 ... PMOS transistor.

Claims (1)

[Claims] 1. A potential detection circuit comprising an inverter having a data line connected to a bit line which is an output line of a memory cell through a selection circuit as an input, and a gate terminal connected to the output of the potential detection circuit and having a source A current detection circuit in which a current detection load device is connected in series to a current detection NMOS transistor whose end is connected to the data line, and an NMOS transistor whose gate end is connected to the output of the current detection circuit is connected to the potential detection circuit. And a data line stabilizing transistor circuit connected between the output and the data line, the gate end is connected to the output of the potential detection circuit, and the source end is connected to the data line A sense amplifier circuit comprising: a charging circuit in which load devices are connected in series.