JPH01214133A - Marking of semiconductor wafer - Google Patents
Marking of semiconductor waferInfo
- Publication number
- JPH01214133A JPH01214133A JP63041154A JP4115488A JPH01214133A JP H01214133 A JPH01214133 A JP H01214133A JP 63041154 A JP63041154 A JP 63041154A JP 4115488 A JP4115488 A JP 4115488A JP H01214133 A JPH01214133 A JP H01214133A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bad
- defective
- recording plate
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 18
- 230000002950 deficient Effects 0.000 claims description 40
- 238000012360 testing method Methods 0.000 abstract description 17
- 239000003550 marker Substances 0.000 abstract description 6
- 239000000523 sample Substances 0.000 abstract description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体チップをウェハー状態にて試験した後、
不良のチップを記録する方法に関するものである。[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides a method for testing semiconductor chips in a wafer state.
This invention relates to a method for recording defective chips.
半導体チップをウェハー状態で試験した後、不良のチッ
プには印(マーク)をつけ、ウェハーを1つ1つのチッ
プに切り離したあと、その不良のマーク(不良打点)の
ついたチップは組立前に取り除かれる。図3はその例で
あるが、不良チップには不良打点がついており、打点は
針でチップの表面に傷をつける又はレーザーで表面を焼
く方法等がとられている。After testing semiconductor chips in the wafer state, marks are placed on defective chips, the wafer is separated into individual chips, and the chips with the defective marks (defective dots) are removed before assembly. be removed. As shown in FIG. 3, defective chips have defective dots, and the dots are created by scratching the surface of the chip with a needle or burning the surface with a laser.
従来より不良チップの表示方法(打点方法)として、針
でチップの表面に傷をつけたり、レーザーで焼いたりし
て、そのチップを完全な不良(損傷させる)にしまい、
あとで取り除くことにしている。Conventionally, the method of indicating defective chips (dotting method) is to scratch the surface of the chip with a needle or burn it with a laser, making the chip completely defective (damaging).
I plan to remove it later.
この場合、完全な不良にしてしまうため以下のような不
具合がある。試験の際、途中で試験装置が故障したり、
テスト条件・方法が不安定であったりして、良品とすべ
きものが不良とされ、打点されてしまい、完全不良にさ
れてしまった後に、不具合がわかり、試験しなおそうと
しても、チップは救剤できない。In this case, the product becomes completely defective, resulting in the following problems. During the test, the test equipment may malfunction during the test.
If the test conditions or method were unstable, what should have been a good product was marked as defective, marked as defective, and even if the defect was discovered and the test was attempted again, the chip could not be salvaged. I can't take medicine.
C問題点を解決するための手段〕
従来は不良チップの表面に直接打点していたのを、本発
明の方法は、他の媒体に不良チップの場所を記録し、あ
とで不良チップを取り除く際には、その記録を使用する
ものである。Means for Solving Problem C] Instead of the conventional method of directly marking the surface of a defective chip, the method of the present invention records the location of the defective chip on another medium, and when removing the defective chip later, the method records the location of the defective chip on another medium. The records shall be used for this purpose.
次に本発明について図面を用いて説明する。 Next, the present invention will be explained using the drawings.
第1図は不良チップの位置を記録する記録板であり、記
録板上には被試験物であるウェハー及びウェハー上のチ
ップと同じ大きさ、形の図形がかかれている。これはま
ったく同じ大きさでなくてもよくチップの位置関係がわ
かるものであればよい。FIG. 1 shows a recording plate for recording the position of a defective chip, and on the recording plate there is drawn a wafer, which is an object to be tested, and a figure of the same size and shape as the chip on the wafer. These do not have to be exactly the same size as long as the positional relationship of the chips can be understood.
本方法においては不良のマークはこの記録板上の、不良
チップに相当する位置にし、不良チップ自身には打点さ
れない。In this method, a defective mark is placed on the recording plate at a position corresponding to the defective chip, and the defective chip itself is not marked.
第2図は、ウェハー状態での試験系の概念図である。こ
こにおいて被試験ウェハーはステージ7におかれ、ステ
ージ7が動くごとに各チップに測定用探針3があてられ
て電気的試験が行なわれる。FIG. 2 is a conceptual diagram of a test system in a wafer state. Here, the wafer to be tested is placed on a stage 7, and each time the stage 7 moves, the measurement probe 3 is applied to each chip to perform an electrical test.
この際記録板4はステージ8におかれているが、ステー
ジ8はステージ7と同じ動きをするようにさせておき、
試験中であるチップに相当する記録板上の場所が、常に
マーカー2の下にくるようになっている。At this time, the recording plate 4 is placed on the stage 8, but the stage 8 is made to move in the same way as the stage 7.
The location on the recording board corresponding to the chip under test is always located below marker 2.
そこで試験されたチップが不良だった場合、マーカー2
にて記録板上に不良であることの印(マーク)をつけれ
ばよい。If the chip tested there is defective, marker 2
Simply put a mark on the recording plate to indicate that it is defective.
このようにして、不良チップの位置が記録板上にマーク
される。不良チップ位置はこの記録板を媒体として後工
程へ送られ、ウェハーを各チップに切り離した後、この
記録板上の情報をもとに不良チップを取り除ける。In this way, the location of the defective chip is marked on the recording plate. The location of the defective chip is sent to a subsequent process using this recording plate as a medium, and after the wafer is cut into chips, the defective chip can be removed based on the information on this recording plate.
前述の実施例は記録板というのを媒体とし、記録板とい
うハードウェアにて不良チップの記録を行なったが、実
施例2としてソフトウェアで行なう方法を述べる。In the embodiments described above, a recording plate was used as a medium, and defective chips were recorded using hardware called a recording plate, but as a second embodiment, a method using software will be described.
第2図において試験装置に、記憶装置が接続されている
。ここで不良チップの位置を記憶装置の記憶媒体の中へ
記憶させておけばよい。後工程への位置情報はこの記憶
媒体によって送られる。記憶媒体としての一例に磁気デ
ィスクが利用できる。In FIG. 2, a storage device is connected to the test device. Here, the location of the defective chip may be stored in the storage medium of the storage device. Position information to subsequent processes is sent by this storage medium. A magnetic disk can be used as an example of a storage medium.
以上説明したように本発明は、直接不良チップに打点せ
ずチップに損傷に与えないため、試験後何らかの不具合
が見つかっても、不具合起因を除去した後、前に一担、
不良とされたものでも再試験して良品であれば救剤でき
る。As explained above, the present invention does not directly impact the defective chip and does not damage the chip, so even if some defect is found after the test, the cause of the defect is removed and then
Even if the product is found to be defective, it can be retested and if found to be good, it can be salvaged.
もう一つの効果としては、各チップに分離した後、不良
チップを自動的に取り除こうとする場合、従来のように
チップ上の針跡、レーザー損傷跡を自動的に認識させて
取り除く方法では認識装置として、複雑な機能のものが
必要となるが、本発明の方法では、簡単な認識装置で可
能となり(記録板上のマークを認識)、又記憶装置を用
いたものは認識装置そのものも必要とせず、ソフトウェ
アにて不良チップが選び出される。Another effect is that when trying to automatically remove defective chips after separating them into chips, the conventional method of automatically recognizing and removing needle marks and laser damage marks on the chips requires a recognition device. However, the method of the present invention can be achieved with a simple recognition device (recognizing marks on a recording board), and the method using a storage device does not require the recognition device itself. First, defective chips are selected by software.
第1図は、本発明の方法に用いられる、不良チップの位
置を記録するものであり、被測定ウェハーのチップの位
置関係を記録できるよう、ウェハー、チップの図形が描
かれている。
ここで 1−・・・・・不良記録板、2・・−・・・ウ
ェハー・チップ図形、3・・・・・・不良マーク、第2
図は本方法を実現させるための試験系の概念図である。
ここで 1・・・・・・被測定ウェハー、2・・・・−
・不良用マーカー、3−・・・・・試験用探針、4・−
・・・・不良記録板、5・・・・・・試験装置、6−・
・・・・マーカー制御部、7・・・・−・ウェハーステ
ージ、8・・・・・−不良記録板ステージ、9・−・・
・・記憶装置、
第3図は従来の方法で不良打点されたウェハーの図であ
る。
ここにおいて 1・・・・・・ウェハー、2・・・・・
・ウェハー上のチップ、3・・・・・・不良打点がつい
ているチップ。
代理人 弁理士 内 原 音FIG. 1 is for recording the position of a defective chip, which is used in the method of the present invention, and the shapes of the wafer and chips are drawn so that the positional relationship of the chips on the wafer to be measured can be recorded. Here, 1-... Defective recording plate, 2... Wafer chip figure, 3... Defective mark, 2nd
The figure is a conceptual diagram of a test system for realizing this method. Here, 1... wafer to be measured, 2...-
・Defective marker, 3-...Test probe, 4-
...Defective recording board, 5...Testing device, 6-.
... Marker control unit, 7 ... Wafer stage, 8 ... Defective recording plate stage, 9 ...
...Storage device, FIG. 3 is a diagram of a wafer with defective dots by the conventional method. Here, 1... wafer, 2...
・Chip on wafer, 3...Chip with defective dots. Agent Patent Attorney Oto Uchihara
Claims (1)
チップに不良打点をせず、他の媒体に記録させておくこ
とを特徴とするマーク方法。A marking method characterized in that when a semiconductor chip on a semiconductor wafer is defective, it is recorded on another medium instead of directly marking the defective point on the chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63041154A JPH01214133A (en) | 1988-02-23 | 1988-02-23 | Marking of semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63041154A JPH01214133A (en) | 1988-02-23 | 1988-02-23 | Marking of semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01214133A true JPH01214133A (en) | 1989-08-28 |
Family
ID=12600504
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63041154A Pending JPH01214133A (en) | 1988-02-23 | 1988-02-23 | Marking of semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01214133A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0574878A (en) * | 1991-09-13 | 1993-03-26 | Nec Yamagata Ltd | Test method of wafer |
CN110243840A (en) * | 2019-07-05 | 2019-09-17 | 德淮半导体有限公司 | Defect detecting system and its defect inspection method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54112176A (en) * | 1978-02-22 | 1979-09-01 | Nec Home Electronics Ltd | Selection method of semiconductor element |
JPS54134568A (en) * | 1978-04-10 | 1979-10-19 | Nec Corp | Wafer mapping unit |
JPS6185837A (en) * | 1984-10-04 | 1986-05-01 | Canon Inc | Chip separating device |
-
1988
- 1988-02-23 JP JP63041154A patent/JPH01214133A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54112176A (en) * | 1978-02-22 | 1979-09-01 | Nec Home Electronics Ltd | Selection method of semiconductor element |
JPS54134568A (en) * | 1978-04-10 | 1979-10-19 | Nec Corp | Wafer mapping unit |
JPS6185837A (en) * | 1984-10-04 | 1986-05-01 | Canon Inc | Chip separating device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0574878A (en) * | 1991-09-13 | 1993-03-26 | Nec Yamagata Ltd | Test method of wafer |
CN110243840A (en) * | 2019-07-05 | 2019-09-17 | 德淮半导体有限公司 | Defect detecting system and its defect inspection method |
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