JPH01213019A - Digital fader device - Google Patents

Abstract

PURPOSE:To gradually change a multiplication coefficient value to follow even when a set coefficient value is changed suddenly and to gradually change a digital output by providing a comparator to compare a coefficient value set with a digital fader circuit and a multiplication coefficient value setter and a multiplier. CONSTITUTION:A digital fader 1 outputs a set coefficient value S set manually. A comparator 3 compares a multiplication coefficient value (m) outputted by a holding circuit 7, when the S is more than the (m), an adding signal Sa is generated, when the S is less than the (m), a substracting signal Ss is generated, and when the S is equal to the (m), the signal is not outputted. A selector 5 outputs an adding value P in the case of the signal Sa, a substracting value M in the case of the signal Sa, and a zero value Z in the case of nothing inputted. An adder 6 adds and outputs a selecting value (e) of the selector 5 and the multiplication coefficient value (m), and the holding circuit 7 holds it until the next output of the adder 6 comes and outputs the coefficient value (m) to a multiplier 2 and the comparator 3. The coefficient (m) is multiplied to a digital input di of a terminal T1, a digital output do is outputted from a terminal T0 and is carried over until the (m) is equal to the S. By such constitution, the setting of the multiplication coefficient value (m) is executed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital fader device that multiplies a digital input by an arbitrary multiplication coefficient value to produce a digital output.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional digital fader device. In the figure, 1 is a digital fader circuit for manually setting a setting coefficient value 8 (multiplication coefficient value m);
indicates a multiplier, and the digital input d from input terminal TI
The digital output d is obtained by multiplying i by the multiplication coefficient value m output by the digital fader circuit 1. It is used for binding and outputting to the output terminal TO.

Next, the operation will be explained.0 Since the digital fist fader circuit 1 outputs a manually set multiplication coefficient value m, the multiplier 2 multiplies the digital input di from the input terminal TX by the multiplication coefficient value m to produce a digital output d. . Therefore, from the output terminal To, a digital output d is obtained by multiplying the digital human power di by the multiplication coefficient value m. is output.

Note that if the multiplication coefficient value m set in the digital fader circuit 1 is, for example, 4 bits, it will range from 0000 to 010.
Although it is possible to instantly change the multiplication coefficient value m from 0000 to 0100, the digital output d. can also change drastically in an instant.

Therefore, the digital output d. When converting to an analog signal and making a sound, an abnormal sound is emitted at the point where the multiplication coefficient value m changes, so the multiplication coefficient value m usually changes from 0000 to 0001.
It is necessary to change it gradually like →0011→0100.

[Problem to be solved by the invention]

Since the conventional digital fader device is configured as described above, when the multiplication coefficient value m is instantaneously changed from, for example, 0000 to 0100 in the digital fader circuit 1, a digital output d is generated. The digital output d changes greatly instantaneously. When converting the signal into an analog signal and making a sound, an abnormal sound is produced at the point where the multiplication coefficient value m changes.

Therefore, the multiplication coefficient value m is 0000→0001→00
Since it is necessary to change the multiplication coefficient m sequentially from 11 to 0100, there is a problem in that it takes time to set the multiplication coefficient value m. This invention was made to solve the above problems. It is an object of the present invention to provide a digital 7-edder device in which a multiplication coefficient value supplied to a multiplier gradually changes even if a set coefficient value is changed instantaneously and greatly in a digital fader circuit.

[Means to solve the problem]

A digital fader device according to the present invention includes a comparator that compares a set coefficient value set in a digital fader circuit with a multiplication coefficient value, and a comparator that compares a set coefficient value set in a digital fader circuit with a multiplication coefficient value, and a set It is equipped with a multiplication coefficient value setter that outputs a value to a multiplier and a comparator while gradually changing the value.

[Effect]

In the digital fader device according to the present invention, the multiplication coefficient value setter sets the multiplication coefficient according to the output of the comparator that compares the set coefficient value outputted by the digital fader circuit with the multiplication coefficient value outputted from the multiplication coefficient value setter. Since the numerical value is gradually changed, the digital output from the multiplier also changes gradually.

〔Example〕

An embodiment of the present invention will be explained below with reference to the drawings. In Fig. 1, the same parts as in Fig. 4 are given the same reference numerals, 3 indicates a comparator, and the digital fader circuit 1 outputs the The set coefficient value S is compared with the multiplication coefficient value m output by the holding circuit 7 of the multiplication coefficient value setter 4, which will be described later.
When the set coefficient value S is larger than the multiplication coefficient value m, an addition signal (comparison signal) S is output, and when the set coefficient value 8 is smaller than the multiplication coefficient value m, a subtraction signal (comparison signal) 8 is output. , when the setting coefficient value B and the multiplication coefficient value m are equal, neither of the two signals 8a+88 is output.

Reference numeral 4 indicates a multiplication coefficient value setter, which is composed of a selector 5, an adder 6, and a retention layer wr1. When the subtraction signal s8 is supplied from the comparator 3, a predetermined subtraction value M is selected, and both signals 8B+8g are output from the comparator 3.
When both are not supplied, zero value Z is selected and output.

The adder 6 adds the selection value e, which is any one of the addition value P, the subtraction value M, and the zero value 2, output from the selection device 5 and the multiplication coefficient value m output from the holding circuit 7. be.

Furthermore, the holding circuit 7 holds the output of the adder 6 until the adder 6 outputs the next output, and uses the multiplication coefficient value m as the multiplication coefficient value m. It is output to the comparator 3 and adder 6.

Next, the operation will be explained.

Since the digital fader circuit 1 outputs the manually set setting coefficient value 8, the comparator 3 compares the setting coefficient value 8 with the multiplication coefficient value m output by the holding circuit 7, and calculates the setting coefficient value S.
When is larger than the multiplication coefficient value m, an addition signal 8a is output, and when the setting coefficient value S is smaller than the multiplication coefficient value m, a subtraction signal S8 is output, so that the setting coefficient value S and the multiplication coefficient value m are When they are equal, neither signal Ba+BB is output.

Therefore, the selector 5 which receives the comparison signal output from the comparator 3 selects the addition value P when the addition signal S& is supplied, and selects the subtraction value M when the subtraction signal S8 is supplied,
If both signals 8B and BB are not output, the zero value 2 is selected and output, so the adder 6 selects and outputs the selected value e outputted by the selector 5.
The k multiplication coefficient value m is added and output.

Then, the output of the adder 6 is held in the holding circuit 7 until the adder 6 outputs the next output, and is used as the multiplication coefficient value m in the multiplier 2. Since it is output to the comparator 3 and the adder 6, the digital input di from the input terminal Ti is multiplied by the multiplication coefficient value m in the multiplier 2, resulting in a digital output d. The above calculation is repeated until the multiplication coefficient value m becomes equal to the set coefficient value 8.

In this way, the setting coefficient value S and the multiplication coefficient value m are always compared, so for example, if the setting coefficient value S is 4 bits 0000,
0100 on digital fader circuit 1.
When the comparator 3 outputs the addition signal sB, the adder 6 changes the addition value P output from the selector 5.
is repeatedly added to the multiplication coefficient value m, and the multiplication coefficient value m
is set to a value between oooo and 0100, and when the multiplication coefficient value m reaches 0100, which is the set coefficient value S, the addition ends.

As mentioned above, even if the setting coefficient value S is changed instantaneously by the digital fader circuit 1, the multiplication coefficient value m gradually changes and follows the setting coefficient value S, so the digital output di also changes gradually. Even if the digital output di is converted into an analog signal and a sound is played, no abnormal noise is produced.

Further, since the setting coefficient value S can be changed instantaneously, setting the multiplication coefficient value m does not require much effort, and the setting of the multiplication coefficient value m becomes easy.

FIG. 2 is a block diagram showing another embodiment of the invention, and the same parts as in FIG. 1 are given the same reference numerals.

In FIG. 2, 4A indicates a multiplication coefficient value setter, which counts up the clock C when the addition signal sB is supplied from the clock generation circuit 8 and the comparator 3 that outputs the clock C, and the subtraction signal S8. is supplied, the clock C is counted down and the multiplication coefficient value m is sent to the multiplier 2. It consists of an up/down counter 9 that outputs to a comparator 3.

Note that the up/down counter 9 counts in steps according to the clock C supplied from the clock generation circuit 8.

Next, the operation will be explained.

Since the digital fader circuit 1 outputs the manually set setting coefficient value 8, the comparator 3 compares the setting coefficient value S with the multiplication coefficient value m output by the up/down counter 9, and outputs the setting coefficient value S. When is larger than the multiplication coefficient value m, an addition signal 8a is output, and when the setting coefficient value S is smaller than the multiplication coefficient value m, a subtraction signal s8 is output, and the setting coefficient value S and the multiplication coefficient value m are When they are equal, neither signal 8H*8B is output.

Therefore, when the addition signal 8a is supplied, the up/down counter 9, which inputs the comparison signal output from the comparator 3, counts up the clock C output from the clock generation circuit 8 to obtain a large multiplication coefficient. m is output, and when the subtraction signal 88 is supplied, the clock C is counted down and a small multiplication coefficient value m is output, and the input terminal T
Digital human power di from i is multiplied by multiplier 2 with multiplication coefficient value m
is multiplied and the digital output d. The above calculation is repeated until the multiplication coefficient value m becomes equal to the set coefficient value S.

The embodiment shown in FIG. 2 described above can also achieve the same effects as the embodiment shown in FIG.

FIG. 3 is a block diagram showing still another embodiment of the present invention, and the same parts as in FIG. 2 are given the same reference numerals.

In FIG. 3, 4B indicates a multiplication coefficient value setter, which counts up the clock C when the addition signal sB is supplied from the clock generation circuit 8 and the comparator 3 that outputs the clock C, and the subtraction signal 8B. is supplied, the clock C is counted down and the multiplication coefficient value m is sent to the multiplier 2. It consists of an up/down Φ counter 9 that outputs to the comparator 3, and a clock control circuit 10 that controls the timing of the clock C output from the clock generation circuit 8.

Next, since the operation is almost the same as that of the embodiment shown in FIG. 2, different points will be explained.

The clock control circuit 10 can control the timing of the clock C output from the clock generation circuit 8.

Therefore, there is an effect that the time during which the multiplication coefficient value m is set to the set coefficient value 8 can be changed by the clock control circuit 10.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a comparator that compares a set coefficient value set by a digital fader circuit with a multiplication coefficient value, and a multiplication coefficient value that is set to a set coefficient value according to a comparison signal outputted from the comparator. Equipped with a multiplication coefficient value setter that outputs to the multiplier and comparator while gradually changing the value up to In order to follow the set coefficient value, the digital output also changes gradually.

Further, since the setting coefficient value can be changed instantaneously, there is an effect that setting the multiplication coefficient value does not take much time and it becomes easy to set the multiplication coefficient value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a digital fader device according to one embodiment of the invention, FIG. 2 is a block diagram showing a digital fader device according to another embodiment of the invention,
FIG. 3 is a block diagram showing a digital fader device according to still another embodiment of the present invention, and FIG. 4 is a block diagram showing a conventional digital fader device. In the figure, 1 is a digital fader circuit, 2 is a multiplier, 3 is a comparator, 4 is a multiplication coefficient value setter, 5 is a selector,
6 indicates an adder, and 7 indicates a holding circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] a digital fader circuit for setting a set coefficient value; a comparator for outputting a comparison signal comparing the set coefficient value and a multiplication coefficient value; A digital fader device comprising: a multiplication coefficient value setter that outputs a multiplication coefficient value while changing the multiplication coefficient value; and a multiplier that multiplies a digital input by the multiplication coefficient value to produce a digital output.