JPS625716A - Attenuator - Google Patents

Abstract

PURPOSE:To supply the desired attenuation to a digital input signal A at a desired step by using a multiplication circuit multiplying a signal by 1/2<k> and a subtraction circuit so as to apply operation of A(1-1/2<k>)<j> to a digital input signal A, where (j) is number of times of operations and selecting (k, j). CONSTITUTION:A selector 1 selecting the digital input signal and a digital signal on the way of operation, a multiplication circuit 2 multiplying the digital signal selected by the selector 1 by 1/2<k> (k=0, 1, 2...) and the 1st delay circuit 3 retarding the digital signal being an output of the selector 1 by a time corresponding to the delay time by the multiplier circuit 2 are provided. Then the subtraction circuit 4 subtracting the digital signal being an output of the multiplier circuit 2 from the digital signal retarded by the 1st delay circuit 3 and the 2nd delay circuit applying the output digital signal of the subtraction circuit 4 to the selector 1 as the digital signal on the way of the operation are provided. Thus, the result of subtractions for a prescribed number of times to the digital input signal is used as the digital output signal.

Description

[Detailed Description of the Invention] [Summary] A multiplication circuit that multiplies the digital input signal A by 1/2'' and a subtraction circuit, and if the number of operations is j, then A (
1-1/2k)j, and k.

By selecting j, a desired amount of attenuation is given to the digital human input signal A at a desired step.

[Industrial application field]

The present invention relates to an attenuator that can provide desired attenuation to a digital input signal such as a digital audio signal.

Attenuators are used in audio monitoring devices and the like to control the audio level. For analog audio signals,
An attenuator made of a variable resistor or the like is used, and for digital audio signals, an attenuator made of a multiplier or the like is used.

[Conventional technology]

Conventional attenuators for digital audio signals.

Attenuators are known that are configured with a multiplier circuit that multiplies by a coefficient of 1 or less, or that attenuates linearly encoded digital audio signals to 1/2 by a bit shift. .

[Problem that the invention seeks to solve]

A conventional attenuator configured with a multiplier circuit requires a parallel multiplier circuit to multiply by a coefficient of 1 or less, which has the disadvantage of making the structure very complicated and expensive. In addition, in the case of a conventional attenuator that attenuates to the power of 2, focus shifting can be achieved with a relatively simple configuration, but the attenuation amount is simply switched to a step of 1 to the power of 2. Therefore, there is a drawback that it is often impossible to obtain the desired amount of attenuation.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned conventional drawbacks and to obtain a desired amount of attenuation with a simple configuration.

[Means for Solving the Problems] The attenuator of the present invention will be described with reference to FIG. Convert the digital signal into 1/2k (.

k=o, 1, 2.3. ...) Multiplying 0 circuit 2
and a first delay circuit 3 that delays the digital signal output from the selector 1 by a time corresponding to the delay time by the multiplier circuit 2. From the digital signal delayed by the first delay circuit 3, the multiplier circuit 2 A subtraction circuit 4 that subtracts the digital signal output from the subtraction circuit 4, and a second delay circuit 5 that adds the digital signal output from the subtraction circuit 4 to the selector 1 as a digital signal in the middle of calculation, and a second delay circuit 5 that applies the digital signal output from the subtraction circuit 4 to the selector l as a digital signal in the middle of calculation. The subtraction result is used as a digital output signal.

[Effect]

The multiplication circuit 2 multiplies by 1 to the exponent of 2, and can be configured as a simple bit shift circuit. By selectively outputting the signal, attenuation equal to the number of 1/2k X operation repetitions can be applied to the digital input signal. Therefore, if the value of k is increased, the step of the attenuation amount becomes smaller, and if the number of calculation repetitions is increased, the attenuation amount becomes larger.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same parts, 6 is a shift register as a second delay circuit, and 7 is an output shift register. Digital input signal a is applied to selector 1, and selector 1 selects between digital input signal a and digital signal g output from a predetermined stage of shift register 6 in response to a control signal. The digital signal output from the selector 1 is applied to a multiplier circuit 2 and a delay circuit 3. The multiplication circuit 2 multiplies 1/2 by 2, and k is
It can be set to a desired value of 0.1.2°3, . . . by setting signal C, and has a circuit configuration that performs k-bit shifting and outputs, and is realized with a simple configuration. can do. For example, if you set k=2, 2
The bits are shifted, and the magnitude of the digital signal is reduced to 1/4 and output.

The digital signal output from the multiplier circuit 2 and the digital signal output from the delay circuit 3 are added to the subtraction circuit 4, and if the digital input signal a is A, then in the subtraction circuit 4, B
= A (1-1/2k) calculation will be performed. Therefore, when the value of k is set to 0°1.2.3.4,
The results are shown in Table 1.

Table 1: Before the next digital input signal a is selected and output by the selector 1, the digital signal g delayed by the shift register 6 is selected and output, and the number of repetitions j is set to 32.
and 64, the maximum attenuation shown in Table 2 can be changed.

Table 2 Table 2 shows that when the digital input signal is a digital signal obtained by linearly encoding an audio signal into 16 bits, and the operating clock signal is 4.096 MHz, the number of calculation repetitions j is 32, and the operating clock Signal 8.192
The figure shows a case where the number of calculation repetitions j is 64 when the frequency is MHz.

The digital signal output from the subtraction circuit 4 is applied to a shift register 6 as a delay circuit, and is applied from a desired shift stage to the selector 1 as a digital signal g in the middle of an operation. When the load timing signal e is applied to the shift register 7, the contents of the register 6 are set in the shift register 7 in parallel to shift 1. When the shift timing signal d is applied to the shift register 7, the digital signals set in parallel are output in series. That is, when the digital output of the subtraction circuit 4 that has performed the desired number of operations is shifted to the shift register 6, the load timing signal e is added, and the attenuated digital signal f is output from the shift register 7. Become.

FIG. 3 is an explanatory diagram of the operation, where ta+ indicates the digital human input signal A, and FIG. 3(b) indicates the control signal S applied to the selector 1. Further, (C) shows a 1/2k×A digital signal of the output of the multiplier circuit 2, and the delay time of the delay circuit 3 is selected so as to match this output phase. Further, (dl indicates the digital signal of A (1-1/2") output from the subtraction circuit 4, and (e) indicates the digital signal of the delayed output from a predetermined shift stage of the shift register 6. (1-1) /2k)
=β, the output signal from one calculation is A-β, and the output signal from two calculations is A-12. Similarly, the output signal when the number of calculation repetitions is j is A−A
' becomes.

Increasing the number of calculation repetitions j over time results in an attenuator that gradually increases the amount of attenuation, and conversely, decreasing the number of calculation repetitions j over time results in an attenuator that gradually decreases the amount of attenuation, thus forming a fade circuit. can do. In this case, by changing the number of shift bits k in the multiplication circuit 2 as well as the number of calculation repetitions j, the rate of change in the amount of attenuation can be arbitrarily selected.

〔Effect of the invention〕

As explained above, in the present invention, the multiplication circuit 2 is 1/2k
(k is a positive integer) By using a multiplication circuit, it can be realized with a simple circuit configuration that simply shifts bits, and the number of operation repetitions j can be controlled by the control of the selector 1 or the selection timing of the output of the subtraction circuit 4. By selecting the desired amount of attenuation, a desired amount of attenuation can be obtained in steps corresponding to the value of k, so there is an advantage that an arbitrary amount of attenuation can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation. 1 is a selector, 2 is a multiplication circuit, 3 is a delay circuit, 4 is a subtraction circuit, 5 is a delay circuit, and 6 and 7 are shift registers.

Claims (1)

[Claims] A selector (1) for selecting a digital input signal and a digital signal in the middle of calculation, and a digital signal selected by the selector (1) by 1/2^k (k=0, 1, 2, 3, ...); a multiplication circuit (2) that multiplies the digital signal selected by the selector (1) for a time corresponding to the delay time by the multiplication circuit (2);
a first delay circuit (3) for delaying; a subtraction circuit (4) for subtracting the digital signal output from the multiplication circuit (2) from the digital signal output from the first delay circuit (3); a second circuit that applies the digital signal output from the circuit (4) to the selector (1) as a digital signal in the middle of the calculation;
An attenuator comprising: a delay circuit (5).