JPH04129311A - Muting device - Google Patents

Abstract

PURPOSE:To decrease an output change per unit time and to prevent noise such as click noise by providing a coefficient generating circuit outputting a gradually increasing or decreasing coefficient and a multiplier circuit outputting the result of multiplication between the coefficient output and a digital data input to the muting device. CONSTITUTION:In the case of fade-out, a fade control signal G is brought into an L level. At first let the relation of k=5, m=3 be set, a digital data input A is set to '01000' and a coefficient input B is set to '111'. When a muting control signal E is set to an H level, an edge detection circuit 6 detects a leading edge of the muting control signal E, an output of an OR circuit 8 goes to an H level and the input B is preset to a preset type up-down counter 4. An output I of an OR circuit 7 goes to an H level and selector 13 selects the result of multiplication JXL by a serial multiplier 12 and given to the coefficient input B. An output H of the multiplier 12 goes to '0' and muting of -infinity db is applied till the muting control signal E returns to an L level. The operation in the case of fade-in is the same as the case with the fade-out.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a muting device using digital processing for digital audio and the like.

(Prior Art) Generally, in digital audio, there is a muting device that performs a fade-in/fade-out, that is, a muting operation, when transitioning from a playback state to a stop state or from a stop state to a playback state.

Therefore, FIG. 5 shows a block diagram of a conventional muting device. In FIG. 5, ]4 is an attenuation circuit, 15 is a parallel/serial conversion circuit, 16 is an inverter, and 17 is a NOR circuit.

In the muting device configured in this way, k
Digital data input A, which is bit parallel data
is subjected to bint shift by the attenuation circuit 14 in accordance with the attenuation control signal F. The direction of the bit shift is determined by the logic level of the fade control signal G.

If this bit shift is digital data of 1 bits, Lebel attenuation can be easily realized by using 2 selectors.

The 1-bit parallel data output from the attenuation circuit 14 is loaded into the parallel/serial conversion circuit 15 by the word clock signal C synchronized with the parallel data, converted into serial data according to the shift clock signal, and then passed through the inverter 16. teNOR
It is input to the circuit 17. The NOR circuit 17 is controlled by the muting control signal E, and muting is realized by setting the output H to the "L" level when the muting control signal E is at the "H" level.

(Problem to be solved by the invention) In the conventional muting device described above, when the muting control signal E goes from the "L" level to the "H" level, the output goes from H to O all at once. For example, when the digital data input A is 16 bits (2's complement) and has the maximum positive value of 7FFF (H) in hexadecimal notation, the muting control signal E changes. When the level becomes “H”, the output is H.
suddenly becomes 0000 (H). At this time, the output change is 7
Since it is a very large value of FFFF (H), it causes noise such as a click sound.

Also, the muting control signal E is from “L” level to “H” level.
``It's the same thing when you move to the level.

The present invention solves the above-mentioned conventional problems, and aims to provide a muting device that does not generate noise such as click sounds by reducing the amount of change in output when muting is applied.

(Means for Solving the Problems) In order to achieve the above object, the muting device of the present invention includes a coefficient generation circuit that outputs a coefficient that gradually decreases or gradually increases, a digital data input, and a coefficient output of the coefficient generation circuit. The configuration includes a multiplication circuit that outputs the multiplication result of the multiplication result.

Further, the coefficient generation circuit specifically includes an edge detection circuit that detects the edge of the muting control signal, a logic circuit that outputs the logical sum of the output of the edge detection circuit and the attenuation control signal, and a logic circuit that outputs the logical sum of the output of the edge detection circuit and the attenuation control signal. An up/down counter whose coefficient input is preset by a logical sum output, an n value detection circuit that detects a match between the output of the up/down counter and a predetermined value n, and an output of the n value detection circuit that receives the output of the n value detection circuit. and a control circuit for stopping supply of the clock signal to the up/down counter.

In addition, in order to execute the muting operation in synchronization with a change in the digital data input to a certain value, an n value detection circuit with an enable that detects the coincidence between the digital data input and the specified value n is provided, and the n value detection circuit The coefficient generation circuit is configured to enable the coefficient output increase/decrease operation based on the output of the circuit.

(Function) With the above configuration, in the present invention, the digital data input is multiplied by the gradually decreasing or gradually increasing coefficient output from the coefficient generation circuit in the multiplication circuit. Therefore, the output of the multiplier circuit gradually decreases or increases.

Furthermore, in the coefficient generation circuit, when the muting control signal changes, the coefficient input to the up/down counter is preset as an initial value.

This counter sequentially counts down or counts up according to the clock signal until the n value detection circuit operates. In other words, muting is applied while suppressing the amount of output change.

Moreover, since the same coefficient continues to be preset in the up/down counter when an attenuation control signal is input, the attenuation operation is executed in accordance with the coefficient input.

Further, when there is no enable power for the n-value detection circuit with enable, the operation of the coefficient generation circuit is permitted by the output of the n-value detection circuit, and the above operation is performed. Then, when an enable input is given to the n-value detection circuit with enable, the coefficient generation circuit is allowed to operate only when the n-value detection circuit detects a match between the digital data input and the predetermined value n, and the muting operation starts. starts.

(Example) Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the muting device in the first embodiment of the present invention, FIG. 2 is a block diagram of the coefficient generation circuit in FIG. 1, and FIG. 3 is a block diagram of the serial multiplication circuit in FIG. 1. It is a diagram.

In FIG. 1, 1 is a parallel/serial conversion circuit that converts 2-bit digital data A into parallel/serial, 2 is an m-bit coefficient as input B, muting control signal E, attenuation control signal F, and fade control signal. A coefficient generation circuit 3 controlled by G is a serial multiplication circuit that multiplies the coefficient output J of the coefficient generation circuit 2 and the serial output of the parallel/serial conversion circuit 1.

In the coefficient generation circuit 2 shown in FIG. 2, 6 is an edge detection circuit for detecting edges of the muting control signal E;
is an OR circuit (logic circuit) that outputs a logical sum signal of the output of the edge detection circuit 6 and the attenuation control signal F. 4 is a preset type up/down counter that uses the output of the OR circuit 8 as a preset signal, uses the m-bit coefficient B as preset data, and switches up and down using a fade control signal G; 5 is a preset type up/down counter An n value detection circuit 9 detects that the m-bit coefficient output J of 4 has reached a predetermined value n, and 9 supplies a word clock signal C to the preset type up/down counter 4 by the output of the n value detection circuit 5. The controlling OR circuit 7 is an OR circuit that outputs a logical sum signal of the muting control signal E and the attenuation control signal F. The output of the OR circuit 7 becomes a switching signal I to the serial multiplier circuit 3.

In the serial multiplication circuit 3 shown in FIG. 3, 12 is a serial multiplier that multiplies the output serial data L of the parallel/serial conversion circuit 1 by the m-bit coefficient output J of the coefficient generation circuit 2 according to the shift clock signal; 13; is a selector that switches between the multiplication result JXL output from the serial multiplier 12 and the input data L using a switching signal I.

Next, the operation of the muting device of the first embodiment configured as described above will be explained with specific numerical examples.

In the case of fade out, set the fade control signal G to “L”
level. First, with k-5 and m=3, digital data manual A is “01000 (binary number)” (hereinafter “
(The numbers in the box are binary numbers unless otherwise specified.)
Let coefficient human power B be "111". Here all coefficients are 1
Below, "111" is 0.111 (binary number) - 7/8
This shows that. Also, usually digital data human power A
changes in synchronization with the word clock signal C, but to simplify the explanation, it is assumed that the digital data input A is “01000”.
″ is assumed to be constant.

First, if both the muting control signal E and the attenuation control signal F are "L level" and neither muting nor attenuation is applied, the output I of the OR circuit 7 in FIG. 2 becomes "L level" and the selector shown in FIG. 13 or A is selected, the input data L of the serial multiplier 12, that is, "01000" is outputted as H as it is.

Next, when the muting control signal E is set to the 'H' level, the state shifts to the muting state as follows.That is, the rising edge of the muting control signal E is detected by the edge detection circuit 6 in FIG. The output of the OR circuit 8 becomes "H" level, and the input B, ie "111"
is preset in the preset type up/down counter 4, and at the same time, the output I of the OR circuit 7 becomes "H" level, and the multiplication result JXL of the selector 13 or B in FIG.
Select. As a result, the multiplication result of "01000" and "111" is output as "00111" or H.

For the next digital data input A, a word clock signal C synchronized with the data is used to perform preset/soto type up/down.
Because down counter 4 counts down by one,
The coefficient J is "110", and the human power data is "01000'"
is multiplied by the coefficient "110" to output "00110". Thereafter, by repeating this operation while decreasing the coefficient J one by one, the output H is attenuated.

Then, when the coefficient J becomes "000", the n value detection circuit 5 in FIG. 2 detects "000" and fixes one input of the OR circuit 9 to "H" level. -The clock supply to counter 4 is stopped and the coefficient J remains at "000". Therefore, the output H of the serial multiplier 12 in FIG. 3 also becomes 0, and muting of 1 db is applied until the muting control signal E returns to the "L" level.

On the other hand, the basic operation for fade-in is the same as for fade-out. However, when the fade control signal G is set to "H" level, the coefficient B1, that is, the counter 4
The initial value of is set to "000". At this time, data “010
The multiplication result of "00" and the coefficient "000' is output as "000" or H. The next word clock signal C causes the Brise-Soto type up/down counter 4 to count up by one, so the coefficient output J becomes "001", and the multiplication result of data "01000" and coefficient "001" is "00".
001" is output as H. Similarly, by repeating this operation while increasing the coefficient J one by one, the output H increases.Then, the coefficient output J becomes "111".
When the n-value detection circuit 5 of FIG. 2 detects that the value has reached ``, the OR circuit 9 is controlled in the same way as described above, and the clock supply to the preset type up/down counter 4 is stopped.

Therefore, the coefficient J remains at "111" and the muting becomes OdB.

Therefore, at the time of attenuation, the attenuation control signal F goes to the "H" level, so the output of the OR circuit 8 in FIG. 2 always goes to the "H" level.
Since the down counter 4 continues to be preset, the coefficient B continues to be input to the serial multiplier 12, and furthermore,
Since the switching signal I is always at "H level," it is possible to perform attenuation according to the coefficient human power B. For example, if the coefficient human power B is "100", the multiplication coefficient J is "1".
00"-0,100 (binary number) indicates -1/2, and -6db of attenuation is applied.

As described above, according to the first embodiment, the coefficient generation circuit 2
By using the digital data input A and the serial multiplier circuit 3, muting is performed in which the output H is automatically gradually decreased or increased in steps of 1/2 of the digital data input A (m is the bit length of the coefficient B). can be applied. Further, the attenuation level can also be set in multiple stages (2 raised to the m power) according to the input coefficient value.

FIG. 4 is a block diagram showing a second embodiment of the present invention. In FIG. 4, 10 is an n-value detection circuit with an enable function whose operation can be stopped by an enable control signal K, and 18 is an OR circuit.

The rest is the same as the first embodiment shown in FIG.

The operation will be explained below. The basic movement is the first
This is the same as the embodiment. In other words, enable control signal K
is at “L” level, the output of the n value detection circuit 10 is “L”
The operation is the same as that of the first embodiment.

When the enable control signal reaches the "H" level, the output of the n-value detection circuit 10 becomes "H" level, the clock supply to the coefficient generation circuit 2 is stopped, and the constant coefficient J continues to be output from the coefficient generation circuit 2.

When the digital data input A matches the value "n", the output of the n value detection circuit 10 returns to the "L" level and a clock is supplied to the coefficient generation circuit 2, which operates in the same manner as in the first embodiment.

As described above, according to the second embodiment, by using the n-value detection circuit 10 with enable, it is possible to execute a muting operation in synchronization with a change in input data to a certain value.

In the above embodiment, the word clock signal C may be used as it is as the clock for the up/down counter 4, or a clock obtained by dividing the word clock may be used.

Furthermore, by selecting the clock for the up/down counter 4 from a plurality of clocks, or by allowing the clock to be frequency divided, it is also possible to select an increase/decrease time from the start of muting.

Furthermore, it goes without saying that the detection level can be made variable by providing a plurality of n-value detection circuits 5 or by allowing the detection values to be set.

(Effects of the Invention) As described above, according to the muting device of the present invention,
It is equipped with a coefficient generation circuit that outputs a coefficient that gradually decreases or increases gradually, and a multiplier circuit that outputs the result of multiplying this coefficient output by a digital data input, so the amount of output change per unit time is small and noise such as clicks is eliminated. Does not occur.

In addition, the output of the edge detection of the muting control signal and the attenuation control signal can be used to increase
By presetting the coefficients of the down counter, multi-level attenuation operations can be performed in addition to muting operations.

Furthermore, if an n-value detection circuit with an enable is provided to enable and control the output increase/decrease operation of the coefficient generation circuit, the muting operation can be controlled by the value of digital data manually.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the muting device in the first embodiment of the present invention, FIG. 2 is a block diagram of the coefficient generation circuit in FIG. 1, and FIG. 3 is a block diagram of the serial multiplication circuit in FIG. 1. It is a diagram. FIG. 4 is a block diagram of a muting device in a second embodiment. FIG. 5 is a block diagram of a conventional muting device. 1...Parallel/serial conversion circuit 2...Coefficient generation circuit 3...Serial multiplication circuit 4...Preset type up/down counter 5...
N value detection circuit 6...Edge detection circuit 7.8.9...OR circuit 10...N value detection circuit with enable 12...Serial multiplier 13...Selector Patent applicant Matsushita Electric Industrial Co., Ltd. Company agent Patent attorney 1) Hiro - Figure 5 1...Parallel/serial conversion circuit 2...Coefficient generation circuit 3...Serial multiplication circuit 4...Preset type a-tub down counter 5
...N value detection circuit 6...Edge detection circuit 7.8.9...OR circuit 10...N value detection circuit with enable 12...Serial multiplier 13...Selector Fig. 1

Claims (3)

[Claims] (1) A muting device comprising: a coefficient generation circuit that outputs a coefficient that gradually decreases or increases; and a multiplication circuit that outputs a multiplication result of a digital data input and a coefficient output of the coefficient generation circuit. (2) The coefficient generation circuit includes an edge detection circuit that detects the edge of the muting control signal, a logic circuit that outputs the logical sum of the output of the edge detection circuit and the attenuation control signal, and a logical sum output of the logic circuit. The coefficient input is preset by
a counter; an n value detection circuit for detecting a match between the output of the up/down counter and a predetermined value n; and supplying a clock signal to the up/down counter upon receiving the output of the n value detection circuit. The muting device according to claim 1, further comprising a control circuit for stopping the muting device. (3) A claim characterized in that it comprises an n-value detection circuit with an enable that detects a match between digital data input and a predetermined value n, and the coefficient generation circuit enables coefficient output increase/decrease operation based on the output of the n-value detection circuit. The muting device according to item (1) or (2).