JPS6298816A - Attenuation device - Google Patents

Abstract

PURPOSE:To obtain a circuit with extremely simple constitution by incorporating a digital filter, and also to execute attenuation with an abundant number of steps. CONSTITUTION:With respect to a data which is delayed by a shift register 1, an impulse response coefficient which is written in a coefficient ROM 2 is multiplied successively. Successively, by an accumulator 4, the data which is multiplied is added and outputted. By repeating said operation by shifting an input data, filtering is executed to a digital signal. When executing an attenuation, SWs 7-10 are all switched to the opposite side. As a result, the data which is inputted to a digital filter is multiplied by an attenuation coefficient which has been stored in a register 5, by a multiplier 3, and thereafter, inputted to a shift register 1. By repeating such an operation, an output of the digital filter is attenuated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an attenuation device in a digital signal processing circuit.

2. Description of the Related Art Currently, a bit shift method is often used when performing annotation in digital signal processing circuits. For example, when attenuating an n-bit signal, this method cuts off the lower m bits and shifts the entire signal to (n-m) bits, resulting in an annotation of -6 mdB. be.

Problem to be solved by the invention - When using the bit shift method described in 7, the annotation level can only be set in 6 dB increments, and the number of steps is also limited by the number of bits of data. Put it away. Therefore, even in the case of soft l-mute, in which muting is performed by successively performing muting in several stages, the slope is limited.

Means for Solving the Problems In view of the above problems, the present invention performs annotation by multiplying data by coefficients given from the outside. However, the above coefficient is smaller than 1 and will be referred to as an annotation coefficient in the following explanation.

Function: With the above-described configuration, the present invention can easily increase the number of bits of an annotation coefficient and increase the number of steps in one annotation novel.

Furthermore, random annotation and random soft muting become possible by changing the program of an external microcomputer or the like that provides annotation coefficients.

Further, the above-mentioned annotation device can be realized with a very simple circuit configuration by using the multiplier section together with the multiplier inside the digital filter.

The embodiment diagram is a block diagram showing an embodiment of the present invention. In the figure, 1 is a shift register, which has an input bus 11 and an output bus 12. 2 is a coefficient ROM giving the impulse response of the digital filter, and the output bus 21
has. 3 is a multiplier that multiplies data and coefficients, and has a data input bus 31, a coefficient input bus 32, and a multiplication output bus 33. 4 is an accumulator that adds data after multiplication, and is connected to an input bus 41 and an output bus 42.
has. 5 is a timing generation circuit which outputs various timing signals 51; The above is the basic circuit configuration of a digital filter. Furthermore, in addition to the circuit described above, a register 6 is included which provides an attenuation coefficient.

6 is an external control signal bus 61. Mode switching signal 62
and an attenuation coefficient output bus 63. Further, reference numeral 7.8.9.10 is a mode switching SW for interrupting the calculation of the digital filter and performing attenuation.

The operation of the circuit configured as described above will be explained. First, as a basic operation of the digital filter, data delayed by the shift register 1 is sequentially multiplied by an impulse response coefficient written in the coefficient ROM 2. Then, the accumulator 4 adds the multiplied data and outputs it. By repeating the above operation while shifting the input data, filtering is performed on the digital signal. The above is the basic operation of a digital filter. At this time, all SWs 8,910 are connected to the side shown in the figure.

Next time you perform attennion, SW7, 8°9.1
Switch all 0s to the opposite side. As a result, the data entered into the digital filter is transferred to register 6 by multiplier 3.
After multiplication with the attenuation coefficient stored in , the signal is input to the shift register 1. By repeating the above action, the output of the digital filter is attenuated.

As described above, according to this embodiment, it is possible to realize the attenuation device of the present invention with a simple circuit configuration in which a register for latching the annotation coefficient is added inside the digital filter. Furthermore, by increasing the number of bits in the multiplier and controlling the attenuation coefficient by a microcomputer, it becomes possible to randomly perform attenuation and muting with a large number of steps.

As can be seen from the effects of the invention, according to the present invention, by combining it with a digital filter, a very simple circuit configuration can be achieved.
You can perform attenuation with a rich number of steps.

[Brief explanation of drawings]

The figure is a digital filter diagram in an embodiment of the present invention. 1...Shift register, 2...Coefficient R
OM. 3... Multiplier, 4... Accumulator, 6... Timing generation circuit, θ...
register.

Claims (2)

[Claims] (1) An attenuation device consisting of a register and a multiplier that latches coefficients given from the outside. (2) The attenuation device according to claim 1, wherein the multiplier is a digital filter multiplier composed of a shift register, a coefficient ROM, an accumulator, and a multiplier.