JPH0797738B2 - Attention equipment - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an attenuation device in a digital signal management circuit.

2. Description of the Related Art At present, a bit shift method is often used when performing attenuation in a digital signal processing circuit. In this method, for example, when an n-bit signal is attenuated, the lower m bits are cut and the whole is shifted to (n−m) bits, thereby performing (6 × m) dB attenuation. is there.

Problems to be Solved by the Invention When the above-mentioned bit shift method is used, the attenuation level can be set only in 6 dB steps, and the number of steps is also limited by the number of bits of data. Therefore, even in the case of soft mute in which muting of several stages is continuously performed and muting is performed, the slobe is limited.

Means for Solving the Problems In order to solve the above problems, the present invention includes a register for latching attenuation coefficient data provided from the outside, and an input digital signal data and an attenuation coefficient data latched in the register are provided. Multiplication of
The configuration is performed by using the multiplier used in the digital filter composed of the shift register, the coefficient ROM, the multiplier, and the accumulator.

Operation The present invention can easily increase the number of bits of the attenuation coefficient and the number of steps of the attenuation level by the above-mentioned configuration. Random attenuation and random soft muting are possible by changing the program of the external microcomputer that gives the attenuation coefficient.

Further, the above attenuation device can be realized with a very simple circuit configuration by using the multiplier part together with the multiplier inside the digital filter.

Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a shift register, which has an input bus 11 and an output bus 12. Reference numeral 2 is a coefficient ROM which gives an impulse response of the digital filter, and has an output bus 21. Reference numeral 3 denotes a multiplier for multiplying data by a coefficient, which includes a data input bus 31, a coefficient input bus 32, and a multiplication output bus 33.
Have. An accumulator 4 adds data after multiplication, and has an input bus 41 and an output bus 42. Reference numeral 5 denotes a timing generation circuit which outputs various timing signals 51. The above is the basic circuit configuration of the digital filter. In addition to the above circuit, a register 6 for giving an attenuation coefficient is included. Reference numeral 6 has an external control signal bus 61, a mode switching signal 62 and an attenuation coefficient output bus 63. Further, reference numerals 7, 8, 9 and 10 denote mode switching SWs for interrupting computation as a digital filter and performing attenuation.

The operation of the circuit configured as above will be described. First, as a basic operation of the digital filter, a coefficient is added to the data delayed by the shift register 1.
The impulse response coefficient written in ROM2 is sequentially multiplied. Then, the accumulator 4 adds the multiplied data and outputs it. By repeating the above operation while shifting the input data, the digital signal is filtered. The above is the basic operation of the digital filter. At this time, SWs 7, 8, 9, and 10 are all connected to the side shown in the figure.

Next, when performing attenuation, switch SW7,8,9,10 to the opposite side. As a result, the input data is input to the shift register 1 after being multiplied by the attenuation coefficient stored in the register 6 by the multiplier 3. That is, at the timing at which the input data should be directly written to the shift register 1, the attenuation calculation is first performed in the multiplier 3, and then the output of the multiplier 3 is written to the shift register 1. Then, when the attenuation calculation is completed, all the SWs are connected to the side shown in the figure and the digital filtering calculation is performed. By repeating the above operation, the input of the digital filter is attenuated.

As described above, according to this embodiment, it is possible to realize the attenuation device of the present invention with a simple circuit configuration in which a register for latching the attenuation coefficient is added inside the digital filter. Further, by increasing the number of bits of the multiplier and controlling the attenuation coefficient by the microcomputer, it becomes possible to randomly perform attenuation and mute with a large number of steps.

Although the shift register 1 is used in this embodiment, any arbitrary element such as RAM can be used as the constituent element 1 as long as it has a function of sequentially shifting data. Further, although the example in which the attenuation calculation is performed before the digital filtering calculation has been described in the present embodiment, the attenuation calculation may be performed after the digital filtering calculation.

EFFECTS OF THE INVENTION As described above, according to the present invention, by combining with a digital filter, it is possible to perform attenuation with a large number of steps with an extremely simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a combined circuit of a digital filter and an attenuation device according to an embodiment of the present invention. 1 ... Shift register, 2 ... Coefficient ROM, 3 ... Multiplier, 4 ... Accumulator, 5 ... Timing generation circuit, 6 ... Register.

Claims (1)

[Claims] 1. A digital signal input terminal and a shift register or RAM for sequentially shifting the digital signal.
A coefficient ROM in which impulse coefficients are stored, a register for latching attenuation coefficient data given from the outside, data obtained by sequentially shifting by the shift register or RAM, and an impulse stored in the coefficient ROM A multiplier for multiplying coefficient data or a multiplication of the digital signal given to the input terminal and the attenuation coefficient data latched by the register; and an accumulator used for cumulatively adding the output of the multiplier. A first switch that connects the input terminal to an input bus of the shift register or RAM during filtering operation and connects the input terminal to a connection line to a second switch described below during attenuation operation; and the multiplier during filtering operation The data input bus of the shift register Or a second switch connected to the RAM output bus for connecting the data input bus of the multiplier to the connection line from the first switch during the attenuation operation, and the coefficient input bus of the multiplier during the filtering operation. A third switch connected to the output bus of the coefficient ROM to connect the coefficient input bus of the multiplier to the output bus of the register during attenuation operation; and the output bus of the multiplier to the input bus of the accumulator during filtering operation A fourth switch for connecting the output bus of the multiplier to the input bus of the shift register or RAM during attenuation calculation, and filtering by the shift register or RAM, the coefficient ROM, the multiplier, and the accumulator The multiplier used for calculation is configured by the register and the multiplier. Attenuation device of the digital filter that is configured to use a multiplier to be used in the destination operation.