JPH04100305A - Digital filter - Google Patents

Abstract

PURPOSE:To reduce the circuit area by providing a digital signal selection means selecting one optional digital signal latch means among plural digital signal latch means to the filter. CONSTITUTION:A selection circuit 10 is a circuit selecting one optional coefficient register among coefficient registers 12a-12d, generates control signals S1-S4 in response to a digital signal being a selection signal inputted from input terminals 5a, 5b and gives a digital signal and a clock signal inputted respectively from input terminals 3,4 to the coefficient registers 12a-12d in response to the control signals S1-S4. Then the coefficient registers 12a-12d form plural digital signal latch means latching a digital signal being a coefficient of multipliers 13a-13d. Thus, one optional coefficient among coefficients of the digital filter is revised by not giving an input to all the digital signal latch means and the circuit area is made smaller than the case of providing an input terminal to each coefficient register.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a digital filter, which selects any one of a plurality of digital signal holding means based on a digital signal that is a 4IK selection signal. The present invention relates to a digital filter equipped with digital signal selection means.

[Conventional technology]

An example of a specific configuration of a conventional digital filter is shown in FIG. 2 and will be described.

The circuit configuration shown in FIG. #I2 is known as a general K FIR (finite impulse response) type digital filter.

In FIG. 2, the digital filter includes an input terminal 1 for inputting a digital signal as an input signal, and delay circuits 11a and llb connected in cascade to this input terminal 1.
, l1g, an input terminal 2 for inputting a clock signal for operating each of the delay circuits tia to 11e, an input terminal 3 for inputting a digital signal which is a coefficient of a digital filter, and this input terminal 3. Coefficient registers 12m and 12b for holding digital signals input from the registers 12m and 12b.

12e, 12d, and each coefficient register 12a to 12
An input terminal 4 for inputting a clock signal for operating d, digital signals given from input terminal 1 and each delay circuit 111 to 11e, and each coefficient register 12 &~
Multipliers 13&, 13b, 13e, 1 for performing multiplication with the digital signal given from 12d
3d, an accumulator 14 for adding up the results of each multiplication by the multipliers tSa to 134, and an output terminal 6 for outputting a digital signal which is the output of the accumulator 14C).

Next, the operation of the digital filter shown in FIG. 2 will be explained.

A digital signal, which is an input signal, is sent to each delay circuit 11a to 11e in response to a clock input from an input terminal 2.
The signal is delayed for a predetermined period and provided to each multiplier 13b to 13d. Since the coefficient registers 12a to 12d are cascade-connected to the input terminal 3, the digital signals that are the coefficients of the digital filter are sequentially input from the digital signal held in the coefficient register 12d. and input terminal 4
Each coefficient register 1 responds to clock B input from
2a-124. By changing the digital signal, which is the coefficient of the digital filter, the multiplication results of each multiplier 13 & ~13d change, and the output of the accumulator 14 changes. The advantage of this is that the characteristics of the digital filter can be changed.

[Problem to be solved by the invention]

In the conventional digital filter as described above, the digital signals that are the coefficients of the digital filter are sequentially input to each coefficient register, so even if you change all the coefficients of any one of the coefficients of the digital signal, all It was necessary to enter the coefficient register of 7) f. Further, if each coefficient register is provided with an input terminal, it is possible to easily change only an arbitrary coefficient, but in this case, there is a problem that the wiring area increases and the circuit area becomes large.

The present invention has been made to solve such problems, and it is possible to select any one of a plurality of coefficient registers based on a digital signal that is a selection signal, and to manually input each coefficient register. It is an object of the present invention to provide a digital filter that requires a smaller circuit area than a digital filter.

[Means to solve the problem]

The digital filter according to the present invention includes a plurality of multipliers, a plurality of digital signal holding means for holding digital signals that are coefficients of the multipliers, and a plurality of digital signal holding means that hold digital signals that are coefficients of the multipliers, and a plurality of digital signal holding means that hold digital signals that are coefficients of the multipliers. It is provided with digital signal selection means for selecting any one of the holding means.

[Effect]

In this invention, any one of the plurality of digital signal holding means is selected based on the digital signal which is the selection signal.
By selecting one, any one of the coefficients of the digital filter can be changed without inputting it to all digital signal holding means.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

JllEllEa is a block diagram showing an embodiment of a digital filter according to the present invention, which has four multipliers and coefficient registers, and selects any one of the fourth to fourth coefficient registers based on a digital signal that is a selection signal. An example of the configuration of a FIRi1 digital filter equipped with a selection circuit for selecting coefficient register tubes is shown in FIG.

In Fig. 1, the same numbers as in Fig. 2 indicate corresponding parts, 5m and 5b are input terminals for inputting a digital signal which is a selection signal, and 10 is a digital signal which is a coefficient of a digital filter. Each coefficient register 12a to 1
This is a selection circuit for inputting a clock signal for operating 2d and selecting a coefficient register by a digital signal which is a 2 selection value number.

In this example, the selection circuit 10 is a selection circuit that selects any one of the first to fourth four coefficient registers 121 to 12d, and the input terminal 5&.

a control m@ path for generating a signal S1 + 82 + 83 J 84 in response to a digital signal which is a selection signal inputted from input terminal 5b, and a digital signal inputted from input terminal 3 and input terminal 4, respectively. and switch circuits 20m, 20b, 20e for providing clock signals to each coefficient register in response to each control signal.

20d. The control circuit includes, for example, inverter circuits 21a e 21b = 21e, 21d and AND circuits 22m, 22b, 22e, 22
Consists of d. Here, selection signals input from input terminals 5m and 5b are 411 coefficient registers 12a to 12d.
2-bit digital signals (selection signals) CI, C, and O are used to select the signal. For example, selecting 2'' coefficient registers requires an N-bit selection signal.

The coefficient registers 12-12d constitute a plurality of digital signal holding means for holding digital signals that are coefficients of the multiplier, and the selection circuit 10 selects the plurality of digital signals based on the digital signals that are selection signals. It constitutes a digital signal selection means for selecting any one of the digital signal holding means.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, among the coefficients of the digital filter shown in Figure 1,
For example, when changing only the digital signal held in the coefficient register 21e, the selection signal is changed to CI-II J (
High), CO= rOJ (Low).

This selection signal is input to the control circuit, and the control signal is s,=
rlJ (High), St, 8z, 84
=ro” (L@W). Here, if the switch circuit is conductive at rlJ (Hlgh), only the switch circuit 20e is conductive, and the digital signal and clock signal inputted from the input terminals 3 and 4, respectively, are provided to the coefficient register 21eK. The other coefficient registers operate in the same way by changing the selection signal.

In addition, when changing only an arbitrary coefficient among the coefficients of a digital filter, it is not necessary to input it to all coefficient registers as in the conventional example.

Next, the operations other than the selection circuit are the same as in the conventional example, and the digital signal that is the input signal is delayed by a predetermined period in each of the delay circuits t1a to 11e in response to the clock input from the input terminal 2. It is applied to multipliers 13b to 13d. By changing the digital signal that is the coefficient of the digital filter, the multiplication results of each multiplier t3a to 13d change, and the output of the accumulator 14C changes. This allows the characteristics of the digital filter to be changed.

〔Effect of the invention〕

As described above, according to the present invention, a digital filter having a plurality of multipliers is provided with a plurality of digital signal holding means for holding digital signals that are coefficients of the multipliers, and a plurality of digital signal holding means that hold digital signals that are coefficients of the multipliers, and By providing the digital signal selection means for selecting any one of the plurality of digital signal holding means, any one of the coefficients of the digital filter can be selected without inputting it to all the digital signal holding means. This has the practical effect that the coefficients can be changed and that the circuit area is smaller than when each coefficient register is provided with its own input terminal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital filter according to the present invention, and the second factor is a block diagram showing an example of a conventional digital filter. 10 Ichiban・Contest selection circuit, 11&~11C11+1...Delay circuit, 12a~12d ---9 Coefficient register, 1
3a to 13d... Multiplier, 14... Accumulator, 2
0a to 20d-...Switch circuit, 21a to 21d.
...Inverter IIM, 22a-224...Fist AND circuit.

Claims (1)

[Claims] A plurality of multipliers, a plurality of digital signal holding means for holding digital signals that are coefficients of the multipliers, and an arbitrary one of the plurality of digital signal holding means based on a digital signal that is a selection signal. A digital filter comprising digital signal selection means for selecting a signal.