JP2570893B2 - Signal processing device - Google Patents
Signal processing deviceInfo
- Publication number
- JP2570893B2 JP2570893B2 JP2216317A JP21631790A JP2570893B2 JP 2570893 B2 JP2570893 B2 JP 2570893B2 JP 2216317 A JP2216317 A JP 2216317A JP 21631790 A JP21631790 A JP 21631790A JP 2570893 B2 JP2570893 B2 JP 2570893B2
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- signal
- input terminal
- output
- sum
- coefficient
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Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、信号処理装置に関し、特に重み付け係数を
リアルタイムに切替えてデータ信号との積和演算を行う
ようにした信号処理装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device, and more particularly to a signal processing device that performs a product-sum operation with a data signal by switching a weighting coefficient in real time.
（従来の技術） ディジタル信号処理によって所望のフィルタ特性等を
実現する場合、次式に示す積和演算が行われる。(Prior Art) When a desired filter characteristic or the like is realized by digital signal processing, a product-sum operation represented by the following equation is performed.
ここに、Ｘ（ｔ−ｉ）はｉ番面のデータ信号、W1はｉ
番目の重み付け係数である。この積和演算を実行する積
和演算器は、例えば第５図に示すように構成される。 Here, X (t−i) is the data signal of the i-th surface, and W 1 is the i-th data signal.
Th weighting factor. A product-sum calculator that performs this product-sum operation is configured, for example, as shown in FIG.
第５図において、この積和演算器は、直列に接続した
Ｎ個の記憶器（501〜50N）と、Ｎ個の乗算器（511〜51
N）と、加算器521とで構成される。入力信号はワード直
列のデータ信号であり、そのＮ個のデータ信号｛Ｘ（ｔ
−Ｎ）〜Ｘ（ｔ）｝のそれぞれがＮ個の記憶器（501〜5
0N）の対応するものから同時にＮ個の乗算器（511〜51
N）の対応するものの一方の入力に出力される。一方、
Ｎ個の重み付け係数（W0〜WN-1）はＮ個の乗算器（511
〜51N）の対応するものの他方の入力に与えられ、所定
の重み付けが行われる。そして、加算器521にて各乗算
器出力の総和を算出する。In FIG. 5, the product-sum operation unit includes N storage units (501 to 50N) connected in series and N multipliers (511 to 51N).
N) and an adder 521. The input signal is a word serial data signal, and the N data signals ｛X (t
-N) to X (t)} are N memories (501 to 5).
0N) to N multipliers (511 to 51) at the same time.
N) output to one input of the corresponding one. on the other hand,
N weight coefficients (W 0 ~W N-1) of the N multipliers (511
5151N) and given weighting is applied to the other input. Then, the adder 521 calculates the sum of the outputs of the respective multipliers.
この積和演算器は、前記式（１）をそのまま実行する
ものであるが、同時にＮ個のデータ信号全ての処理を行
うので、Ｎが大きくなるに従い回路規模が増大し実現困
難になる。This product-sum operation unit executes the above-mentioned equation (1) as it is, but simultaneously processes all N data signals. Therefore, as N increases, the circuit scale increases and it becomes difficult to realize.
そこで、第６図に示すような信号処理装置が提案され
ている（「ディジタルパルス圧縮装置」特許出願番号01
−138053号：特開平３−2687号）。これは、並列に動作
するＭ個の積和演算器（601〜60M）と、Ｎ個の重み付け
係数を発生する係数発生器611と、各部のタイミング信
号を発生するタイミング制御器631と、出力合成器6101
とで構成される。各積和演算器は遅延器661と、同662
と、累積器681と、出力制御器691とで構成される。係数
発生器611が発生する重み付け係数は遅延器661にて１ワ
ード分ずつ遅延されて後段に順次伝達され、またタイミ
ング制御器631が発生するタイミング信号も遅延器662に
て１ワード分ずつ遅延されて後段に順次伝達される。そ
して、ワード直列のデータ信号は各積和演算器の累積器
681の一方の入力に並列的に与えられるが、最前段の積
和演算器601の累積器681の他方の入力には係数発生器61
1の出力が直接与えられ、次段の積和演算器602以降の各
累積器681の他方の入力には前段積和演算器の遅延器661
で遅延された重み付け係数が与えられる。Therefore, a signal processing device as shown in FIG. 6 has been proposed (“Digital pulse compression device” Patent Application No. 01).
-138053: JP-A-3-2687). This includes M product-sum calculators (601 to 60M) operating in parallel, a coefficient generator 611 for generating N weighting coefficients, a timing controller 631 for generating a timing signal for each unit, and an output combining unit. Container 6101
It is composed of Each sum-of-products unit is a delay unit 661 and 662
, An accumulator 681, and an output controller 691. The weighting coefficients generated by the coefficient generator 611 are delayed by one word by the delay unit 661 and sequentially transmitted to the subsequent stage, and the timing signal generated by the timing controller 631 is also delayed by one word by the delay unit 662. And transmitted to the subsequent stage. The word-serial data signal is stored in the accumulator of each product-sum operation unit.
One input of the accumulator 681 of the product-sum operation unit 601 at the forefront stage is provided to one input of the
1 is directly given, and the other input of each accumulator 681 after the product-sum operation unit 602 at the next stage is a delay unit 661 of the product-sum operation unit at the previous stage.
The weighted coefficients delayed by are given.
即ち、第７図に示すように、各累積器681への入力デ
ータ信号は第７図の711に示す通りであるが、最前段の
累積器では重み付け係数は遅延していないから、第７図
の701であり、データ信号（X0〜XN-1）について累積操
作が行われる。一方、ｊ番目の累積器では、重み付け係
数は第７図の70jとなるから、データ信号（Xj〜
XN+j-1）について累積操作が行われる。ここに、累積器
681は、１個の乗算器とその出力を加算する加算器とで
構成される。That is, as shown in FIG. 7, the input data signal to each accumulator 681 is as shown at 711 in FIG. 7, but the weighting coefficient is not delayed in the first stage accumulator. a 701, cumulative operation is performed for the data signals (X 0 ~X N-1) . On the other hand, in the j-th accumulator, since the weighting coefficient is 70j of FIG. 7, the data signals (X j ~
X N + j-1 ) is accumulated. Where the accumulator
Reference numeral 681 denotes a single multiplier and an adder for adding its output.
次に、各積和演算器の出力制御器691は、累積器681の
出力状態に応じてそれを出力合成器6101への送出可否を
制御する。Next, the output controller 691 of each product-sum operation unit controls whether or not it can be sent to the output combiner 6101 according to the output state of the accumulator 681.
このように、この信号処理装置は、Ｍ個の積和演算器
を並列動作させることによってＮが大きくなっても回路
規模は大きくならない特徴をもっている。As described above, this signal processing device has a feature that the circuit scale does not increase even when N increases by operating the M product-sum operation units in parallel.
（発明が解決しようとする課題） ところで、信号処理装置では、例えば所望のフィルタ
特性を実現している最中に、その特性をリアルタイムに
変更する必要の生ずる場合がある。即ち、重み付け係数
を時刻tjの時点で切り替えるようにするのである。第６
図に示した信号処理装置で言えば、第１番目から第ｊ−
１番目までの累積器が切り替え前の重み付け係数を用
い、第ｊ番目から第Ｍ番目までの累積器が切り替えの後
の重み付け係数を用いるようにするのである。しかし、
この信号処理装置ではこのような切り替えができないの
で、改善が望まれている。(Problems to be Solved by the Invention) In the signal processing apparatus, for example, while realizing a desired filter characteristic, it may be necessary to change the characteristic in real time. That is, to to switch the weighting coefficients at time t j. Sixth
In the case of the signal processing device shown in FIG.
The first accumulator uses the weighting coefficient before switching, and the jth to Mth accumulators use the weighting coefficient after switching. But,
Since such switching cannot be performed in this signal processing device, improvement is desired.
本発明は、このような問題に鑑みなされたもので、そ
の目的は、重み付け係数をリアルタイムに切替えて演算
を行う重み付け係数切替形の積和演算器を備えた信号処
理装置を提供することにある。The present invention has been made in view of such a problem, and an object of the present invention is to provide a signal processing apparatus including a weighting coefficient switching type product-sum operation unit that performs an operation by switching a weighting coefficient in real time. .
（課題を解決するための手段） 前記目的を達成するために、本発明の信号処理装置は
次の如き構成を有する。(Means for Solving the Problems) In order to achieve the above object, a signal processing device of the present invention has the following configuration.
即ち、第１発明の信号処理装置は、当該装置各部の動
作基準たるタイミング信号を発生するタイミング制御器
と;N個の第１及び第２の重み付け係数をそれぞれ順次発
生する第１及び第２の係数発生器と；切替信号を発生す
る切替制御器と；並列配置される複数の積和演算器と；
この複数の積和演算器の各出力を合成する出力合成器
と；を備え、前記複数の積和演算器は、それぞれ、タイ
ミング信号入力端子、タイミング信号出力端子、切替信
号入力端子、第１の重み付け係数入力端子、第２の重み
付け係数入力端子、重み付け係数出力端子、データ信号
入力端子及び演算結果データの出力端子を備え；各デー
タ信号入力端子、各第２の重み付け係数入力端子及び各
切替信号入力端子にはワード直列のデータ信号、前記第
２係数発生器の出力及び前記切替制御器の出力がそれぞ
れ並列的に入力し；当該複数の積和演算器の一端側の積
和演算器（最前段積和演算器）では第１の重み付け係数
入力端子及びタイミング信号入力端子に前記第１係数発
生器の出力及び前記タイミング制御器の出力がそれぞれ
入力し；前記最前段積和演算器の次の積和演算器以降の
各積和演算器では第１の重み付け係数入力端子及びタイ
ミング信号入力端子に前段積和演算器の重み付け係数出
力端子の信号及びタイミング信号出力端子の信号がそれ
ぞれ入力し；かつ、各積和演算器は、第１の重み付け係
数入力端子の信号と第２の重み付け係数入力端子の信号
とを切替信号入力端子の信号に従って切替出力する係数
選択器と；前記係数選択器の出力を１ワード分遅延して
重み付け係数出力端子に送出する第１遅延器と；タイミ
ング信号入力端子の信号を１ワード分遅延してタイミン
グ信号出力端子に送出する第２遅延器と；データ信号入
力端子に印加されるデータ信号の各ワードと前記係数選
択器の出力たるＮ個の重み付け係数の対応するもの同士
の乗算を行い、それらを累積加算する累積器と；前記累
積器の出力状態に応じて信号出力端子への信号送出の可
否制御をする出力制御器と；を備えることを特徴とする
ものである。That is, the signal processing device of the first invention includes a timing controller that generates a timing signal that is an operation reference of each unit of the device, and a first and a second that sequentially generate N first and second weighting coefficients, respectively. A coefficient generator; a switching controller for generating a switching signal; a plurality of multiply-accumulate operators arranged in parallel;
An output combiner that combines the outputs of the plurality of sum-of-products arithmetic units; wherein the plurality of sum-of-products arithmetic units are respectively a timing signal input terminal, a timing signal output terminal, a switching signal input terminal, and a first A weighting coefficient input terminal, a second weighting coefficient input terminal, a weighting coefficient output terminal, a data signal input terminal, and an output terminal for operation result data; each data signal input terminal, each second weighting coefficient input terminal, and each switching signal An input terminal receives in parallel a word-serial data signal, the output of the second coefficient generator, and the output of the switching controller. The sum-of-products calculator at one end of the plurality of sum-of-products (most An output of the first coefficient generator and an output of the timing controller are respectively input to a first weighting coefficient input terminal and a timing signal input terminal; In each of the sum-of-products units following the sum-of-products unit, the first weighting coefficient input terminal and the timing signal input terminal are connected to the signal of the weighting coefficient output terminal of the preceding stage sum-of-products arithmetic unit and the signal of the timing signal output terminal And a product selector that switches and outputs the signal of the first weighting coefficient input terminal and the signal of the second weighting coefficient input terminal in accordance with the signal of the switching signal input terminal; A first delay unit for delaying the output of the coefficient selector by one word and sending it to the weighting coefficient output terminal; a second delay unit for delaying the signal at the timing signal input terminal by one word and sending it to the timing signal output terminal Multiplying each word of the data signal applied to the data signal input terminal by the corresponding one of the N weighting coefficients output from the coefficient selector, and accumulating them. It is characterized in further comprising a; a product unit; and an output controller for whether control signal sent to the signal output terminal in response to the output state of the accumulator.
また、第２発明の信号処理装置は、当該装置各部の動
作基準たるタイミング信号を発生するタイミング制御器
と;N個の第１及び第２の重み付け係数を時分割多重して
発生する単一の係数発生器と；切替信号を発生する切替
制御器と；並列配置される複数の積和演算器と；この複
数の積和演算器の各出力を合成する出力合成器と；を備
え、前記複数の積和演算器は、それぞれ、タイミング信
号入力端子、タイミング信号出力端子、切替信号入力端
子、重み付け係数入力端子、重み付け係数出力端子、デ
ータ信号入力端子及び演算結果データの出力端子を備
え；各データ信号入力端子及び各切替信号入力端子には
ワード直列のデータ信号及び前記切替制御器の出力がそ
れぞれ並列的に入力し；当該複数の積和演算器の一端側
の積和演算器（最前段積和演算器）では重み付け係数入
力端子及びタイミング信号入力端子に前記係数発生器の
出力及び前記タイミング制御器の出力がそれぞれ入力
し；前記最前段積和演算器の次の積和演算器以降の各積
和演算器では重み付け係数入力端子及びタイミング信号
入力端子に前段積和演算器の重み付け係数出力端子の信
号及びタイミング信号出力端子の信号がそれぞれ入力
し；かつ、各積和演算器は、重み付け係数入力端子の信
号を１ワード分遅延して重み付け係数出力端子に送出す
る第１遅延器と；タイミング信号入力端子の信号を１ワ
ード分遅延してタイミング信号出力端子に送出する第２
遅延器と；重み付け係数入力端子の信号をそれぞれ適宜
量分遅延して出力する第３及び第４の遅延器と；前記第
３遅延器の出力信号と前記第４遅延器の出力信号とを切
替信号入力端子の信号に従って切替出力する係数選択器
と；データ信号入力端子に印加されるデータ信号の各ワ
ードと前記係数選択器の出力たるＮ個の重み付け係数の
対応するもの同士の乗算を行い、それらを累積加算する
累積器と；前記累積器の出力状態に応じて信号出力端子
への信号送出の可否制御をする出力制御器と；を備えた
ことを特徴とするものである。The signal processing device of the second invention includes a timing controller that generates a timing signal as an operation reference of each unit of the device; and a single signal that is generated by time-division multiplexing the N first and second weighting coefficients. A switch generator for generating a switching signal; a plurality of sum-of-products arithmetic units arranged in parallel; and an output combiner for synthesizing respective outputs of the plurality of sum-of-products arithmetic units. Each of which has a timing signal input terminal, a timing signal output terminal, a switching signal input terminal, a weighting coefficient input terminal, a weighting coefficient output terminal, a data signal input terminal, and an output terminal for operation result data; A word-serial data signal and the output of the switching controller are input in parallel to the signal input terminal and each switching signal input terminal, respectively; In the sum operation unit), the output of the coefficient generator and the output of the timing controller are input to the weighting coefficient input terminal and the timing signal input terminal, respectively; In the product-sum operation unit, the signal of the weighting coefficient output terminal and the signal of the timing signal output terminal of the preceding stage product-sum operation unit are input to the weighting coefficient input terminal and the timing signal input terminal, respectively. A first delay unit for delaying the signal at the input terminal by one word and sending it to the weighting coefficient output terminal; a second delay unit for delaying the signal at the timing signal input terminal by one word and sending it to the timing signal output terminal
A delay unit; third and fourth delay units for respectively delaying the signal at the weighting coefficient input terminal by an appropriate amount and outputting the same; switching between an output signal of the third delay unit and an output signal of the fourth delay unit A coefficient selector for switching and outputting according to the signal of the signal input terminal; multiplying each word of the data signal applied to the data signal input terminal by a corresponding one of the N weighting coefficients output from the coefficient selector; An accumulator for accumulating and adding them; and an output controller for controlling whether a signal can be sent to a signal output terminal according to an output state of the accumulator.
（作 用） 次に、前記の如く構成される本発明の信号処理装置の
作用を説明する。(Operation) Next, the operation of the signal processing device of the present invention configured as described above will be described.
第１発明では、２種の重み付け係数をそれぞれ発生す
る第１及び第２の係数発生器を設け、第１の重み付け係
数は遅延させながら各積和演算器を順次伝達させ、第２
の重み付け係数は各積和演算器に並列的に供給し、各積
和演算器では両重み付け係数の一方を選択し、これとデ
ータ信号との演算を行うようにしてある。In the first invention, first and second coefficient generators for respectively generating two types of weighting coefficients are provided, and the first weighting coefficients are sequentially transmitted to the respective product-sum calculators while being delayed.
Are supplied in parallel to each product-sum operation unit, and each product-sum operation unit selects one of the two weighting coefficients and performs an operation on this and the data signal.
また、第２発明では、１つの係数発生器で２種の重み
付け係数を時分割的に発生させ、それを遅延させながら
各積和演算器を順次伝達させるとともに、各積和演算器
において２種の重み付け係数に分離しその一方を選択
し、これとデータ信号との演算を行う。In the second invention, one coefficient generator generates two types of weighting coefficients in a time-division manner, and sequentially transmits the weighted coefficients to the respective product-sum operation units while delaying the weighted coefficients. And selects one of them, and performs an operation on this and the data signal.
斯くして、リアルタイムに重み付け係数を切替えるこ
とのできる積和演算器を備えた信号処理装置を簡単な構
成で実現できる。Thus, it is possible to realize a signal processing device having a product-sum calculator capable of switching the weighting coefficient in real time with a simple configuration.
（実 施 例） 以下、本発明の実施例を図面を参照して説明する。Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例に係る信号処理装置を示
す。この信号処理装置は、並列に動作するＭ個の積和演
算器（101〜10M）と、Ｎ個の第１の重み付け係数Ｗを発
生する（第１）係数発生器111と、Ｎ個の第２の重み付
け係数Ｗ′を発生する（第２）係数発生器112と、切替
信号を発生する切替制御器121と、タイミング制御器131
と、出力合成器1101とで基本的に構成され、これらはタ
イミング制御器131からのタイミング信号に従って動作
する。FIG. 1 shows a signal processing apparatus according to one embodiment of the present invention. This signal processing device includes M product-sum calculators (101 to 10M) operating in parallel, a (first) coefficient generator 111 for generating N first weighting coefficients W, and N number of (Second) coefficient generator 112 for generating a weighting coefficient W ′ of 2, a switching controller 121 for generating a switching signal, and a timing controller 131
And an output combiner 1101, which operate according to a timing signal from the timing controller 131.
各積和演算器は、係数選択器151（15j）と、（第１）
遅延器161（16j）と、（第２）遅延器171（17j）と、累
積器181（18j）と、出力制御器191（19j）とで基本的に
構成される。なお、入出力端子は図示省略した。Each product-sum operation unit includes a coefficient selector 151 (15j) and a (first)
It basically includes a delay device 161 (16j), a (second) delay device 171 (17j), an accumulator 181 (18j), and an output controller 191 (19j). The input / output terminals are not shown.
切替制御器121からの切替信号と係数発生器112からの
第２の重み付け係数は各積和演算器の係数選択器に並列
的に入力し、またデータ信号は各積和演算器の累積器の
一方の入力端に並列的に印加される。一方、係数発生器
111からの第１の重み付け係数は最前段の積和演算器101
の係数選択器151に入力する。係数選択器151は切替信号
に従って第１の重み付け係数と第２の重み付け係数を切
替えて出力するもので、その出力は累積器181の他方の
入力と遅延器161とに与えられる。遅延器161は入力され
た重み付け係数を１ワード分遅延して次段の積和演算器
102の係数選択器152に出力する。以下、同様に終段の積
和演算器10Mまで遅延されながら伝達される。タイミン
グ制御器131からのタイミング信号も同様に各段で遅延
されながら終段の積和演算器10Mまで伝達される。The switching signal from the switching controller 121 and the second weighting coefficient from the coefficient generator 112 are input in parallel to a coefficient selector of each product-sum calculator, and the data signal is input to an accumulator of each product-sum calculator. It is applied in parallel to one input. Meanwhile, the coefficient generator
The first weighting coefficient from 111 is the sum-of-products calculator 101 in the first stage.
Is input to the coefficient selector 151. The coefficient selector 151 switches and outputs the first weighting coefficient and the second weighting coefficient according to the switching signal, and the output is provided to the other input of the accumulator 181 and the delay unit 161. The delay unit 161 delays the input weighting coefficient by one word, and performs a product-sum operation at the next stage.
Output to the coefficient selector 152 of 102. Hereinafter, similarly, it is transmitted to the final stage product-sum operation unit 10M while being delayed. Similarly, the timing signal from the timing controller 131 is transmitted to the final stage product-sum operation unit 10M while being delayed at each stage.
以上の構成において、時刻tjで係数の切替えを行う場
合、tj以後のデータ信号を用いる積和演算器では第２の
重み付け係数Ｗ′を用いることになる。そこで、切替制
御器121は積和演算器10jの係数選択器15jに対し第２の
重み付け係数Ｗ′の選択を内容とする切替信号を出力す
る。なお、最前段の積和演算器101の係数選択器151では
第１の重み付け係数Ｗを選択し、次段の積和演算器102
以降であって積和演算器10jを除くものの係数選択器で
は前段積和演算器の（第１）遅延器の出力を選択する。
その結果、積和演算器10j以降では第２の重み付け係数
Ｗ′が用いられることになり、各積和演算器におけるデ
ータ信号と重み付け係数のタイミング関係は第２図に示
すようになる。In the above configuration, when the coefficient is switched at time t j , the product-sum calculator using the data signal after t j uses the second weighting coefficient W ′. Therefore, the switching controller 121 outputs a switching signal containing the selection of the second weighting coefficient W 'to the coefficient selector 15j of the product-sum calculator 10j. Note that the first weighting coefficient W is selected by the coefficient selector 151 of the sum-of-products calculator 101 at the first stage, and the product-sum calculator 102 of the next stage is selected.
After that, except for the product-sum operation unit 10j, the coefficient selector selects the output of the (first) delay unit of the preceding-stage product-sum operation unit.
As a result, the second weighting coefficient W 'is used after the product-sum operation unit 10j, and the timing relationship between the data signal and the weighting coefficient in each product-sum operation unit is as shown in FIG.
第２図において、211はデータ信号であり、このデー
タ信号のデータXjにおいて切替えが行われる。従って、
最前段の積和演算器101でのデータ信号Ｘと第１の重み
付け係数Ｗのタイミング関係は201のようになり、次段
の積和演算器102では202のように１ワード分ずれたタイ
ミング関係となる。一方、積和演算器10j以降では第２
の重み付け係数Ｗ′が用いられるから、20jや20j＋１に
示すようになる。In FIG. 2, reference numeral 211 denotes a data signal, and switching is performed on data Xj of the data signal. Therefore,
The timing relationship between the data signal X and the first weighting coefficient W in the first stage sum-of-products arithmetic unit 101 is as shown by 201, and the timing relationship shifted by one word as shown in 202 in the next stage sum-of-products arithmetic unit 102. Becomes On the other hand, after the product-sum operation unit 10j, the second
20j or 20j + 1 because the weighting coefficient W ′ is used.
次に、第３図は本発明の他の実施例に係る信号処理装
置を示す。本第２実施例では、係数発生器を311の１個
とし、これに第４図の401に示すように第１の重み付け
係数Ｗと第２の重み付け係数Ｗ′とを時分割的に発生さ
せるようにしてある。第４図の403は遅延器361の出力を
示すが、このように係数発生器311の出力は各積和演算
器において１ワード分ずつ遅延されながら終段の積和演
算器30Mまで伝達される。また、最前段の積和演算器301
では係数発生器311の出力が（第３）遅延器362と（第
４）遅延器363に与えられ、ここで第１の重み付け係数
Ｗと第２の重み付け係数Ｗ′とに分離され（第４図中の
402）、係数選択器351に入力する。積和演算器302以降
では前段積和演算器から送られて来る時分割重み付け係
数を同様に分離する。Next, FIG. 3 shows a signal processing apparatus according to another embodiment of the present invention. In the second embodiment, the number of coefficient generators is one of 311 and a first weighting coefficient W and a second weighting coefficient W 'are generated in a time-division manner as shown at 401 in FIG. It is like that. Reference numeral 403 in FIG. 4 indicates the output of the delay unit 361. As described above, the output of the coefficient generator 311 is transmitted to the final stage product-sum calculator 30M while being delayed by one word in each product-sum calculator. . Also, the product-sum operation unit 301 at the forefront stage
In (2), the output of the coefficient generator 311 is provided to a (third) delay unit 362 and a (fourth) delay unit 363, where it is separated into a first weighting coefficient W and a second weighting coefficient W '(fourth). In the figure
402), input to the coefficient selector 351. After the product-sum operation unit 302, the time division weighting coefficient sent from the preceding product-sum operation unit is similarly separated.
動作は前記第１実施例と同様であるのでその説明を省
略する。The operation is the same as in the first embodiment, and a description thereof will be omitted.
なお、切替制御器121、同321が切替信号を出力するタ
イミングは、外部から入力される基準信号に基づき時間
計測して設定すると良い。Note that the timing at which the switching controllers 121 and 321 output the switching signal may be set by measuring the time based on a reference signal input from the outside.
（発明の効果） 以上説明したように、第１発明では２つの係数発生器
を設け、第１の重み付け係数は遅延させながら各積和演
算器を順次伝達させ、第２の重み付け係数は各積和演算
器に並列的に供給し、各積和演算器で両重み付け係数の
一方を選択する。また、第２発明では１つの係数発生器
で２種の重み付け係数を時分割的に発生させ、それを遅
延させながら各積和演算器を順次伝達させるとともに、
各積和演算器において２種の重み付け係数を分離しその
一方を選択するようにしたので、リアルタイムに重み付
け係数を切替えることのできる積和演算器を備えた信号
処理装置を簡単な構成で実現できる効果がある。(Effects of the Invention) As described above, in the first invention, two coefficient generators are provided, the first weighting coefficients are sequentially transmitted to the respective product-sum calculators while being delayed, and the second weighting coefficients are determined by the respective product weights. It is supplied in parallel to the sum calculator and one of the two weighting coefficients is selected in each product sum calculator. In the second invention, one coefficient generator generates two kinds of weighting coefficients in a time-division manner, and sequentially transmits the sum-of-products while delaying them,
Since the two types of weighting factors are separated in each product-sum operation unit and one of them is selected, a signal processing device having a product-sum operation unit capable of switching the weighting factor in real time can be realized with a simple configuration. effective.
第１図は本発明の一実施例に係る信号処理装置の構成ブ
ロック図、第２図は動作タイムチャート、第３図は本発
明の他の実施例に係る信号処理装置の構成ブロック図、
第４図は動作タイムチャート、第５図は従来の積和演算
器の構成ブロック図、第６図は本発明が対象とする従来
の信号処理装置の構成ブロック図、第７図は動作タイム
チャートである。 101〜10M,301〜30M……積和演算器、111……（第１）係
数発生器、112……（第２）係数発生器、121,321……切
替制御器、131,331……タイミング制御器、151（15j）,
351……係数選択器、161（16j）,361……（第１）遅延
器、171（17j）,371……（第２）遅延器、181（18j）,3
81……累積器、191（19j）、391……出力制御器、311…
…係数発生器、362……（第３）遅延器、363……（第
４）遅延器、1101,3101……出力合成器。FIG. 1 is a configuration block diagram of a signal processing device according to one embodiment of the present invention, FIG. 2 is an operation time chart, FIG. 3 is a configuration block diagram of a signal processing device according to another embodiment of the present invention,
4 is an operation time chart, FIG. 5 is a configuration block diagram of a conventional product-sum operation unit, FIG. 6 is a configuration block diagram of a conventional signal processing device to which the present invention is applied, and FIG. 7 is an operation time chart. It is. 101 to 10M, 301 to 30M: product-sum calculator, 111: (first) coefficient generator, 112: (second) coefficient generator, 121, 321: switching controller, 131, 331: timing controller, 151 (15j),
351... Coefficient selector, 161 (16j), 361 (first) delayer, 171 (17j), 371 (second) delayer, 181 (18j), 3
81: Accumulator, 191 (19j), 391: Output controller, 311
... coefficient generator, 362 ... (third) delay device, 363 ... (fourth) delay device, 1101,3101 ... output combiner.
Claims (2)
号を発生するタイミング制御器と;N個の第１及び第２の
重み付け係数をそれぞれ順次発生する第１及び第２の係
数発生器と；切替信号を発生する切替制御器と；並列配
置される複数の積和演算器と；この複数の積和演算器の
各出力を合成する出力合成器と；を備え、前記複数の積
和演算器は、それぞれ、タイミング信号入力端子、タイ
ミング信号出力端子、切替信号入力端子、第１の重み付
け係数入力端子、第２の重み付け係数入力端子、重み付
け係数出力端子、データ信号入力端子及び演算結果デー
タの出力端子を備え；各データ信号入力端子、各第２の
重み付け係数入力端子及び各切替信号入力端子にはワー
ド直列のデータ信号、前記第２係数発生器の出力及び前
記切替制御器の出力がそれぞれ並列的に入力し；当該複
数の積和演算器の一端側の積和演算器（最前段積和演算
器）では第１の重み付け係数入力端子及びタイミング信
号入力端子に前記第１係数発生器の出力及び前記タイミ
ング制御器の出力がそれぞれ入力し；前記最前段積和演
算器の次の積和演算器以降の各積和演算器では第１の重
み付け係数入力端子及びタイミング信号入力端子に前段
積和演算器の重み付け係数出力端子の信号及びタイミン
グ信号出力端子の信号がそれぞれ入力し；かつ、各積和
演算器は、第１の重み付け係数入力端子の信号と第２の
重み付け係数入力端子の信号とを切替信号入力端子の信
号に従って切替出力する係数選択器と；前記係数選択器
の出力を１ワード分遅延して重み付け係数出力端子に送
出する第１遅延器と；タイミング信号入力端子の信号を
１ワード分遅延してタイミング信号出力端子に送出する
第２遅延器と；データ信号入力端子に印加されるデータ
信号の各ワードと前記係数選択器の出力たるＮ個の重み
付け係数の対応するもの同士の乗算を行い、それらを累
積加算する累積器と；前記累積器の出力状態に応じて信
号出力端子への信号送出の可否制御をする出力制御器
と；を備えることを特徴とする信号処理装置。A timing controller for generating a timing signal as an operation reference of each section of the apparatus; a first and a second coefficient generator for sequentially generating N first and second weighting coefficients, respectively; A switching controller for generating a signal; a plurality of sum-of-products units arranged in parallel; and an output combiner for synthesizing respective outputs of the plurality of sum-of-products units; , A timing signal input terminal, a timing signal output terminal, a switching signal input terminal, a first weighting coefficient input terminal, a second weighting coefficient input terminal, a weighting coefficient output terminal, a data signal input terminal, and an output terminal of operation result data, respectively. A word-serial data signal, an output of the second coefficient generator, and an output of the switching controller. The data signal input terminal, the second weighting coefficient input terminal, and the switching signal input terminal each have a word serial data signal. Are input in parallel; the sum-of-products arithmetic unit at the one end of the plurality of sum-of-products arithmetic units (the first stage sum-of-products arithmetic unit) is configured to generate the first coefficient at a first weighting coefficient input terminal and a timing signal input terminal. The output of the timing controller and the output of the timing controller are respectively input to the first weighting coefficient input terminal and the timing signal input terminal in each of the sum-of-products units subsequent to the first-stage sum-of-products arithmetic unit. The signal of the weighting coefficient output terminal and the signal of the timing signal output terminal of the preceding stage product-sum operation unit are respectively input; and each of the product-sum operation units is connected to the signal of the first weighting coefficient input terminal and the second weighting coefficient input terminal. And a first delayer for delaying the output of the coefficient selector by one word and sending it to a weighting coefficient output terminal; a timing signal; A second delay unit for delaying the signal at the input terminal by one word and sending it to the timing signal output terminal; each word of the data signal applied to the data signal input terminal; and N weighting coefficients which are the outputs of the coefficient selector And an output controller that controls whether a signal can be transmitted to a signal output terminal according to the output state of the accumulator. Signal processing device.
号を発生するタイミング制御器と;N個の第１及び第２の
重み付け係数を時分割多重して発生する単一の係数発生
器と；切替信号を発生する切替制御器と；並列配置され
る複数の積和演算器と；この複数の積和演算器の各出力
を合成する出力合成器と；を備え、前記複数の積和演算
器は、それぞれ、タイミング信号入力端子、タイミング
信号出力端子、切替信号入力端子、重み付け係数入力端
子、重み付け係数出力端子、データ信号入力端子及び演
算結果データの出力端子を備え；各データ信号入力端子
及び各切替信号入力端子にはワード直列のデータ信号及
び前記切替制御器の出力がそれぞれ並列的に入力し；当
該複数の積和演算器の一端側の積和演算器（最前段積和
演算器）では重み付け係数入力端子及びタイミング信号
入力端子に前記係数発生器の出力及び前記タイミング制
御器の出力がそれぞれ入力し；前記最前段積和演算器の
次の積和演算器以降の各積和演算器では重み付け係数入
力端子及びタイミング信号入力端子に前段積和演算器の
重み付け係数出力端子の信号及びタイミング信号出力端
子の信号がそれぞれ入力し；かつ、各積和演算器は、重
み付け係数入力端子の信号を１ワード分遅延して重み付
け係数出力端子に送出する第１遅延器と；タイミング信
号入力端子の信号を１ワード分遅延してタイミング信号
出力端子に送出する第２遅延器と；重み付け係数入力端
子の信号をそれぞれ適宜量分遅延して出力する第３及び
第４の遅延器と；前記第３遅延器の出力信号と前記第４
遅延器の出力信号とを切替信号入力端子の信号に従って
切替出力する係数選択器と；データ信号入力端子に印加
されるデータ信号の各ワードと前記係数選択器の出力た
るＮ個の重み付け係数の対応するもの同士の乗算を行
い、それらを累積加算する累積器と；前記累積器の出力
状態に応じて信号出力端子への信号送出の可否制御をす
る出力制御器と；を備えたことを特徴とする信号処理装
置。2. A timing controller for generating a timing signal as an operation reference of each section of the apparatus; a single coefficient generator for generating the N first and second weighting coefficients by time division multiplexing; A switching controller for generating a signal; a plurality of sum-of-products units arranged in parallel; and an output combiner for synthesizing respective outputs of the plurality of sum-of-products units; A timing signal input terminal, a timing signal output terminal, a switching signal input terminal, a weighting coefficient input terminal, a weighting coefficient output terminal, a data signal input terminal, and an output terminal for operation result data, respectively; each data signal input terminal and each switching A word-serial data signal and the output of the switching controller are input in parallel to a signal input terminal, respectively. The sum-of-products arithmetic unit at one end of the plurality of sum-of-products arithmetic units (the first stage sum-of-products arithmetic unit) has a weight. The output of the coefficient generator and the output of the timing controller are input to the input coefficient input terminal and the timing signal input terminal, respectively; in each of the sum-of-products units subsequent to the first-stage sum-of-products unit, The signal of the weighting coefficient output terminal and the signal of the timing signal output terminal of the preceding product-sum operation unit are respectively input to the weighting coefficient input terminal and the timing signal input terminal; and each of the product-sum operation units outputs the signal of the weighting coefficient input terminal. A first delay unit that delays by one word and sends it to the weighting coefficient output terminal; a second delay unit that delays the signal at the timing signal input terminal by one word and sends it to the timing signal output terminal; Third and fourth delay units for respectively delaying the signals by an appropriate amount and outputting the signals; an output signal of the third delay unit and the fourth delay unit;
A coefficient selector for switching and outputting the output signal of the delay unit in accordance with the signal of the switching signal input terminal; correspondence between each word of the data signal applied to the data signal input terminal and the N weighting coefficients output from the coefficient selector And an output controller for controlling whether or not to send a signal to a signal output terminal according to the output state of the accumulator. Signal processing device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2216317A JP2570893B2 (en) | 1990-08-16 | 1990-08-16 | Signal processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2216317A JP2570893B2 (en) | 1990-08-16 | 1990-08-16 | Signal processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0498903A JPH0498903A (en) | 1992-03-31 |
| JP2570893B2 true JP2570893B2 (en) | 1997-01-16 |
Family
ID=16686636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2216317A Expired - Lifetime JP2570893B2 (en) | 1990-08-16 | 1990-08-16 | Signal processing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2570893B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69832985T2 (en) * | 1998-10-06 | 2006-08-17 | Texas Instruments Inc., Dallas | Multiply-accumulator circuits |
-
1990
- 1990-08-16 JP JP2216317A patent/JP2570893B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0498903A (en) | 1992-03-31 |
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