JPH0563509A - Digital filter - Google Patents

Abstract

PURPOSE:To suppress a limit cycle by providing a 2nd multiplier means multiplying a coefficient whose output is 0 or -1 depending whether an output of a delay means is positive or negative and a subtractor means for outputs 1st and 2nd multiplier means to the filter without discriminating the polarity of the result of the multiplication. CONSTITUTION:A digital signal X from an input terminal 1 is inputted to a delay circuit 2 via an adder 4, in which the signal is delayed by a prescribed time and an output signal Y is outputted from an output terminal 5. Moreover, an output signal XM of the circuit 2 is multiplied with a multiplier coefficient (b) at a multiplier 3 and multiplied with a multiplier coefficient be at a multiplier 6 respectively. Then an output YM of the multiplier 3 is subtracted by an output of the multiplier 6 at a subtractor 7 and the resulting signal YM' is added to the digital input signal X at an adder 4. Then the result is inputted again to the circuit 2. A prescribed characteristic is given to the signal X by applying the processing to the signal repetitively to output the signal Y from the terminal 5. Thus, the limit cycle is suppressed without discriminating the polarity of the result of multiplication.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter used for electronic musical instruments and the like, which imparts a predetermined characteristic to a digital signal.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration example of a conventional feedback type digital filter, in which 1 is a 4-bit two's complement digital signal X.
Input terminal, 2 is a delay circuit that delays the input signal for a predetermined time, and 3 is an output signal of the delay circuit 2, which is a 3-bit 2
A multiplier that multiplies the complement multiplication coefficient b of 4 with an adder that adds the digital signal X and the output signal YM of the multiplier 3,
An output terminal 5 outputs the digital signal Y as the calculation result.

In such a configuration, the digital signal X input from the input terminal 1 is delayed by the adder 4 for a predetermined time in the delay circuit 2 and then output from the output terminal 5 as the output signal Y. After being multiplied by the multiplication coefficient b in the multiplier 3, it is added to the digital signal X in the adder 4 as the signal YM, and is input to the delay circuit 2 again. By repeating the processing described above, the digital signal X is given a predetermined characteristic and is output from the output terminal 5 as the signal Y.

Here, a concrete multiplication result of the multiplier 3 when the multiplication coefficient b is (010) is shown. (1) When the input signal XM of the multiplier 3 is (0001) YM = 0001 × 010 = 0000 10 (rounded down) ∴ YM = 0000 (2) When the input signal XM of the multiplier 3 is (1111) YM = 1111 × 010 = 11111 10 (rounded down) ∴YM = 1111

The multiplication result of the multiplier 3 described above is shown by a black circle in FIG. As can be seen from the figure, when the input signal XM is negative, the multiplication result YM is obtained even if the last two digits are truncated from the LSB.
Will not be (0000). Therefore, even when the input signal disappears in this state, that is, when (0000) is repeated, the output signal repeats (1111) forever, and this is output as noise. Become. This phenomenon is called limit cycle.

Therefore, conventionally, in order to suppress the limit cycle, when the multiplication result YM of the multiplier 3 is negative, correction is made by adding the positive minimum value (0001) to obtain the Δ mark in FIG. To do. That is, the correction value is added or subtracted according to the polarity of the multiplication result. As a result, the output signal Y becomes (0000) even when the multiplication result is negative.

[0007]

In the conventional digital filter described above, it is necessary to determine whether the multiplication result YM of the multiplier 3 is positive or negative. Therefore, this digital filter is used as a digital signal processor (DSP) having no conditional branch. In the case of configuring by (1), there is a drawback that it is not possible to create a microprogram that suppresses the limit cycle. Further, there is a drawback that the configuration of the digital filter becomes complicated because the function of discriminating the polarity is required.

The present invention has been made under such a background, and an object of the present invention is to provide a digital filter capable of suppressing a limit cycle with a simple configuration even when configured by a DSP having no conditional branch. And

[0009]

SUMMARY OF THE INVENTION According to the present invention, an adding means for adding a plurality of input signals, a delay means for delaying the input signals by a predetermined time, and an output signal of the delay means are multiplied by a predetermined multiplication coefficient. In a closed loop so that the output signal of the first multiplication means is fed back to the addition means as an input signal, the output signal of the delay means is positive. In this case, the output signal is (0), and when the output signal of the delay means is negative, the output signal of the delay means is multiplied by a multiplication coefficient which is (-1). And a subtraction unit for subtracting the output signal of the second multiplication unit from the output signal of the first multiplication unit.

[0010]

According to the above construction, the input signal of the digital filter is output as the output signal after being delayed by the adding means for the predetermined time in the delay means. The output signal of the delay means is multiplied by a predetermined multiplication coefficient in the first multiplication means, and when the output signal of the delay means is positive in the second multiplication means, the output signal becomes (0). When the output signal of the delay means is negative, the output signal is multiplied by the multiplication coefficient which becomes (-1). Next, the output signal of the first multiplying means is subtracted from the output signal of the second multiplying means in the subtracting means, then added to the input signal in the adding means, and input again to the delay means. By repeating this processing, a predetermined characteristic is given to the input signal and the signal is output.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing the configuration of a feedback type digital filter according to an embodiment of the present invention. In this figure, parts corresponding to those in FIG. 2 are assigned the same reference numerals and explanations thereof are omitted. In the digital filter shown in this figure, when the input signal is positive, the output signal is (0000), and when the input signal is negative, the output signal is (1111). Multiplier 6 for multiplying signals
And a subtracter 7 for subtracting the output signal of the multiplier 6 from the output signal of the multiplier 3 are newly provided.

In such a configuration, the digital signal X input from the input terminal 1 is delayed by the adder 4 for a predetermined time in the delay circuit 2, and then output from the output terminal 5 as the output signal Y. The output signal XM of the delay circuit 2 is multiplied by the multiplication coefficient b in the multiplier 3 and the multiplication coefficient be in the multiplier 6. Next, the output signal YM of the multiplier 3 is subtracted from the output signal of the multiplier 6 in the subtractor 7, and then added as the signal YM ′ to the digital signal X in the adder 4 and input to the delay circuit 2 again. It By repeating the processing described above, the digital signal X is given a predetermined characteristic and is output from the output terminal 5 as the signal Y.

Here, a concrete calculation result will be shown. (1) When the input signal XM of the multiplier 3 is (0001),
The output signal YM is (0000) as described above. Since the signal XM is positive, the output signal of the multiplier 6 is (0000). Therefore, the output signal YM 'of the subtractor 7 becomes (0000). (2) When the input signal XM of the multiplier 3 is (1111),
The output signal YM is (1111) as described above. Since the signal XM is negative, the output signal of the multiplier 6 is (1111). Therefore, the output signal YM 'of the subtractor 7 becomes (0000). The calculation result described above is indicated by a triangle mark in FIG.

In the above embodiment, the input signal XM is multiplied by the multiplication coefficient be only once, but the number of bits of the multiplication coefficient be is larger than that of the input signal XM. When the number is small, this multiplication is repeated many times.

In the above-described embodiment, the digital filter includes the delay circuit 2, the multiplier 3 and the adder 4.
Although the example in which the closed loop is configured by is shown, the invention is not limited to this. In short, the present invention can be applied to any structure of the feedback type digital filter.

[0016]

As described above, according to the present invention, there is an effect that the limit cycle can be suppressed without discriminating whether the multiplication result is positive or negative. Therefore, this digital filter can be easily constructed by a DSP having no conditional branch. Further, there is an effect that the limit cycle can be suppressed without inputting another signal from the outside.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a feedback type digital filter according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a conventional feedback type digital filter.

FIG. 3 is a diagram showing a calculation result Y for a signal XM of a digital filter according to an embodiment of the present invention and a conventional example.
It is a figure which shows an example of M and YM '.

[Explanation of symbols]

1 ... input terminal, 2 ... delay circuit, 3,6 ... multiplier,
4 ... Adder, 5 ... Output terminal, 7 ... Subtractor.

Claims (1)

[Claims] 1. An adding means for adding a plurality of input signals, a delay means for delaying the input signals by a predetermined time, and a first means for multiplying an output signal of the delay means by a predetermined multiplication coefficient.
In the closed loop so that the output signal of the first multiplying means is fed back to the adding means as an input signal, the output signal of the delaying means is positive. Second output means for multiplying the output signal of the delay means by a multiplication coefficient whose output signal becomes (0) and whose output signal becomes (-1) when the output signal of the delay means is negative. And a subtracting means for subtracting the output signal of the second multiplying means from the output signal of the first multiplying means.