JPH01212972A - Black level correcting circuit - Google Patents

Abstract

PURPOSE:To stably correct a black level and to prevent a brightness from being fluctuated by completely sampling a vertical synchronizing signal. CONSTITUTION:A frequency divider 9 inputs a reference signal synchronizing with a horizontal synchronizing signal from a reference signal input terminal 8, divides a frequency to form a signal having a pulse duration corresponding to the sum of the equalizing periods A, C of the vertical synchronizing signal and a vertical synchronizing period B and input to an OR circuit 5. The OR circuit 5 forms a black level correcting sampling signal from the OR of a vertical blanking signal and a horizontal blanking signal inputted to a horizontal blanking signal input terminal 3 and inputs to a black level hold circuit 6. According to the black level correcting sampling signal, a signal except the video of a video signal inputted to the black level hold circuit 6 through a clamp circuit 2 is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a black level correction circuit used in color television receivers and the like.

[Conventional technology]

The black level of the video signal differs depending on the video source with respect to the back porch pedestal portion of the synchronization signal. Therefore, if only the video signal is pedestally clamped, the black level will fluctuate due to differences in the video source, and the brightness on the screen will vary depending on the channel. To prevent this, a black level correction circuit is used.

FIG. 2 is a block diagram showing a conventional black level correction circuit that functions as described above. 1 is a video signal input terminal, 2
3 is a clamp circuit for clamping the black level of the video signal from the video signal input terminal 1 to a constant potential, and 3 is a horizontal blanking circuit to which a signal for removing a horizontal synchronizing signal (hereinafter referred to as a horizontal blanking signal) is input. Ranking signal input terminal, 4 is a vertical blanking signal input terminal into which a signal for removing the vertical synchronization signal (hereinafter referred to as vertical blanking signal) is input, 5 is the logical sum of the horizontal blanking signal and the vertical blanking signal. 6 is an OR circuit that creates a handling signal for black level correction to extract a signal other than the video (synchronization signal) from the video signal; 6 is a video signal from the clamp circuit 2 and a black level correction signal from the OR circuit 5; A sampling signal is given, and the level of the signal with the lowest level of the signal from which a non-video signal (synchronization signal) is removed from the video signal by the sampling signal for black level correction is held, and the held value is applied to the clamp circuit 2. 7 is an output terminal to which a video signal after black level correction is output.

Next, the operation will be explained. A video signal is input to a clamp circuit 2 via a video signal input terminal 1. The clamp circuit 2 clamps the pedestal level of the video signal to a constant potential and supplies it to the black level hold circuit 6.

On the other hand, the OR circuit 5 receives a horizontal blanking signal synchronized with a horizontal synchronizing signal created based on a flyback pulse, and a vertical blanking signal created based on a vertical synchronizing signal separated from a video signal. It is input via the horizontal blanking signal input terminal 3 and the vertical blanking signal input terminal 4. The OR circuit 5 generates the third signal by ORing the horizontal blanking signal and the vertical blanking signal.
A handling signal for black level correction as shown in Figure (b) is created and output. This sampled signal for black level correction is input to the black level hold circuit 6. Then, signals other than the video signal out of the video signal are handled by a handling signal for black level correction, and the black level hold circuit 6 holds the level of the signal with the lowest level of the remaining video portion, and the value is stored in the clamp circuit 2. give to The clamp circuit 2 clamps the potential given from the black level hold circuit 6 to the constant potential instead of the pedestal level. In this way, fluctuations in the black level due to differences in video sources are prevented, and fluctuations in brightness are prevented.

The black level hold circuit 6 is configured to hold only a level below a predetermined level (1, R,
E) Also, in the case of the same video source, the level of the lowest level signal among the signals is held, and if a different video signal is input afterwards, the lowest level signal among the video signals is held again. It is configured to hold the level of

[Problem to be solved by the invention]

The conventional black level correction circuit is configured as described above, and the horizontal synchronization signal is completely removed by the horizontal blanking signal, but the vertical blanking signal for extracting the vertical synchronization signal is shown in Figure 3(b). As shown in FIG. 3(a), since it was created in synchronization with the start of the vertical synchronization period B of the vertical synchronization signal in the video signal, during the equalization period A before the vertical synchronization period B of the vertical synchronization signal. The handling of the equalization pulse was incomplete. It is also conceivable to use a mono multivibrator or the like to create a signal with a pulse width that responds to the sum of the equalization periods A and C of the vertical synchronization signal and the vertical synchronization period B, and remove the vertical synchronization signal. Difficult to synchronize to vertical synchronization signal. Therefore, the level held by the black level hold circuit 6 is not the darkest level of the video portion, but the sync tip potential of the equalization pulse, resulting in a problem that the black level standard is different and the luminance fluctuates.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a black level correction circuit that can completely extract the vertical synchronization signal and perform stable black level correction.

[Means to solve the problem]

The black level correction circuit according to the present invention includes a clamp circuit that is provided with a video signal and clamps the black level of the video signal to a constant level, and a reference signal synchronized with a horizontal synchronization signal that divides the frequency of the reference signal. By this, a vertical synchronization signal having a pulse width corresponding to the sum of the equalization period and the vertical synchronization period of the vertical synchronization signal of the first half video signal and synchronized with the start of the equalization period that exists immediately before the first half vertical synchronization period. a frequency divider for creating a first signal for removing a signal, a second signal for removing a horizontal synchronization signal, and a first signal created by the frequency divider; A processing signal generation circuit that generates a processing signal for removing signals other than video from the previous video signal by combining the above, and the video signal from the clamp circuit and the sampling signal are provided, and the sampling signal generates the processing signal from the previous video signal. The present invention includes a black level hold circuit which holds the level of the lowest level signal after removing signals other than the video from the video signal, and feeds the held level back to the clamp circuit as a black level.

[Effect]

The frequency divider according to the present invention is provided with a reference signal synchronized with a horizontal synchronization signal, and by frequency-dividing the reference signal, the frequency divider has a pulse width equal to the sum of the equalization period and the vertical synchronization period of the vertical synchronization signal of the video signal. , and a first signal for removing the vertical synchronization signal synchronized with the beginning of the equalization period existing in the orthogonal direction of the vertical synchronization period of the vertical synchronization signal, and provided to the sampling signal generation circuit.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the difference from the conventional circuit in FIG. 2 is that by frequency-dividing the reference signal input from the reference signal input terminal 8, it corresponds to the sum of the equalization period of the vertical synchronization signal and the vertical synchronization period. A frequency divider 9 is newly provided which generates a signal having a pulse width and synchronizes with the start of the equalization period that exists immediately before the synchronization period of the vertical synchronization signal and inputs it to the OR circuit 5. The other configurations are similar to the conventional circuit shown in FIG.

Next, the operation will be explained. The operation from when a video signal is inputted from the video signal input terminal 1, the pedestal level of the signal is clamped to a constant potential by the clamp circuit 2, and then inputted to the black level correction circuit 6 is the same as in the prior art.

On the other hand, a reference signal synchronized with the horizontal synchronizing signal is input to the frequency divider 9 from the reference signal input terminal 8. Then, the frequency divider 9 divides the reference signal to generate a signal having a pulse width corresponding to the sum of the equalization periods A and C of the vertical synchronization signal and the vertical synchronization period B shown in FIG. 3(a). and input it to the OR circuit 5. In order for the signal created by frequency divider 9 to remove the signals within equalization periods A, C and vertical synchronization period B, this signal must be synchronized to the beginning of equalization period A before vertical synchronization period B. Must be. In the M/NTSC (Japanese Standard System) synchronization signal waveform, the frequency of the equalization pulse and vertical synchronization pulse in the vertical synchronization signal shown in Figure 3(a) is 2 times the horizontal synchronization frequency.
The equalization period A and the C2 vertical synchronization period B each become three horizontal periods (3H).

Therefore, based on the start of vertical synchronization period B, the start of the next vertical period is 259.58. Taking advantage of this, a counter (not shown) is reset in synchronization with the start of vertical synchronization period B, and the signal created as described above is synchronized and frequency-divided when 259.58 elapses from that point. The device 9 outputs.

In this way, a vertical blanking signal having the timing and time width shown in FIG. 3(C) is created. Then, as in the past, the OR circuit 5 creates a handling signal for black level correction by ORing the vertical blanking signal and the horizontal blanking signal input to the horizontal blanking signal input terminal 3, and holds the black level. Input to circuit 6. Clamp circuit 2 is activated by the sampling signal for black level correction.
Signals other than video are removed from the video signal input to the black level hold circuit 6 via the black level hold circuit 6. In this case, the vertical blanking signal has a vertical signal equalization period A, as described above.
has a pulse width corresponding to the sum of C and vertical synchronization period B,
Since the signal is synchronized with the beginning of the vertical synchronization signal, the equalization period A of the vertical synchronization signal.

C and all signals within the vertical synchronization period B are removed, and the true black level is held in the black level hold circuit 6.

After that, the operation until the video signal whose black level has been corrected is output to the output terminal 7 is the same as in the conventional example.

〔Effect of the invention〕

As described above, according to the present invention, a reference signal synchronized with a horizontal synchronization signal is provided, and by dividing the frequency of the reference signal, the frequency becomes equal to the sum of the equalization period and the vertical synchronization period of the vertical synchronization signal of the video signal. A first signal for removing a vertical synchronization signal having a pulse width and synchronized with the start of an equalization period existing immediately before the vertical synchronization period of the vertical synchronization signal is created and inputted to a sampling signal creation circuit. Since a frequency divider is provided, the sampling signal created by the sampling signal creation circuit allows
Non-video signals from the video signal can be completely and easily removed, and the true black level is held in the black level correction circuit.
The effect is that stable black level correction is possible and brightness does not fluctuate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional black level correction circuit, and FIG. 3 is a waveform diagram for explaining the operation of FIGS. 1 and 2. It is. In the figure, 2 is a clamp circuit, 5 is an OR circuit, 6 is a black level hold circuit, and 9 is a frequency divider. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A clamp circuit is provided with a video signal and clamps the black level of the video signal to a constant level, and a reference signal synchronized with a horizontal synchronization signal is provided. A pulse width corresponding to the sum of the equalization period of the vertical synchronization signal and the vertical synchronization period, and synchronized with the start of the equalization period that exists immediately before the previous vertical synchronization period, for removing the vertical synchronization signal. A frequency divider that creates the first signal, a second signal for removing the horizontal synchronization signal, and a first signal created by the first frequency divider are given, and by combining these signals, the first signal of the first video signal is generated. A sampling signal generation circuit that generates a sampling signal from which signals other than video are removed; and a sampling signal generation circuit that receives the video signal from the clamp circuit and the sampling signal, and removes the non-video signal from the previous video signal using the sampling signal. and a black level hold circuit that holds the level of the lowest level signal and returns this held level to the clamp circuit as a black level.