JPH01205676A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain high density constitution by eliminating a part of a photoelectric conversion means corresponding to part or all the undesired picture elements in the system and inserting a circuit to the eliminated part. CONSTITUTION:Since blocks at both sides of a photo diode array except in the middle detect a picture element required for the automatic focus detection system, the middle point of the photodiode array corresponds the non-use picture element not required for the automatic focus detection system. Thus, the photodiode(PD) in the middle of the photodiode array corresponding to the non-use picture element is removed and part of the circuit for output processing of a photodiode for brightness monitor being a brightness monitor is inserted to the removed part. Thus, the chip area as the entire solid state image pickup device is reduced and high density constitution is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a solid-state imaging device used in an automatic focus detection device of a camera or the like.

<Prior art> Conventionally, this type of solid-state imaging device
There is one described in 5817 publication. This solid-state imaging device is a C0D (charge coupled device)
The photodiode array includes a photodiode array formed by arranging photodiodes in series from end to end, a transfer register, and a gate disposed between the photodiode array and the transfer register.

<Problems to be Solved by the Invention> By the way, in a device that performs focus detection using a light beam transmitted through a plurality of different regions of the exit pupil of a photographic lens, the pixels necessary for focus detection are located on both sides of the photodiode array except for the vicinity of the center. This is the part. That is, the locations corresponding to effective pixels necessary for the camera's focusing system are at both ends of the photodiode array, and the center location corresponds to invalid pixels unnecessary for the system.

However, in the conventional solid-state imaging device described above, since a photodiode is also provided in the central location where the invalid pixel becomes, a certain area is occupied by the unnecessary invalid pixel, which reduces the area of the chip. There is a problem in that the amount increases.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a solid-state imaging device that can reduce the chip area and obtain a high-density configuration.

<Means for Solving the Problems> In order to achieve the above object, the present invention provides a photoelectric conversion means that has a large number of pixels and generates a charge corresponding to the amount of light incident on each pixel, and a photoelectric conversion means for the photoelectric conversion means. In a solid-state imaging device comprising a transfer register for transferring generated charges and a gate provided between the photoelectric conversion means and the transfer register, the photoelectric conversion means may be used as part of a pixel unnecessary for the system. Alternatively, it is characterized in that all corresponding locations are removed and at least one circuit is inserted into the removed locations.

<Effect> The photoelectric conversion means generates a charge according to the amount of incident light.

This generated charge is controlled by the gate and sent to the transfer register. The transfer register sequentially transfers charges sent from the photoelectric conversion means.

In the photoelectric conversion means, some or all portions corresponding to pixels unnecessary in terms of the system are removed, and at least one circuit is inserted in the removed portions.

In this way, since the parts corresponding to pixels that are not used in the system are effectively used, the chip area of the solid-state imaging device as a whole is reduced, and a high-density configuration can be obtained.

Further, when the solid-state imaging device is used as an automatic focus detection device of a camera, the photoelectric conversion means is removed at the center δ.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

First, a first example will be described. FIG. 1 shows the configuration of an image sensor (13) manufactured as a COD.

(1) is a photodiode array consisting of a plurality of photodiodes (PD) as photoelectric conversion means that generate charges according to the amount of incident light; (ST) is a storage unit that accumulates charges generated by the photodiodes (PD); , (B.G.
) is a field-effect transistor (hereinafter referred to as a field-effect transistor), which is a gate provided between a photodiode (PD) and a storage section (ST).
'It's called FET. ), and this barrier gate (BC;) connects the photodiode (PD) and the storage section (ST) when voltage is applied, and transfers the charge generated in the photodiode (PD) to the storage section (ST). On the other hand, when no voltage is applied, the photodiode (PD) and the storage section (ST) are separated, and the charge generated in the photodiode (PD) stops flowing into the storage section (ST). The above photodiode (PD) and storage section (ST)
) and the barrier gate (BG) constitute storage means. In addition, (RG) is a transfer register that transfers charge from left to right in the drawing by two-phase drive, and (Sl-1) is a storage unit (ST).
This is a transfer gate made of PET, which is a gate provided between the transfer register (rtG) and the transfer register (rtG). This transfer gate (S H) connects the storage section (ST) and transfer register (RG) when voltage is applied, and transfers the charge accumulated in the storage section (ST) to the transfer register (RG), while also transferring the charge accumulated in the storage section (ST) to the transfer register (RG). When not applying, the storage section (ST) and transfer register (r(
G) to prevent charges accumulated in the storage section (ST) from flowing into the transfer register (RG). Also, (R
GICG) is an integral clear gate consisting of a FET as a gate. This integral clear gate (RGICG) is
When voltage is applied, the transfer register (RG) and overflow drain (ODI) are connected, and before integration, unnecessary charges in the photodiode (PD) and storage section (ST) of each pixel are transferred from the transfer register (RG) to the overflow drain (ODI). ODI). The overflow drain (ODI) is connected to the power supply voltage VDD and has the lowest potential.

On the other hand, an overflow gate (OC) is provided between the photodiode (PD) and the overflow drain (OD'2).
No voltage is applied to OG), and the potential is always fixed to be lower than the potential of the barrier gate (BG) when no voltage is applied. The charge of each pixel transferred to the transfer register (RG) is transferred to the transfer lock φ1. φ is sequentially transferred to the capacitor (8-1) from the right side in the drawing. The capacitor (8-I) is F
Charging is reset to the power supply voltage by the 0SRS signal applied to the gate of ET (8-3). Thereafter, the potential of the capacitor (8-1) decreases from the charging voltage by the transferred charge. The voltage between the terminals of this capacitor (8-1) is taken out as an O8 signal by a buffer (8-2).

Although (8-1) has been described here as a capacitor for convenience of explanation, it can be replaced with a PN junction of a diode, and when the circuit is integrated, this capacitor is manufactured as a diode. Hereinafter, the same applies when referring to a capacitor.

On the plurality of photodiodes (PD) at the ends of the photodiode array (1), a light-shielding A12 film (I--I) is provided in order to take out a black reference pixel output, which will be described later.

The photodiode array (1) detects pixels necessary for the automatic focus detection system using blocks on both sides except for the central area.
) corresponds to unused pixels that are unnecessary for the automatic focus detection system. For this reason, the central photodiode (PD) of the photodiode array (1) corresponding to the unused pixel is removed, and a brightness monitoring photodiode (9), which is a brightness monitoring means described later, is installed in this removed portion.
A part of the circuit for output processing is inserted (21st
(see figure).

Further, in order to control the integration time of the image sensor (13), a brightness monitoring photodiode (9) is provided as brightness monitoring means for monitoring the amount of light incident on the photodiode (PD).

This brightness monitoring photodiode (9) has an elongated shape because it is formed across two blocks on both sides of the photodiode array <1) that detects pixels necessary for the automatic focus detection system. In addition, this brightness monitoring photodiode (9) is configured so as not to monitor the amount of light irradiated to the area corresponding to the unused pixel.
A12 film (9-1) is placed on the part corresponding to the above unused pixels.
It is shaded by. In this way, the brightness monitoring photodiode (9) is arranged with the alignment direction of the photodiode array (+) in the elongated direction, and is configured to straddle the two blocks at both ends of the photodiode array (1). Since the portion corresponding to the used pixel is covered with the A12 film (9'-1), the average output level of the portion corresponding to the used pixel can be accurately monitored. A part of the circuit for output processing of the brightness monitoring photodiode (9) is inserted in the center of the photodiode array (1) from which the photodiode (PD) has been removed, as shown in FIG.

As mentioned above, the luminance monitoring photodiode (9) has an elongated shape, and if its length is σ and the output is taken out from one end, then generally the length g and the response time τ
The relationship τcs = (1" holds true, and the longer the length θ, the more rapidly the response deteriorates. Therefore, in order to prevent the response from deteriorating, the center of the brightness monitoring photodiode (9) is The output is taken out from the nearby extraction electrode.Therefore, the response time is 1/4 of the case where a contact is provided at the end of the photodiode (9), as shown in the following equation.

In this way, since the extraction electrode is provided near the center and the response of the brightness monitoring photodiode (9) is fast, even if the integration time is determined based on the output of the brightness monitoring photodiode (9), it will not be excessive. Proper integration can be performed without performing excessive integration that accumulates charges in the storage section (ST).

A capacitor (10-1), which is a storage means, is connected to the brightness monitoring photodiode (9), and prior to the integration of the image sensor (13), an FET (10-3
), the capacitor (10-1) is charged to the power supply voltage VDD. A
After the GCR8 signal is removed, the potential at the capacitor (10-1) drops due to charges generated in response to light irradiation. This potential is outputted as an AGCO8 signal via a buffer (10-2) which is an output means.

The compensation diode (11) is provided to remove the dark output of the brightness monitoring photodiode (9), and a light-shielding AQ film (If-1) is provided thereon. This compensation diode (lI) is designed to obtain the same amount of output as the dark output of the brightness monitor photodiode (9), but if it has the same structure as the brightness monitor photodiode (9). This requires the same area as the brightness monitoring photodiode (9), which makes it difficult to increase the chip size. Therefore, as shown in FIG. 7(a), this compensating diode (11) consists of a large number of parts whose N-type parts are separated from each other and arranged at regular intervals, and these are made into P-type parts. By embedding it in the area, the length (peripheral length) La of the PN junction on the surface, which is the source of dark output, is increased, and the same amount of darkness can be achieved with a smaller size than the photodiode (9) for brightness monitoring. It is designed to provide high output power.

The compensation diode (11) is connected to the capacitor (12-1
). This capacitor (12-1) is connected to the FET (12-3) prior to integration of the image sensor (13).
) is charged to the power supply voltage VDD by the AGCRS signal applied to the gate of the transistor. However, after the AGCR8 signal is removed, the potential of the capacitor (12-■) gradually decreases due to the dark output charge of the compensation diode (11). This potential is output as a DOS signal via a buffer (12-3). This concludes the description of the configuration of the image sensor (I3).

Next, the overall hardware configuration will be explained along with the block diagram shown in FIG. 2 showing an image sensor, a microcomputer, and an interface circuit between them. Second
The cloth (14) in the figure is a microcomputer (14) which is an arithmetic control means for controlling the drive of the image sensor (I3).
μCom). This microcomputer (14)
The image sensor control unit (16) of the image sensor (
13) Outputs two signals MD, , MD for switching the four modes described later, and two signals N B + and N B t for giving operation timing to the bus, and also outputs them from the I10 buffer (22). , Tlt (T signal and image sensor output A
/ADT which is the logical sum with the ADS signal indicating the start of D conversion.
The signal is manually input, and the gain information Gl, G3 signal is
B,,NB, are input using a signal bus.

The circuit on the left side of the above microcomputer (I4) is
■It is constructed on a chip IC (integrated circuit). Among these, the I10 buffer (22) has the following functions.

That is, the function is to OR the TINT signal and the ADS signal and output it to the microcomputer (14) as the ADT signal, and to switch the input/output of the signal line of the NB, ., Ni2° signal so that the Ni2. , NB, the function of inputting the signals from the microcomputer (14) and outputting the Gl and G3 signals to the microcomputer (14) at the time of output, and the signal level of the microcomputer (I4) and the frequency dividing circuit (19), Integral time control section (20
), a signal processing timing generator (2I), a transfer lock generator (30), and other circuits.

On the other hand, the mode selection circuit (23) selects M D + , M
D is a circuit that decodes a signal and selects one of the following four modes. M D , -“L
”.

When MD=“L”, the mode selection circuit (23) is ■N
- Set only the signal to "H" and select INN mode. I
The NI mode is a mode for initializing the image sensor (]I3.MD, -“L”.

In the case of MD, = 'l('', the mode selection circuit (23)
Only the NT signal is set to "H" and the INT mode is selected.

The INT mode is a mode in which the image sensor (13) performs integration. MDI-“H”, M D t = “11
”, the mode selection circuit (23) sets only the DD+ signal to “H” and selects the DDI mode.The DDI mode is a mode in which reading of the image sensor (13) is started, and NB, . This is also a mode in which sample and hold of the black reference pixel, which will be described later, is performed using the NBt signal.MD,
-“■]”, MD2-“L”, mode selection circuit (
23) sets only the DD2 signal to "H" and selects the DD2 mode. In DD2 mode, the image sensor (I3) is read out, and the read and processed output of the image sensor (13) is sent to the microcomputer (14).
This is the mode in which the data is transmitted to the A/D converter (15) of the. The operation and functions of each mode will be described later.

The above frequency dividing circuit (19) is a microcomputer (14)
The base betting clock CP generated by the clock generator (18) of
The image sensor (13) transfer lock φ1. The clock φ that is the source of φ. At the same time,
Integral time control section (20) and signal processing timing generation section (
21) clock φ. A timing clock φ is generated for synchronization with the

The above clock φ. is sent to the transfer lock generation unit (30), where S transmitted from the integral time control unit (20)
H signal, RGICG signal and clock φ.

Therefore, the clock φ3. φ, and serves as a transfer lock for the image sensor (13). The integral time control section (20) receives a timing signal N transmitted from the microcomputer (14) when in INI mode or INT mode.
Based on the signals B, , NB, the AGCRS signal and the BG multiplied signal SH multiplied signal RGICG are generated in synchronization with the clock φ sent from the frequency divider circuit (19), and the integration start operation is performed. Each of the above signals is transmitted to the image sensor (1) shown in Figure 1.
3) are given to each part. In addition, the integral time control section (20
) is the integration completion signal VFLG from the brightness determination circuit (24), which is a subtraction means, which becomes "L" - "r-t" when the integration of the image sensor (13) becomes appropriate, or the mode selection circuit (23). ) A BG multiplied signal is generated by the timing signals NB, , NB2 transmitted when the DDI signal is "H", and an operation for terminating the integration is performed.

Furthermore, this integration time control section (20) is configured so that the DDI signal is “
I]", the timing signal NB,.

Ni2. The signal SH multiplied by this is generated, and the operation to start reading the output from the storage section (ST) is performed. At this time, a signal for obtaining luminance information, which will be described later, an SH multiplied signal, and φa, φb, and φC1φd signals are transmitted to the luminance determination circuit (24). The brightness determination circuit (24) monitors the amount of light irradiated to the image sensor (13) based on the AGCO9 signal and DOS signal sent from the image sensor (13), and when it is determined that the integration has reached an appropriate level. ,V
A function to invert the FLG signal and convert the integration to VFL at low brightness.
If the G signal is an inverse signal inverter, determine the level of integration,
It has a function of outputting Gl and G3 signals for switching the gain of the image sensor (13) according to the level.

AGC differential amplifier circuit (25) is an image sensor (13)
This circuit amplifies the output signal O8 sent from.

In this AGC differential amplifier circuit (25), the FET (8) of the image sensor (13) is turned on by the 09R9 signal.
-3) After sample-bolding the potential O8 immediately after the capacitor (8-ri) is charged by the R9S/H signal sent from the signal processing timing generation section (21),
This potential O8 is transferred to the capacitor (8-
1) The difference between the potential O8 of the capacitor (8-1) dropped by the generated charge of each pixel transferred to 1) is taken, and this is amplified, and the signal Vos' is subtracted by OB subtraction A.
It is output to the GC differential amplifier circuit (26).

The gain of the on-subtraction AGC differential amplifier circuit (26) during amplification is switched by the G3 signal output from the brightness determination circuit (24). Above OB subtraction 8 to C amplification circuit (2
6), the differential amplification between the output of the black reference pixel and the output of the normal pixel without AQ light shielding, that is, the output of the action pixel, and the output V os
' Sample hold is being carried out. Since the photodiode (PD) always has an output in the dark, the pixel detected by the photodiode (PD) with AQ light shielding is used as the black reference pixel and the reference pixel for the dark output, and the output of the normal pixel is used as the reference pixel for the dark output. The value obtained by subtracting the black reference pixel component is the output of the image sensor (13). The OB subtraction AGC amplifier circuit (26) is an AGC differential amplifier circuit (26).
Since the output Vos' from 5) is repeatedly input in synchronization with the transfer lock, the signal processing timing generator (
21) Sample and hold the level of the signal output Vos' of the OSS/HSS/upstream and effective pixels sent from the signal processing timing generator (21), and OBS sent from the signal processing timing generator (21).
The /l~I signal causes the output V to change while the black reference pixel is being output.
Sample and hold os'. Above OB subtraction AGC
The amplifier circuit (26) subtracts the sampled and held black reference pixel output level Vos' from the sampled and held effective pixel output level Vos', and also generates a gain that is switched by the G3 signal output from the brightness determination circuit (24). is applied and output as a signal Vos below the analog reference voltage V ref.

The temperature detection section (27), which is a fixed range voltage output means,
Temperature is detected by the resistance divider circuit shown in Figure 3. This resistance divider circuit (27) includes a diffusion resistance (32) formed by diffusion and a resistance (33) formed of polysilicon (Poly-Si), which are designed to have equal resistance values at room temperature. ing. Each resistor (32), (
33) have different temperature coefficients, the output VTMP output from their connection point via the buffer (34) is V
It depends on the temperature around ref/2. Note that in the DD2 mode, the analog switch (31) is in the correct position = "L", and the current consumption is reduced by turning off the analog switch (31). On the other hand, the analog switch (28) shown in FIG. 2 is turned on in the DD2 mode, that is, when DD2 = "■ ("), and conversely, the analog switch (29) is turned on when DD2 - "L". In the DD2 mode, the signal Vos is output as the output VouL, and in other than the DD2 mode, the signal Vos is output as the output VouL.
The signal VTMP is output as out. The above signal Vou
t is the A/D converter (!4) in the microcomputer (!4).
15), where the analog reference voltage V rer
A/D conversion of the analog output on the lower voltage side is started with the ADT signal and converted into digital data.

In this way, when the analog switches (28, 29) are switched and the OB subtraction AGC differential amplifier circuit (26) is outputting the signal Vos corresponding to the used pixel, the signal is transferred to the A/D converter ( 15), while in other cases, the voltage VTM within a certain range from the temperature detection part (27)
Since P is input manually to the A/D converter (15), the negative output generated by subtracting the output corresponding to the black reference pixel from the output corresponding to the unused pixel from the OB subtraction AGC differential amplifier circuit (26), Even if a negative output is generated by subtracting the output of the black reference pixel from the output of the used pixel after pixel reading is completed, these will not be input to the A/D converter (15) and will not be input to the temperature detector. (27), the voltage V TMPh within a certain range is input to the A/D converter (15). Therefore, the A/D converter (15) will not exceed the input dynamic range and there is no risk of damage. .

This concludes the explanation of the hardware configuration.

Next, the operation of the image sensor (13) described above in each mode will be explained in detail.

First, the initialization mode will be explained.

Microcomputer (14) is MDI, = “L”.

When MD2="L" is output, the mode selection circuit (23)
In this case, only the INI signal is set to “H”, and the integral time control section (20
) is notified that it is in initialization mode (Ill mode). The INI mode is a mode for discharging unnecessary charges from the image sensor (13) immediately after the image sensor (13) is powered on. Image sensor (13
) are potential wells (photodiode (PD), storage section (ST), transfer register (RG)) after power is turned on.
Unnecessary charges are accumulated in each of them, and it is necessary to quickly discharge these charges and start up the image sensor (13) so that it can be used. Therefore, in order to quickly discharge unnecessary charges, the INI mode was set, and the potential structure of the image sensor (13) was changed to the structure shown in FIG. 3.

Hereinafter, explanation will be given along with the potential diagram of FIG. 3 and the time chart of FIG. 4. In FIG. 3(a), from left extension 1 to overflow drain (OD2), overflow gate (OG), and photodiode (PD).

Barrier gate (BG), storage section (ST), transfer gate (SH), transfer register (RG), integral clear gate (
RG I CG), overflow drain (ODl)
It becomes. Barrier gate (BG), transfer gate (S
When voltage is applied to l(), each gate of the integral clear gate (RGICG), and the transfer register (RG) (φ1 is applied to the transfer register (RG)), Fig. 3(b
), PD>BG>ST>SH>RG>RG
The potential is designed so that I CG > OD l, and the photodiode (PD) and storage section (S T
), unnecessary charges in the transfer register (RG) are discharged to the overflow drain (ODl) at this time. This operation will be explained along the time chart.

The state in FIG. 4(a) corresponds to FIG. 3(a).

At this time, with NB=“L” and NBt=“L”,
No voltage is applied to each gate of the barrier gate (BG), transfer gate (S H), and integral clear gate (Rctcc), and also to the photodiode (PD).

Unnecessary charges are accumulated in each section of the storage section (ST) and transfer register (RG). When both NB, NBt are "L", the integral time control section (20) that controls the image sensor (13) does not perform any operation on the image sensor (13).

The microcomputer (14) is NB, -“I-1”.

When Nl32-“L” is output, the integral time control section (20
) is the clock φ sent from the frequency dividing circuit (I9). 5II-“H” as shown in FIG. 4(b).
.

BG="[1"] and IICI CG="[I"] are output to the image sensor (13). Furthermore, the SI-1 signal,
The RGTCG signal is also sent to the transfer lock generation section (30), and the transfer lock generation section (30) receives the SH signal and the clock φ. The OR output of is transferred to lock φ, and R
GICG signal and φ. Transfers the Noah output of and locks φ.

In the case of SH-“H” and RGICG-“I-1”, the transfer lock to the image sensor (13) is stopped in the state of φ-”H” and φ=”L”. . And the image sensor (13) is 5t-1, BGJtGI
CG, φ1. As shown in FIG. 3(b), each signal φ causes the photodiode (PD) and the storage section (S
T), drain unnecessary charges from the transfer register (RG).

The microcomputer (14) then calculates N B r =
After outputting “I]”, NB, = “■1”, NF2. =
“L”.

N B 2 = “H” is output. In response to this, the integral time control section (20) sets the clock φ. synchronized with S I
-1 signal and BG double signal “L” (Figure 3 (C)
, Figure 4(C)). On the other hand, the transfer lock generation unit (30)
Now, as the 5Hfi signal returns to "L", the transfer lock φ1 starts to move, and the transfer lock φ is at "L".

At this time, the potential difference between the transfer register (RG) and the O7 (-flow drain (ODI)) increases, promoting the discharge of unnecessary charges from the transfer register (RG), and completely discharging them to the overflow drain (ODI). (3rd
Figure (d), Figure 4 (d)). Also, at this time, since the transfer lock φ remains stopped at "L", another transfer register (RG) adjacent to the above transfer register (RG) to which the transfer lock φ is applied is connected to the above register. (RG)
No unnecessary charge flows into the circuit.

After the timer measures that the predetermined time has elapsed, the microcomputer (14) controls NB1. Return both NB2 to "shi". The integral time control section (20) thereby adjusts φ.

The RGICG signal is set to "L" in synchronization with. Then, the voltage applied to the RGICG terminal of the image sensor (13) becomes zero, and this integral clear gate (RGICG
) is closed. At the same time, the transfer lock generation unit (30
), the transfer lock φ also starts to move as the RGICG signal becomes “L” (Fig. 3(e), Fig. 4(e))
). With this, one cycle of unnecessary charge discharging operation is completed.

Normally, when initializing the image sensor (13), the above-described unnecessary charge discharge operation is repeated several cycles, and then the initialization mode is ended.

In the present invention, the structure in which an integral clear gate (RGICG) is connected to each register (RG) eliminates the need to discharge unnecessary charge from each register (RG) by transferring it from the register (RG). It is possible to shorten the time for one cycle of the unnecessary charge discharge operation, and to shorten the time allocated to the initialization mode.

Next, the second mode, the integral mode, will be explained.

Microcomputer (I4) is MD, = “L”.

When MD is outputted as -“I-r”, the mode selection circuit (23) sets only the TNT signal to “H” and notifies the integration time control unit (20) that it is in the integration mode (INT mode). . In the INT mode, the image sensor (13) starts integrating and ends the integration during high brightness.

The operation will be explained along with FIGS. 5 and 6. The integration starting operation is exactly the same as the unnecessary charge discharge operation during initialization, except for the BG multiplication signal. BG double signal NB, -“H”
After the microcomputer (14) outputs . (In the figure, this is the rising timing of φ1) and is raised to "I4" in synchronization with the rising timing of φ1. This is the same as in INI mode. However, the microcomputer (I4) is NB, -
When outputting “L”, NBt-“H”, φ in INI mode. Although the BG double signal is returned to "L" again in synchronization with , the BG double signal remains "H" in the INT mode. The BG multiplied signal becomes "L" at the end of integration, which will be described later.

At the time of Fig. 5(C) and Fig. 6(c), the transfer gate (SI
When the gate 1 pressure of I) becomes zero, the transfer gate (Sr4)
returns to a higher potential than the photodiode (FD), storage section CST), and overflow gate (OG), and from this point on, the charge generated in the photodiode (PD) flows into the storage section (ST), and the storage section Accumulation begins at (ST), and integration begins at the image sensor (I3).

On the other hand, the time point at which the integration ends is monitored by the output of the brightness monitoring photodiode (9). The operation of the brightness determination circuit (24) will be explained below, and the operation of completing the integration will be explained.

The integration time control unit (20) transmits the AGCR9 signal to the image sensor (13) at the same timing as the SH multiplication signal at the start of integration.
). As shown in FIG. 1, the AGCR9 signal is applied to a FET (10-1) connected to a capacitor (10-1) connected to a brightness monitoring photodiode (9).
3) and the FET (+2) connected to the capacitor (!2-1) connected to the compensation diode (11).
-3) is applied to the gate. By applying the AGCRS signal, the capacitor (10-1), (
12-1) is charged to approximately the power supply voltage VDD. When the AGCR9 signal becomes “L” at the same timing as the SH double signal,
The power supply is cut off, and from this point on, the brightness monitoring photodiode (9) generates a charge according to the amount of light irradiated, and the capacitor (10-1) connected to it generates a charge according to the generated charge. The potential begins to drop. On the other hand, the compensating diode (11) generates a charge due to its dark output, and the potential of the capacitor (11-1) connected thereto also begins to drop in accordance with the generated charge. Each potential is outputted to the analog circuit shown in FIG. 8 of the brightness determination circuit (24) in FIG. 2 via each buffer (10-2) and (12-2). In FIG. 8, the AGCOS signal is input to the positive input of the operational amplifier (43), the DO9 signal is input to the negative input of the operational amplifier (43), and the differential output is output from the operational amplifier (43).

The output V43 of the operational amplifier (43) is expressed by the following formula.

V4s=Vref-(DOS-AGCOS) This output V
43 is a comparator (45) which is a brightness determination means.
The negative input is done manually.

On the other hand, the positive input of the comparator (45) is connected to the FET (46°47.
A constant voltage generated by resistance division according to 48.49) is supplied. During integration, only φd is “H”, PET (49) is turned on, and the constant voltage supplied is V.
4. =(VrefVth). comparator(
The output of 45) becomes "H" when V43<V411.

That is, Vref-(DOS-AGCOS)<Vref-Vth
When DOS-AGCOS>Vth, it becomes "l(").

(DOS-AGCOS) indicates a voltage dropped due to light irradiation from the brightness monitoring photodiode (9) (the dark output component is compensated by the output of the compensation diode (11)). Immediately after the start of integration, the amount of light irradiated to the brightness monitor photodiode (9) is insufficient, and DOS-
AGCO3 is 0, and the output of the comparator (45) (
VFLG) is at "L". During the integration (DOS-
At the point when AGCO9) becomes larger than the voltage of vth, the integration for the image sensor (13) becomes appropriate, and the output (VFLG) of the comparator (45) changes from "L" to "1".
]". As shown in the time chart of FIG.
5) When the output VFLG is inverted, the BG double signal “L”
”.When the BG double signal becomes “L”, the potential of the barrier gate (BG) becomes larger than the potential of the photodiode (PD), as shown in Figure 5(e), and the potential of the photodiode (PD) increases. The generated charge is prevented from flowing into the storage section (ST), and the charge accumulated in the storage section (ST) is held when the VFLG signal becomes "1 (", that is, the BG multiplied signal "L"). , the integration ends.

The charge generated after the completion of integration is accumulated in the photodiode (FD), and even if the accumulation progresses, as shown in Figure 5 (e), the charge will not pass through the overflow gate (OG), which has a lower potential than the barrier gate (BG). , is discharged to the overflow drain (OD2), so the storage part (ST
).

Further, the integration time control section (20) sets the I3G signal to "L" and simultaneously sets the TINT signal to "L", and notifies the microcomputer (14) of the inversion of the TINT signal via the ADT terminal. This concludes the explanation of the integration start operation in the integration mode and the integration end operation during high brightness.

Next, the third mode, data read mode 1 (DD+
mode).

The microcomputer (14) is MD, -“T-I”.

When M D t = “H” is output, the mode selection circuit (
23) sets only the DDI signal to "H" and notifies the integration time control section (20) that it is in the DDI mode. D.D.I.
The mode is a mode in which the integration is completed when the brightness is low, and the reading of each pixel data of the image sensor (I3) is started.

First, the integration termination operation at low luminance will be explained based on the time chart of FIG. 22. When the subject brightness is low, it may take a long time until the brightness determination circuit (24) determines that the appropriate integration time has been reached. If integration is performed for a long time, the dark output increases, leading to deterioration of the S/N ratio. Furthermore, an extremely long integration time is inconvenient from a system perspective.

For example, when used in a focus detection device for a camera, the focus detection cycle becomes long, resulting in the inconvenience that the focus detection cannot follow the movement of the subject. For this reason, the longest integration time allowable within the microcomputer (14) is set in advance, and if the TINT signal output to the ADT terminal has not been inverted even after this time, M
D+=“H” 1MD, -“H” is output, the mode shifts to the DDI mode, and the operation of terminating the integration is performed in the DDI mode. In the DDI mode, the integral time control section (20)
+ = “H”.

NB, = “L” signal to the microcomputer (14)
When the signal is received from the BG signal, the BG multiplied signal is immediately set to "L". As a result, as in the previous case, the barrier gate (B
The potential of G) becomes higher than that of the photodiode (PD), the charge generated in the photodiode (PD) stops flowing into the storage section (ST), and the integration ends (second
Figure 2).

Next, the operation to start reading out each pixel data of the image sensor (13) will be explained. Regardless of whether the brightness is low or high, the microcomputer (14
) outputs NB=“H” and NB=“L”, the integral time control unit (20) locks the transfer φ. Synchronize and transfer lock φ. generates an SH signal pulse at the timing of "■4" (FIG. 6 or FIG. 22). This results in
As shown in FIGS. 5(f) and (g), a pulse voltage is applied to the S I-1 gate of the image sensor (13), and the signal charges of each pixel accumulated in each accumulation section (ST) are Transferred to transfer register (RG). After that, transfer lock φ1. The signal charge of each pixel is transferred and read out by φ. The microcomputer (14) transfers the signal charges accumulated in each accumulation section (ST) to the transfer register (rtG) in the DDI mode.
This is performed when H4-"L" is output, and at this time, it is necessary that the transfer register (RG) returns from the unsteady state after the start of integration and is in a steady state.

In a steady state, each transfer register (RG) has a dark charge of 23
It is accumulated as shown in the figure. This dark charge is the sum of the dark charge generated in the potential well of each transfer register (RG) and the dark charge of the previous stage register that is sequentially transferred. At the start of integration, the integral clear gate (RGIC
A voltage is applied to the gate terminal of the transfer register (RG).
) and the overflow drain (ODI) is turned on, and the transfer register (R
All dark charges in G) have been cleared. After the integral clear gate (RG I CG) is turned off, the dark charge in the transfer register (RG) reaches a steady state from the left side of FIG. 23 every time one cycle of the transfer lock φ1 passes.

It takes a time equal to the number of pixels (N) x one transfer lock cycle (T) until all transfer registers (RG) return to a steady state.

When the S H pulse is generated in an unsteady state, the dark charge component of the transfer register (RG) in the charge taken out as an output may be in an unsteady state depending on the pixel, so a correct signal cannot be taken out. Therefore, the SH pulse is generated when at least the RGICG signal changes from “[I” to “L”].
After that, the number of pixels x one transfer lock cycle (NX
T) It must be done after some time has elapsed.

At high brightness! Integration is often completed within the period (NXT), but since the integration is terminated by closing the barrier gate (BG), the integration may be completed after one period (NxT).
It is possible to make the generation of the SH pulse wait.

Next, regarding the processing of the read pixel output, FIG.
This will be explained below with reference to FIG.

The signal charge of each pixel of the image sensor (13) is φ, −
At the timing of "L", φ, = "H", it is transferred to the capacitor (8-1) shown in FIG. In the signal processing timing generation section (2I), prior to the transfer of this signal charge, as shown in FIG.
A ClR9 signal pulse is generated at the timing of ", and this pulse is applied to the gate of the FET (8-3) shown in FIG. 1 to charge and reset the capacitor (8-1) to approximately the power supply voltage. φ, = “L”.

When the signal charge is transferred at the time when φ becomes -“H”, the voltage of this capacitor (8-1) decreases due to the signal charge, and the output O8 of the image sensor (13) becomes the 12th
The output is as shown in the figure. AGC differential amplifier circuit (
25), the voltage level at the time of reset is set to the first! by the R9S/H signal sent from the signal processing timing generator (21). The sample and hold circuit consisting of the FET (52), capacitor (53), and buffer (51) shown in the figure allows
It is stored and input to the plus input of the operational amplifier (54).

On the other hand, the O8 signal is input to the negative input of the operational amplifier (54) via the buffer (50), and the F'ET (
55, 56, 57, 58).

The output differentially amplified with the gain determined by the G2 signal (see FIG. 11) is output from the operational amplifier (54) as Vos' (see FIG. 12).

Next, the determination of the integral level will be explained.

If the integration is forcibly terminated when the brightness is low, the level of the pixel output of the image sensor (13) will naturally be lower than when it is appropriate. Therefore, in this case, the above-mentioned brightness determination circuit (24) is used to detect the level of integration, and a gain is applied to the output of the image sensor (13) according to the result, so that an output at an appropriate level is always obtained. I'm trying to be able to do that.

The following will explain the brightness determination analog circuit of FIG. 8, the pulse timing chart of FIG. 9, the brightness determination logic circuit of FIG. 1θ, and the truth table of FIG. Note that the brightness determination circuit (23) is constituted by this brightness determination analog circuit and the brightness determination logic circuit. As shown in FIG. 8, the operational amplifier (43) outputs an output v43=Vref-(DOS-AGCOS) corresponding to the amount of light, and a comparator (45) which is a brightness determination means
is input to the negative input of When determining the integration time, φd is applied as shown in FIG. 9, and the PET (49) of the reference voltage generation circuit (RVC) is turned on.
The positive input of the comparator (45) is (Vref-V
th) is input. Now, when the SH pulse occurs, latch 1 (73) and latch 2 (74) in Figure 1θ
, latch 3 (75) are all reset. after that,
As shown in FIG. 9, when the φC pulse is generated, the FET (48) in FIG. 8 is turned on, and the comparator (45)
(Vref-Vth/2) is input to the plus input of. Here, if DO3-AGCOS)>Vth
/2, the output VFLG of the comparator (45) is “I
]”, and the AND gate (
70) becomes "■(", and latch 1 (73) is set. After that, as shown in FIG. 9, when the φb pulse is generated, PET (47) in FIG. 8 is turned on, and the comparator The positive manpower of (45) is (V ref
-V th/4 ) is input. Here, if DO8-AGCOS)>Vth/4, the output VFLG of the comparator (45) is “H”.
”, and in FIG. 1O, the output of the AND gate (7I) becomes “H” and the latch 2 (74) is set.Furthermore, as shown in FIG. The FET (46) in Figure 8 is turned on, and the positive input of the comparator (45) has (V rer-V
th/8) is input. Here, (DO9-A
GCOS)>Vth/8, the output VFLG of the comparator (45) is “I
-1", the output of the AND gate (72) shown in FIG. 10 becomes "I", and latch 3 (75) is set. For each of the above cases, Gl , G3 signals are generated.Based on this signal, the gains are selected as shown in the table below, and the V
os is obtained.

In this way, by sequentially turning on the FETs (49, 48, 47, 46), the reference voltage generation circuit (RVC)
generates multiple reference voltages, one comparator (45) can judge the brightness at multiple stages, and the image sensor (
13) The number of comparators formed on the same chip can be reduced.

The FET (44) shown in Figure 8 is in INT mode and DD mode.
This is a switch for supplying power to the resistance divider circuit, that is, the reference voltage generation circuit (RVC) only in the I mode.

This PET (44) allows the reference voltage generation circuit (RV
C) is energized only when brightness determination is necessary, reducing current consumption. This saving effect on current consumption becomes greater at high brightness because the integration time becomes shorter than the readout time.

As shown in FIG. 11, the signal V os'
), a capacitor (62), and a buffer (64).
It is input to the minus input of (65). This signal Vos
' is held by the signal processing timing generator (21
) to φ1-“L” and φ2-“H” by the OSS/I] pulse signal generated at the timing of signal charge transfer. In addition, the signal Vos' is generated by a sample-and-hold circuit (2) consisting of an FET (59), a capacitor (61), and a buffer (63).This sample-and-hold circuit uses the AQ light-shielded black reference shown in Figure 1. Sample and hold the pixel output.The pulse that provides the sample and hold timing is OBS/1-1 shown in Figure 12.
signal, which is generated in the sequence shown below.

As shown in FIG. 2.12, after shifting from the INT mode to the DDI mode, the ADS signal that provides the timing to start A/D conversion appears in the ADT signal. The microcomputer (14) measures the timing of sampling and holding the black reference pixel output while monitoring this signal. The microcomputer (I4) outputs N B +=“H”, NB,=“H” while outputting the black reference pixel,
The signal processing timing generator (21) thereby
BS/I (Signal is set to "I-1". Subsequently, the microcomputer (I4) outputs NI3° - "L" and NBt = "H" until the next ADS signal rises, and the signal processing timing is generated. Part (21) is thereby O[3S
/H signal is set to “OFF”. As described above, FIG. 11 shows the FET (59), capacitor (61), buffer (63).
) makes the input black reference pixel output bold and inputs it to the negative terminal of operational amplifier 2 (65). After sampling and holding the black reference pixel output, the output of operational amplifier 2 (65) is subtracted by the amount corresponding to the held black reference pixel output, and the output of the FET (
66) to G3. connected to the gates of (68). It is amplified by the gain determined by the G4 signal (distinction table 11) and output as a signal Vos (FIG. 12).

As described above, the output signal O8 of the image sensor (13) is double sampled in the AGC differential amplifier circuit (25) and the OB subtraction AGC differential amplifier circuit (26), the reset level is subtracted from the signal level, and the reset level is subtracted from the signal level. A signal without the influence of noise is extracted, and the black reference level is further subtracted from the signal without the influence of reset noise, resulting in an output Vos in which the dark output is removed from the output of each pixel.
is obtained. Furthermore, this output Vos is applied to the AGC differential amplifier circuit (
25) and the OB subtraction AGC differential amplifier circuit (26), a gain of x8 to x64 is applied, as described later, according to the average level of each pixel output. In this way, since the two amplifier circuits (25, 26) perform two-stage amplification, the range of resistance values connected to the operational amplifier (54, 64) can be smaller than when amplifying with one amplifier circuit. , the area occupied by the resistor becomes smaller.

Next, the gain of the operational amplifier (54) of the AGC differential amplifier circuit (25) and the gain of the operational amplifier (65) of the OB subtraction AGC differential amplifier circuit (26) shown in FIG. 1t will be described. Here, for the output OS of the image sensor (13), x8. I16. In order to switch the gain of I32゜I64, operational amplifier 1 (54) has two stages, operational amplifier 2
(65) performs two-stage gain switching. In this case, the operational amplifiers (54) and (65) always have an offset problem. When applying gain in two stages, the first stage gain is GNI, the second stage gain is GN2,
If the offset of each operational amplifier is ΔV, the input is Vi, and the output is Vo, the output is expressed by the following formula.

V o-((Vi + △V) X GNI+△V)
X GN2=vixGN1xGN2+△V ・(GNI
X GN2 + GN2)-(Vi+△V) x G
NI x GN2 + △VxGN If the total gain GNIXGN2 of the 22-stage operational amplifier does not change,
The offset due to GN2 appears in the second term (ΔVXGN2) of the above equation.

That is, the smaller GN2 is, the smaller the total offset will be.

Therefore, the first stage gain GNI is the second stage gain GN2.
The offset can be suppressed by choosing higher than , but even with this measure the offset remains. For this reason,
As shown in Fig. 11, the operational amplifier 2 (65) in the latter stage performs a level shift based on a voltage that is one diode (99) which is a bias means from the reference voltage Vrer, so A/D conversion is always possible. In this way, the offset is made to appear on the lower voltage side than the reference voltage V ref.

After sampling and holding the signal representing the black reference pixel, the OB subtraction AGC differential amplifier circuit (26) receives a signal representing the second black reference pixel subjected to AI2 light shielding, before outputting the signal representing the effective pixel. is outputting. Since the previously held black reference pixel is subtracted from the output representing the second black reference pixel, an output matching the reference voltage Vref is obtained if there is no offset of the operational amplifier. However, since the output of the operational amplifier 2 (65) always has an offset Voffset on the lower voltage side than the reference voltage Vref, the output becomes (Vrer-Vorfset). This is A
When /D conversion is performed, a signal corresponding to Vofrset is obtained as digital data. Thereafter, the output of the effective pixel is subtracted by this Vofrset by the calculation of the microcomputer (14).
The data manually entered in I4) is substantially the same as the data with the offset component removed.

Next, the DD2 mode will be explained.

In the DD2 mode, the image sensor (I3) is not caused to perform any active operation.

For this reason, the NBr connected to the I10 buffer (22)
, NB, outputs a G1 signal to NB, a G3 signal to NBt, and notifies the microcomputer (14) of the gain information of the output of the image sensor (13). This +10 switching is performed by the DD2 signal.

Only in the DD2 mode, the signal output as Vout is the output Vos of the image sensor (13).

The pixels used in this system are image sensors (13)
are pixels detected in two separate regions of
No photodiode (PD) is provided between the two regions. When outputting the output of these pixels as Vout to the A/D converter (15), there are problems that will be described later, so by switching between DD2 mode and DD1 mode,
Vos is output as Vout only when valid pixels are output. The output Vos' of the AGC differential amplifier circuit (25) is the output component Vo corresponding to the optical signal when the effective pixel is output.
s' (sig) and the dark output component V os' (dark
) expressed as the sum of (V os' −V os'
(sig) + Vos' (dark)). OB
V os' (d
ark) is subtracted, and Vos= V ref −G N 2 X (Vos'
-Vos' (dark)) as the A/D converter (!
5) is output.

At this time, the output of the pixel from which the photodiode (PD) has been removed becomes Vos'-0 because there is no output corresponding to the optical signal and no dark output component. Here, when Vos' (dark) is subtracted by the OB subtraction AGC differential amplification (26), Vos=Vref-GN2 x(o-Vos'(dark)
k))>Vrer, and the reference voltage V that can be A/D converted
Contrary to the lower voltage side than ref, Vos is the reference voltage Vr
The voltage becomes higher than ef, exceeding the dynamic range of A/D conversion, and there is a possibility that the A/D conversion device, that is, the A/D conversion section (15) may be destroyed. For this reason, the analog switch (28), (
29) to constantly output a temperature detection output VTMP that can be converted into an A/D converter. like this? Here, only when outputting a valid pixel, output Vos by setting DD2="■]', and when outputting an invalid pixel, set VTM as DD2-"I7".
By outputting P, A/D conversion is always performed within the dynamic range of A/D conversion.

This concludes the explanation of the DD2 mode and the explanation of the first embodiment.

Next, a second embodiment will be described in which the means for removing the dark output component in the first embodiment described in Section 1 is modified. Here, only the differences from the first embodiment will be explained with reference to the block diagram in FIG. 14 and the circuit diagram of the AGC differential amplifier circuit in FIG. 15.

First, the block diagram of FIG. 14 showing the second embodiment and the block diagram of FIG.
As shown by the differences in the block diagram of FIG. 2 illustrating an embodiment of the analog reference voltage V re
The difference from the first embodiment is that "f" is output from the AGC differential amplifier circuit (+25). Also, in FIG. 14, the OB subtraction AGC differential amplifier circuit in the first embodiment is removed. There is.

The operation of the second embodiment will be explained with reference to FIG. As in the first embodiment, prior to outputting the effective pixels, the image sensor (13) outputs the dark output, that is, the output of the black reference pixel.Here, the FE in the AGC differential amplifier circuit (125)
T (159), capacitor (161) and buffer (
163), which is a holding means, samples and holds the output of the black reference pixel using the OBS/H pulse. In the first embodiment, the held output is connected to the negative power of operational amplifier 2 (65),
Subtraction was performed in the operational amplifier 2 (65), but in the second embodiment, the held output is output as V ref'. This V rer' is the A/D converter (1
15) as an analog reference voltage, and the A/D converter (115) A/D converts the input voltage using this voltage as a reference. That is, since the difference between the input Vout and the reference voltage V ref' is taken and converted into a digital value, this is equivalent to subtracting the black reference pixel output within the A/D converter (115).

Therefore, the problem of operational amplifier offset that occurs when the operational amplifier subtracts the black reference pixel output from the effective pixel output, shifts the level, and uses this as a reference voltage for the A/D conversion section does not occur in this embodiment.

In addition, the output of the black reference pixel, which is sampled and held by the sample-and-hold circuit consisting of the FET (160), the capacitor (162), and the buffer (164), and the output of each effective pixel are the outputs of the operational amplifier 2 (165). Since these differentials are taken within the A/D converter (115), the offset of operational amplifier 2 (165) is completely removed. Therefore, in the second embodiment, the dark output of the image sensor (13) is removed and the operational amplifier 2 (16) is removed simultaneously.
5) Offset removal is performed.

Next, a third embodiment will be described with reference to FIGS. 16, 17, and 18. This third embodiment differs from the first and second embodiments in the dark output removal means.

First, let us look at the block diagram of the third embodiment (Fig. 16) and the block diagram of the first embodiment.
Differences from the block diagram of the embodiment (FIG. 2) will be described.

In the third embodiment, the sample and hold pulse OBS/H of the black reference pixel is applied to an A/D converter, that is, an A/D converter (
215), and the OB subtraction AGC differential amplifier circuit is removed. In this third embodiment, subtraction of the black reference pixel is performed within the A/D converter (215). 1st
FIG. 8 shows an A/D conversion section (215), which includes an A/D conversion circuit (206) and an internal circuit provided on the same chip. V in Figure 18
The output of the image sensor input manually as "in" consists of the output of a black reference pixel and the subsequent effective pixels. The output of the black reference pixel is sampled and held by a sample and hold circuit consisting of an FET (20), a capacitor (202), and a buffer (203) using the OBS/I-1 pulse.Then, the effective pixel output input thereafter is subtracted. After the sampled and held black reference pixel output is subtracted by the operational amplifier (205), which is the means, the A/D conversion circuit (205)
06).

In this way, the operational amplifier (205) calculates the difference between the effective pixel output and the black reference pixel output and converts it into A/D, reducing the processing on the image sensor (13) side and simplifying the circuit configuration. .

FIG. 17 shows an AGC differential amplifier circuit (225).

In the first embodiment, there was a sample and hold circuit for the output of the black reference pixel, but in the third embodiment, this is removed. Further, as in the second embodiment, since the black reference pixel output and the effective pixel output are output from the same operational amplifier (165), the offset of this operational amplifier (165) is completely canceled.

Next, a fourth example in which the dark time output removing means is different from the above-mentioned embodiment.
An example will be explained. FIG. 19 is a hardware block diagram according to the fourth embodiment. This is different from FIG. 16, which is a block diagram of the third embodiment, when the reference voltage V re
The difference is that f is not input to the A/D converter (315), and the AGC differential amplifier circuit (225) has exactly the same configuration as the third embodiment.

FIG. 20 shows the A/D converter (315), and this A/D converter (315)
The conversion section (315) includes an A/D conversion circuit (405) and an internal circuit provided on the same chip. While the image sensor (13) is outputting the black reference pixel,
The OBS/H pulse is given to the /D converter (315), and the output of the black reference pixel input to the terminal Vin is FE.
T (401), capacitor (402), buffer (40
Sample and hold the sample and hold circuit consisting of 3). The held black reference pixel output is input to the A/D conversion circuit (405) as an analog reference voltage (V ref"). From then on, the effective pixel output of the image sensor (13) input to the terminal Vin is: Second
As in the embodiment, the output of the held black reference pixel (V
re4') is subtracted and then A/D converted. This removes the dark output component.

As described above, in this fourth embodiment, the black reference pixel output is sampled and held, and the black reference pixel output is used as the analog reference voltage (V ref') to be applied to the A/D conversion circuit (405).
) performs A/D conversion, an operational amplifier for level-shifting the black reference pixel output to the reference voltage is not required, and furthermore, the level shift offset becomes zero.

<Effects of the Invention> As is clear from the above, according to the present invention, in the photoelectric conversion means, portions corresponding to some or all of the pixels that are unnecessary in the system are removed, and at least one portion is added to the removed portion. Since two circuits are inserted, it is possible to effectively utilize the portion corresponding to the invalid pixel which is not used in the system, the overall area of the chip of the solid-state imaging device can be reduced, and a high-density configuration can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the image sensor in the solid-state imaging device of the present invention, FIG. 2 is a block diagram of the fixed imaging device of the first embodiment of the invention, and FIG. 3 shows the potential structure of the image sensor at the time of initialization. 4 is a time chart of the signal in the initialization mode of the first embodiment, FIG. 5 is a diagram showing the potential structure of the image sensor in the integral mode, and FIG. 6 is a time chart of the signal in the integral mode. Fig. 7 is a structural diagram of a compensation diode, Fig. 8 is a circuit diagram of a luminance judgment analog circuit, Fig. 9 is a time chart of signals during luminance judgment,
FIG. 10 is a circuit diagram of the brightness determination logic circuit, FIG. 11 is a circuit diagram of the ACC differential amplifier circuit and the OB subtraction AGC differential amplifier circuit in the first embodiment, FIG. 12 is a time chart regarding pixel output processing, and FIG. The figure is a circuit diagram of the temperature detection section, Figure 14 is a block diagram of the solid-state imaging device of the second embodiment, Figure 15 is a circuit diagram of the AGC operational amplifier circuit of the second embodiment, and Figure 16 is the third embodiment. 17 is a circuit diagram of the AGC operational amplifier circuit of the third embodiment, FIG. 18 is a circuit diagram of the A/D conversion section, and FIG. 19 is a block diagram of the solid-state imaging device of the fourth embodiment. 20 is a circuit diagram of the A/D conversion section of the fourth embodiment, FIG. 21 is a structural diagram of the image sensor, and FIG. 22 is a time chart of signals in the integration mode of the fourth embodiment. FIG. 23 is a diagram explaining the transfer of dark charges, and FIG. 24 is a diagram showing a truth table of the brightness determination logic circuit. FD...Photodiode, BG...Barrier gate, ST...Storage section, SH...Shift gate, RG...
...Transfer register, RG I CG... Integral clear gate, 14... Microcomputer, 20... Integral time control section, 23... Mode selection circuit, 24...
Brightness determination circuit, 30... transfer lock generation section. Patent applicant: Minolta Camera Co., Ltd. Agent: Patent attorney: Qingbai Zhong and 2 others Figure 3 (a) Zhou Takumiao Lb Figure 7 Zhou Bao Chang La LO Xue'7.7Lb

Claims (3)

[Claims] (1) A photoelectric conversion means having a large number of pixels and generating charges corresponding to the amount of light incident on each pixel, a transfer register for transferring the charges generated to the photoelectric conversion means, and the photoelectric conversion means; In a solid-state imaging device equipped with a gate provided between a transfer register, the photoelectric conversion means has a portion corresponding to some or all of the pixels unnecessary for the system removed, and at least A solid-state imaging device characterized in that one circuit is inserted. (2) The solid-state imaging device according to claim 1, wherein the circuit is a brightness determination circuit that determines brightness based on the charge generated in the brightness monitor means. (3) The solid-state imaging device according to claim 1, wherein the photoelectric conversion means has a central portion removed.