JP2009278149A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device for removing noise from a pixel signal by using a same correlated double sampling means in both continuous mode and reset mode. <P>SOLUTION: The solid-state imaging device 1 includes an imaging part 90 and a reset circuit 10, and includes dummy pixels 6, 7 which are not provided with a function for receiving incident light. In the reset mode, the correlated double sampling circuits 8, 9 carry out correlated double sampling based on photo charge voltages and reset voltages read from pixels 2-5. In the continuous mode, the correlated double sampling circuits 8, 9 carry out the correlated double sampling based on photo charge voltages read from the pixels 2-5 and reference voltages read from the dummy pixels 6, 7. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a correlated double sampling technique in a solid-state imaging device.

  For example, a solid-state imaging device that is mounted on a vehicle and detects white lines or objects in front of the road needs to capture images throughout the day and night or in a tunnel, so it can detect subjects with stable sensitivity without being affected by light and dark. A possible performance, that is, a wide dynamic range is required. Patent Documents 1 and 2 describe a solid-state imaging device having such a wide dynamic range.

  In the solid-state imaging device disclosed in Patent Document 1, a photodiode and a MOS transistor are used, and a minute current (drain current) called a subthreshold current flows through the transistor by setting the gate voltage of the transistor to a threshold voltage or less. Like that. By utilizing the fact that this current is an exponential function of the gate-source voltage, the current corresponding to the amount of incident light is logarithmically converted to a voltage, thereby realizing a wide dynamic range.

  In the optical sensor circuit described in Patent Document 2, after detecting an optical signal, the gate voltage of the n-channel MOS transistor is set to a high value for a predetermined time, or the gate voltage of the p-channel MOS transistor is decreased for a predetermined time. Set to value. This reduces the impedance between the drain and source and controls the charging or discharging of the capacitor connected to the detection terminal to prevent the occurrence of afterimages and to obtain a wide dynamic range with high sensitivity. Yes.

  By the way, there are two types of pixels (pixels) that constitute the imaging unit of the solid-state imaging device: linear conversion type and logarithmic conversion type.

  The linear conversion type pixel operates on the principle that a photocurrent flowing through a photodiode is accumulated in a capacitor connected in parallel to the photodiode, and a potential generated as a result is read out. In this case, the potential changes linearly with respect to time. That is, the potential to be read is always in an unsteady state, and the reference potential level between pixels matches unless the initial value of the potential in at least one frame and the readout time (photo charge accumulation time) are the same between pixels. The normal image cannot be played back. For this reason, a reset operation for providing a constant voltage (reset voltage) as an initial value is essential.

  On the other hand, as shown in Patent Documents 1 and 2, the logarithmic conversion type pixel has a potential at which the photocurrent flowing through the photodiode and the subthreshold current flowing through the MOS transistor connected in series with the photodiode are balanced. It operates on the principle of reading. Therefore, there is no concept of initial value or photocharge accumulation time. That is, the read potential does not change with time. For this reason, the reset operation like the linear conversion type pixel is not essential.

  As described above, in the case of a linear conversion type pixel, a correct potential cannot be read from the pixel unless an initial state is given, and therefore, only a method of applying a reset can be performed. On the other hand, in the case of a logarithmic conversion type pixel, a correct potential can be read from the pixel without resetting in a subject whose illuminance is higher than a certain value, so it can be used without resetting and used with resetting. It is also possible. In the following, a method for applying reset is referred to as “reset mode”, and a method for not performing reset is referred to as “continuous mode”.

  In a linear conversion type image sensor, a correlated double sampling (CDS) method is used as means for removing noise generated in pixels. Due to variations in the characteristics of elements constituting the pixel, the output voltage of the pixel before resetting and the output voltage of the pixel at resetting each include a noise component. In correlated double sampling, the noise component is canceled by calculating the difference between these output voltages. Patent Documents 3 and 4 disclose such a correlated double sampling technique.

  On the other hand, the logarithmic conversion type image sensor can operate in the continuous mode or the reset mode as described above, but normally only one of the modes is used. However, when switching between continuous mode and reset mode for each frame (for example, while maintaining sensitivity to a dark subject, a clear image can be obtained even if the frame position is changed continuously) In the reset mode, noise can be removed by correlated double sampling in the same way as the linear conversion type. However, the reset mode cannot be read out in the continuous mode, so the reset voltage cannot be read. Similar correlated double sampling cannot be performed.

Japanese Patent Laid-Open No. 3-192864 Japanese Patent Laid-Open No. 10-90058 JP-A 63-765883 JP-A-1-243675

  An object of the present invention is to provide a solid-state imaging device capable of removing noise from a pixel signal using the same correlated double sampling means in both the continuous mode and the reset mode.

  The present invention has a light receiving element that converts incident light into a current, and a MOS transistor that operates in a subthreshold region by applying a gate voltage that is equal to or lower than a threshold voltage and outputs a voltage obtained by logarithmically converting the current of the light receiving element. An image pickup unit including a plurality of first pixels, and an output voltage of the first pixel is reset to an initial value by applying a gate voltage exceeding a threshold voltage to the MOS transistor and a MOS transistor. In a solid-state imaging device having a reset circuit, correlated double sampling is performed based on output voltages of a second pixel that does not have a function of receiving incident light and the first and second pixels, and an image signal is output Correlated double sampling means. When the correlated double sampling means resets after reading the output voltage of the first pixel (reset mode), the output voltage of the first pixel before resetting and the first voltage at the time of resetting are reset. Correlated double sampling is performed based on the difference from the output voltage of the pixel. When the correlated double sampling means does not reset after reading the output voltage of the first pixel (continuous mode), the output voltage of the first pixel, the output voltage of the second pixel, Correlated double sampling is performed based on the difference between the two.

  In this manner, in the reset mode in which the reset is performed, the correlated double sampling is performed on the two voltages that are read out from the first pixel and are temporally shifted as usual. On the other hand, in the continuous mode that does not require resetting, correlated double sampling is performed on the voltage read from the first pixel and the voltage read from the second pixel. For this reason, in the continuous mode, even if the reset voltage cannot be read, the output voltage of the second pixel is read and used instead of the reset voltage, so that correlated double sampling is performed and the noise is reduced. The removed image signal can be taken out.

  In the present invention, a configuration may be adopted in which one second pixel is provided corresponding to a predetermined number of first pixels, and each of these pixels is connected to a common output signal line. According to this, in the continuous mode, a voltage for correlated double sampling is generated in common by one second pixel for a predetermined number of first pixels, so the number of second pixels It is possible to simplify the configuration by reducing the number.

  According to the solid-state imaging device of the present invention, when the reset mode and the continuous mode coexist, correlated double sampling is performed using the same correlated double sampling means in any mode, and noise is generated from the image signal. Can be removed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit block diagram of a solid-state imaging device according to the present invention. The solid-state imaging device 1 includes an imaging unit 90, a reset circuit 10, dummy pixels 6 and 7, and correlated double sampling circuits 8 and 9. The imaging unit 90 includes a plurality of pixels 2 to 5 (first pixels) arranged in a matrix. In order to simplify the description, the imaging unit 90 is a 2 × 2 matrix here. As will be described later, each pixel includes a photodiode that converts incident light into a current, and a MOS transistor that converts the current into a voltage. The reset circuit 10 applies a voltage exceeding the threshold voltage to each of the pixels 2 to 5 during the reset operation, and resets the output voltage of the pixel to an initial value. The dummy pixels 6 and 7 (second pixels) are pixels that do not have a function of receiving incident light, and have MOS transistors as will be described later. The correlated double sampling circuits 8 and 9 perform correlated double sampling based on the output voltages of the pixels 2 to 5 and the dummy pixels 6 and 7 and output an image signal from which noise has been removed. The dummy pixels 6 and 7 and the correlated double sampling circuits 8 and 9 are provided for one row. Note that a decoder or the like that selects a pixel based on an address signal is not shown.

  To each of the pixels 2 to 5, reset signal lines 11 and 21 in the row direction, readout signal lines 12 and 22, voltage supply lines 13 and 23, and output signal lines 41 and 42 in the column direction are connected. The reset circuit 10 outputs a voltage exceeding the above-described threshold voltage to the reset signal lines 11 and 21 as a reset signal. A control signal line 31, a read signal line 32, and output signal lines 41 and 42 are connected to the dummy pixels 6 and 7. Output signal lines 41, 42, control signal lines 51, 52, 53 and output signal lines 61, 62 are connected to the correlated double sampling circuits 8, 9.

  In the present embodiment, one dummy pixel 6 is provided corresponding to a plurality of pixels 2, 4 in the same column, and these pixels 2, 4, 6 are connected to a common output signal line 41. One dummy pixel 7 is provided corresponding to the plurality of pixels 3, 5 in the same column, and these pixels 3, 5, 7 are connected to a common output signal line 42.

  FIG. 2 is a circuit diagram of one pixel (unit pixel). Here, the configuration of the pixel 2 will be described, but the configurations of the other pixels 3 to 5 are the same. The pixel 2 includes MOS transistors (hereinafter simply referred to as transistors) Tr1, Tr2, Tr3, and a photodiode PD. The drain of the transistor Tr1 is connected to the voltage supply line 13 in FIG. 1, and the gate is connected to the reset signal line 11. The source of the transistor Tr1 is connected to the cathode of the photodiode PD. The anode of the photodiode PD is connected to the ground. The gate of the transistor Tr2 is connected to the cathode of the photodiode PD, and the source is connected to the drain of the transistor Tr3. The power supply VDD is supplied to the drain of the transistor Tr2. The source of the transistor Tr3 is connected to the output signal line 41, and the gate is connected to the read signal line 12.

  The pixel 2 is a logarithmic conversion type pixel and has a wider dynamic range than the linear conversion type pixel. A photocurrent corresponding to the amount of incident light flows through the photodiode PD as a light receiving element. At this time, if the gate voltage of the transistor Tr1, which is a voltage conversion element, is set to be equal to or lower than the threshold voltage, the transistor Tr1 operates in a subthreshold region where the drain-source has a high impedance, and the transistor Tr1 has the same photocurrent. An amount of subthreshold current flows. Thereby, the potential V of the cathode of the photodiode PD is stabilized at a potential corresponding to the photocurrent. The cathode potential V is a potential obtained by logarithmically converting the photocurrent. The cathode potential V is amplified by the transistor Tr2. When the transistor Tr <b> 3 is turned on by the read signal applied to the read signal line 12, a voltage corresponding to the amount of incident light is output to the output signal line 41.

  On the other hand, when a voltage exceeding the threshold voltage, that is, a reset signal is applied to the gate of the transistor Tr1, the transistor Tr1 operates in a saturation region where the drain-source impedance is low. For this reason, regardless of the amount of incident light of the photodiode PD, the potential V of the cathode of the photodiode PD becomes substantially equal to the potential of the voltage supply line 13 and is fixed to this value. Therefore, the voltage output to the output signal line 41 at this time becomes a constant value, and this voltage becomes the initial voltage of the pixel in one frame, that is, the reset voltage.

  FIG. 3 is a circuit diagram of a dummy pixel. Although the configuration of the dummy pixel 6 is described here, the configuration of the dummy pixel 7 is the same. The dummy pixel 6 includes MOS transistors (hereinafter simply referred to as transistors) Tr4 and Tr5. The power supply VDD is supplied to the drain of the transistor Tr4. The gate of the transistor Tr4 is connected to the control signal line 31. The source of the transistor Tr4 is connected to the drain of the transistor Tr5. The gate of the transistor Tr5 is connected to the read signal line 32, and the source is connected to the output signal line 41.

  When a read signal is supplied from the read signal line 32 to the gate of the transistor Tr5 while a high level signal is applied from the control signal line 31 to the gate of the transistor Tr4, the output signal line 41 is passed through the transistors Tr4 and Tr5. , A voltage substantially equal to VDD is output. This voltage is given as a reference voltage to the correlated double sampling circuit 8 connected to the output signal line 41.

  FIG. 4 is a circuit diagram of a correlated double sampling circuit. Although the configuration of the correlated double sampling circuit 8 will be described here, the configuration of the correlated double sampling circuit 9 is the same. The correlated double sampling circuit 8 includes MOS transistors (hereinafter simply referred to as transistors) Tr6 to Tr9, capacitors C1 and C2, and a differential operational amplifier (hereinafter referred to as an operational amplifier) OP. The gate of the transistor Tr6 is connected to the control signal line 51, and the gate of the transistor Tr7 is connected to the control signal line 52. The drain of the transistor Tr6 and the drain of the transistor Tr7 are connected, and the connection point is connected to the output signal line 41.

  The source of the transistor Tr6 is connected to the drain of the transistor Tr8, and one end of a sample and hold capacitor C1 is connected to the connection point. The other end of the capacitor C1 is connected to the ground. The source of the transistor Tr7 is connected to the drain of the transistor Tr9, and one end of a sample and hold capacitor C2 is connected to the connection point. The other end of the capacitor C2 is connected to the ground. The gate of the transistor Tr8 is connected to the gate of the transistor Tr9, and the connection point is connected to the control signal line 53.

  The source of the transistor Tr8 is connected to the positive input terminal of the operational amplifier OP, and the source of the transistor Tr9 is connected to the negative input terminal of the operational amplifier OP. The output terminal of the operational amplifier OP is connected to the output signal line 61. The operation of the correlated double sampling circuit 8 will be described later.

  FIG. 5 is a timing chart of main signals in the reset mode. Here, the signals of the signal lines 21, 22, 51 to 53 (FIG. 1) are shown. In the following description, the pixels 4 and 5 are described, but the signal lines 11 and 12 and the pixels 2 and 3 are also described. The operation is similar.

  At time t1, when the previous reset operation is completed and the reset signal a from the reset circuit 10 is stopped, the reset signal line 21 is changed from the high level to the low level. Then, at time t2 after the elapse of time T from time t1, the reset signal b is output again from the reset circuit 10, and the reset signal line 21 changes from low level to high level. A period from time t1 to time t2 (time T) is an accumulation time of charges (photocharge) photoelectrically converted by the photodiode PD.

  Immediately before the time t2 when the reset is performed, the read signal c is given to the read signal line 22, and the output voltage (photocharge voltage) based on the photocharge of the pixels 4 and 5 is read. At the same timing, the control signal d is given to the control signal line 51, and the transistors Tr6 (FIG. 4) of the correlated double sampling circuits 8 and 9 are turned on. As a result, the photocharge voltage read from the pixels 4 and 5 is held in the sample and hold capacitor C1 of the correlated double sampling circuits 8 and 9.

  Next, at time t3, when the reset operation is completed and the reset signal b from the reset circuit 10 is stopped, the reset signal line 21 is changed from the high level to the low level. Immediately before time t3, a read signal e is given to the read signal line 22, and an output voltage (reset voltage) based on reset of the pixels 4 and 5 is read. At the same timing, the control signal f is given to the control signal line 52, and the transistors Tr7 (FIG. 4) of the correlated double sampling circuits 8 and 9 are turned on. As a result, the reset voltage read from the pixels 4 and 5 is held in the sample and hold capacitor C2 of the correlated double sampling circuits 8 and 9. At time t3, the control signal g is supplied to the control signal line 53, and the control signal line 53 changes from the low level to the high level. As a result, the transistors Tr8 and Tr9 of the correlated double sampling circuits 8 and 9 are turned on, and the operational amplifier OP has the charge accumulated in the capacitor C1 (photo charge voltage) and the charge accumulated in the capacitor C2 (reset voltage). The difference between and is calculated. This difference is output to the output signal lines 61 and 62 as an image signal.

  In the reset mode as described above, the read signal lines 32 of the dummy pixels 6 and 7 are always kept at a low level.

  FIG. 6 is a diagram showing a read route of the photocharge voltage in the reset mode, and corresponds to reading by the read signal c in FIG. As indicated by thick arrows, the photocharge voltage Vp is transferred from the pixels 4 and 5 to the correlated double sampling circuits 8 and 9 via the output signal lines 41 and 42.

  FIG. 7 is a diagram showing a read route of the reset voltage in the reset mode, and corresponds to reading by the read signal e in FIG. As indicated by thick arrows, the reset voltage Vr is transferred from the pixels 4 and 5 to the correlated double sampling circuits 8 and 9 via the output signal lines 41 and 42.

  Thus, in the reset mode, the correlated double sampling circuits 8 and 9 normally output the output voltage (photocharge voltage Vp) of the pixels 4 and 5 before resetting, and the output voltage of the pixels 4 and 5 at the time of reset, as usual. Correlated double sampling is performed based on the difference from (reset voltage Vr), and an image signal from which noise has been removed is output.

  Next, the operation in the continuous mode will be described. FIG. 8 is a timing chart of main signals in the continuous mode. Here, the signals of the signal lines 21, 22, 51 to 53, and 32 (FIG. 1) are shown. In the following description, the pixels 4 and 5 will be described. The operation is the same as for.

  Since reset is not applied in the continuous mode, the reset signal line 21 always maintains a low level state. Further, the photocharge voltage of the pixels 4 and 5 can be read out at any timing. In FIG. 8, immediately before time t4, a read signal h is applied to the read signal line 22, and the photocharge voltages of the pixels 4 and 5 are read. At the same timing, the control signal i is given to the control signal line 51, and the transistors Tr6 (FIG. 4) of the correlated double sampling circuits 8 and 9 are turned on. As a result, the photocharge voltage read from the pixels 4 and 5 is held in the sample and hold capacitor C1 of the correlated double sampling circuits 8 and 9.

  Next, immediately before time t5, the read signal j is given to the read signal line 32, and the output voltage (reference voltage) of the dummy pixel 6 is read. At the same timing, the control signal k is applied to the control signal line 52, and the transistors Tr7 (FIG. 4) of the correlated double sampling circuits 8 and 9 are turned on. As a result, the reference voltage read from the dummy pixel 6 is held in the sample and hold capacitor C2 of the correlated double sampling circuits 8 and 9. At time t5, the control signal m is supplied to the control signal line 53, and the control signal line 53 changes from the low level to the high level. As a result, the transistors Tr8 and Tr9 of the correlated double sampling circuits 8 and 9 become conductive, and the operational amplifier OP has the charge (photo charge voltage) accumulated in the capacitor C1 and the charge (reference voltage) accumulated in the capacitor C2. The difference between and is calculated. This difference is output to the output signal lines 61 and 62 as an image signal.

  FIG. 9 is a diagram showing a read route of the photocharge voltage in the continuous mode, and corresponds to reading by the read signal h in FIG. As indicated by thick arrows, the photocharge voltage Vp is transferred from the pixels 4 and 5 to the correlated double sampling circuits 8 and 9 via the output signal lines 41 and 42. This readout route is the same as the readout route for the photocharge voltage in the reset mode (FIG. 6).

  FIG. 10 is a diagram showing a read route of the reference voltage in the continuous mode, and corresponds to reading by the read signal j in FIG. As indicated by thick arrows, the reference voltage Vf is transferred from the dummy pixels 6 and 7 to the correlated double sampling circuits 8 and 9 via the output signal lines 41 and 42.

  Thus, in the continuous mode, the correlated double sampling circuits 8 and 9 perform correlated double sampling based on the difference between the photocharge voltage Vp of the pixels 4 and 5 and the reference voltage Vf of the dummy pixels 6 and 7. And output an image signal from which noise has been removed.

  As described above, in the above-described embodiment, in the reset mode, the correlated double sampling is performed on the photocharge voltage Vp and the reset voltage Vr that are read out from the pixels 2 to 5 and that are read in time, as usual, In the continuous mode, correlated double sampling is performed on the photocharge voltage Vp read from the pixels 2 to 5 and the reference voltage Vf read from the dummy pixels 6 and 7. Therefore, in the case of the continuous mode, even if the reset voltage cannot be read, the reference voltage Vf of the dummy pixels 6 and 7 is read and used in place of the reset voltage, thereby performing correlated double sampling. An image signal from which noise has been removed can be taken out. Therefore, when the reset mode and the continuous mode coexist, the correlated double sampling is performed using the same correlated double sampling circuits 8 and 9 in any mode, and noise can be removed from the image signal. .

  In the above-described embodiment, one dummy pixel 6 is provided corresponding to the pixels 2 and 4 in the same column, and these are connected to the common output signal line 41 and correspond to the pixels 3 and 5 in the same column. One dummy pixel 7 is provided and connected to a common output signal line 42. For this reason, since the reference voltage in the continuous mode can be generated in common by one dummy pixel for a plurality of pixels, the number of dummy pixels is reduced and the configuration is simplified.

  In the present invention, various embodiments other than those described above can be adopted. For example, in the above embodiment, the dummy pixels are configured by one row, but the number of rows of dummy pixels may be plural. Thereby, the influence by the dispersion | variation in the characteristic of the element which comprises each pixel can be made small. As a configuration of the dummy pixel, the light receiving unit may be shielded from light using the same circuit as the normal pixel.

  Furthermore, processing other than the above embodiment may be added, and the block configuration and circuit configuration of the solid-state imaging device are not limited to the above embodiment.

1 is a circuit block diagram of a solid-state imaging device according to the present invention. It is a circuit diagram of 1 pixel (unit pixel). It is a circuit diagram of a dummy pixel. It is a circuit diagram of a correlated double sampling circuit. It is a timing chart of the main signal in reset mode. It is a figure which shows the read-out route of the photo charge voltage in reset mode. It is a figure which shows the read route of the reset voltage in reset mode. It is a timing chart of the main signal in a continuous mode. It is a figure which shows the read-out route | root of the photocharge voltage in a continuous mode. It is a figure which shows the read-out route | root of the reference voltage in a continuous mode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2-5 Pixel 6, 7 Dummy pixel 8, 9 Correlated double sampling circuit 10 Reset circuit 11, 21 Reset signal line 12, 22 Read signal line 13, 23 Voltage supply line 31 Control signal line 32 Read signal line 41, 42 Output signal line 51, 52, 53 Control signal line 61, 62 Output signal line 90 Imaging unit Tr1 MOS transistor PD Photodiode

Claims (2)

A first light-receiving element that converts incident light into a current, and a MOS transistor that operates in a subthreshold region by applying a gate voltage equal to or lower than a threshold voltage and outputs a voltage obtained by logarithmically converting the current of the light-receiving element. An imaging unit including a plurality of pixels, and these pixels are arranged in a matrix;
In a solid-state imaging device comprising: a reset circuit that resets an output voltage of the first pixel to an initial value by applying a gate voltage exceeding the threshold voltage to the MOS transistor;
A second pixel having no function of receiving incident light;
Correlated double sampling means for performing correlated double sampling based on the output voltages of the first and second pixels and outputting an image signal;
The correlated double sampling means includes
When the reset is performed after reading the output voltage of the first pixel, the correlation is based on the difference between the output voltage of the first pixel before the reset and the output voltage of the first pixel at the time of reset. Do double sampling,
When the reset is not performed after the output voltage of the first pixel is read, correlated double sampling is performed based on the difference between the output voltage of the first pixel and the output voltage of the second pixel. A solid-state imaging device. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein one second pixel is provided corresponding to a predetermined number of first pixels, and each of these pixels is connected to a common output signal line.

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