JPH01205680A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To minimize an area occupied by resistance in a chip by executing an amplification with gains the number of which is obtained by multiplying the gains of a first step amplifying circuit and that of a second step amplifying circuit. CONSTITUTION:The output of a transferring register is amplified by a first step amplifying circuit 25, the gains of which are switched based on the output of a luminance deciding circuit 24, and further, the output of the first step amplifying circuit 26 is amplified by a second step amplifying circuit 26, the gains of which are switched based on the output of the luminance deciding circuit 24. Since a signal to indicate luminance, which is outputted from the transferring register in this manner, is amplified with the two steps of the first step amplifying circuit 25 and the second step amplifying circuit 26, in total, the gains can obtained, the step number of which is the result of multiplying the step number of the gains of the respective steps with one another, the widths of respective resistance values in the respective-step amplifying circuits 25 and 26 can be narrow, and the area of the resistance in the chip of this solid state image pickup device can be minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a solid-state imaging device used in an automatic focus detection device of a camera or the like.

<Prior art> Solid-state imaging devices used in automatic focus detection devices of cameras use a wide brightness range, so the photoelectric output is multiplied by a predetermined gain in an amplifier at low brightness times, so that a predetermined value can be maintained even at low brightness times. It is common to make it possible to obtain a level output. The gain of this amplifier is switched in multiple stages depending on the luminance, so that luminance information at an appropriate level can always be obtained.

Conventionally, such a solid-state imaging device has a photoelectric conversion section that generates charges corresponding to each pixel, an accumulation section that accumulates the charges generated in the photoelectric conversion section, and a storage section that sequentially stores the charges stored in this accumulation section. A transfer register to be transferred, a brightness monitor means for monitoring the amount of light irradiated to the photoelectric conversion section, a brightness determination circuit for determining brightness based on the output of the brightness monitor means, and a plurality of resistors connected thereto are connected by a switch. There is a device that is equipped with an operational amplifier whose gain is adjusted in multiple stages by being switched, and the brightness signal from the transfer register is amplified by the operational amplifier to obtain a brightness signal at an appropriate level (Japanese Patent Application Laid-Open No. 60-125817
Publication No.).

<Problems to be Solved by the Invention> However, in the above-mentioned conventional solid-state imaging device, a plurality of resistors having resistance values corresponding to the number of stages from small resistance values to large resistance values are connected to one operational amplifier, and by switching these resistances. Since the gain is adjusted in multiple stages to obtain a brightness signal at an appropriate level, a number of resistors are required, ranging from small resistance values to large resistance value resistances. There is a problem that the area becomes large.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a solid-state imaging device that can reduce the area occupied by a resistor in an amplifier circuit.

Another object of the present invention is to provide a solid-state imaging device that can reduce the total offset after amplification.

<Means for Solving the Problems> In order to achieve the above object, the solid-state imaging device of the present invention has the following features:
As illustrated in Figure 1.2.11, there is a photoelectric conversion section (PD) that generates charges corresponding to each pixel, and a storage section (ST) that accumulates the charges generated in the photoelectric conversion section (PD).
), a transfer register (RG) that sequentially transfers the charges stored in the storage section (ST), and a transfer register (RG) that generates charges according to the amount of incident light and adjusts the amount of light irradiated to the photoelectric conversion section (PD). A brightness monitor means (9) for monitoring, and an accumulation means (10) for accumulating charges generated in the brightness monitor means (9).
-1), a brightness determination circuit (24) that determines brightness based on the output from the storage means (10-1), and a gain is switched based on the output from the brightness determination circuit (24), A first-stage amplifier circuit (25) that amplifies the output of the transfer register (RG), and a brightness determination circuit (24) that amplifies the output of the transfer register (RG).
), the gain is switched based on the output of the first stage amplifier circuit (25), and a second stage amplifier circuit (26) amplifies the output of the first stage amplifier circuit (25).

Further, it is desirable that the gain of the first stage amplifier circuit (25) is higher than the gain of the second stage amplifier circuit (26).

<Operation> When the photoelectric conversion section (PD) is irradiated with light, a corresponding charge is generated and accumulated in the storage section (ST).

The charges stored in the storage section (ST) are transferred to the transfer register (
RG).

On the other hand, the amount of light irradiated to the photoelectric conversion section (PD) is monitored by a brightness monitor means (9). The charges generated in the brightness monitor means (9) are stored in the storage means (10-1), and based on the output from the storage means (10-1), the brightness determination circuit (24) is connected to the photoelectric conversion unit (PD). Determine the brightness of the light irradiated.

The output of the transfer register (RG) is the brightness determination circuit (2
The output of the first stage amplifier circuit (25) is amplified by a first stage amplifier circuit (25) whose gain is switched based on the output of the brightness determination circuit (24). It is amplified by a second stage amplifier circuit (26) whose gain is switched. In this way, the signal representing the luminance output from the transfer register (RG) is
Since the amplification is performed by two stages, the first stage amplifier circuit (25) and the second stage amplifier circuit (26), each stage amplifier circuit (25,
Even if the number of stages to be switched in 26) is small, it is possible to obtain a total gain equal to the total number of stages multiplied by the number of gain stages in each stage.
The width of the resistance value in 6) can be small, and the area occupied by the resistance on the chip of this solid-state imaging device is reduced.

In addition, when amplifying with these two stage amplifier circuits (25) and (26), if the gain of the first stage amplifier circuit (25) is higher than the gain of the second stage amplifier circuit (26), each stage When there is an offset in the amplifier circuit (25, 26), )・
- Since the total gain is the sum of the gains of each stage, the total offset becomes small.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

First, a first example will be described. FIG. 1 shows the configuration of an image sensor (13) manufactured as a COD.

(1) is a photodiode array consisting of a plurality of photodiodes (FD) as photoelectric conversion means that generate charges according to the amount of incident light, and (ST) is a storage unit that accumulates charges generated by the photodiodes (PD). , (B.G.
) is a field-effect transistor (hereinafter referred to as a field-effect transistor), which is a gate provided between a photodiode (PD) and a storage section (ST).
It is called FET. ), and this barrier gate (BG) connects the photodiode (FD) and the storage section (ST) when voltage is applied, and the photodiode
1" (PD) is caused to flow into the storage section (ST), while when no voltage is applied, the photodiode (
PD) and storage section (ST) are separated, and the photodiode (PD) is separated from the storage section (ST).
The charge generated in PD) stops flowing into the storage section (ST). In addition, (RG) is a transfer register that transfers charge from left to right in the drawing by two-phase drive, and (Sl-[) is a gate provided between the storage section (ST) and the transfer renoster (RG). This is a transfer gate consisting of a FET. This transfer gate (S) () connects the storage section (ST) and transfer register (RG) when voltage is applied, and transfers the charge accumulated in the storage section (ST) to the transfer register (RG), while
When no voltage is applied, the storage section (ST) and transfer register (RG) are separated to prevent charges accumulated in the storage section (ST) from flowing into the transfer register (RG). Further, (RGICG) is an integral clear gate consisting of an FET as a gate. This integral clear gate (RGICG
) connects the transfer register (RG) and overflow drain (ODI) when voltage is applied, and before integration,
Photodiode (FD) and storage section (ST) of each pixel
) is discharged from the transfer register (RG) to the overflow drain-in (ODI). The overflow drain (ODI) is connected to the power supply voltage VDD and has the lowest potential.

On the other hand, an overflow gate (OG) is provided between the photodiode (PD) and the overflow drain (OD2).
No voltage is applied to G), and the potential is always fixed to be lower than the potential of the barrier gate (BG) when no voltage is applied. The charge of each pixel transferred to the transfer register (RG) is transferred to the transfer lock φ1. φ is sequentially transferred to the capacitor (8-1) from the right side in the drawing. The capacitor (8-1) is connected to the FE prior to the charge being transferred.
Charging is reset to the power supply voltage by the osns signal applied to the gate of T(8-3). Then the capacitor (
8-1), the potential decreases from the charging voltage by the transferred charge. The voltage between the terminals of this capacitor (8-1) is taken out as an O8 signal by a buffer (8-2). Although (8-1) has been described here as a capacitor for convenience of explanation, it can be replaced with a PN junction of a diode, and when the circuit is integrated, this capacitor is manufactured as a diode. Hereinafter, the same applies when referring to a capacitor.

A light-shielding Ai2 film (l-1) is placed on the plurality of photodiodes (PDs) at the end of the photodiode array (+).
is provided to extract the black reference pixel output, which will be described later. The above-mentioned photodiode array (+) detects the necessary pixels on the automatic focus detection system using blocks on both sides excluding the central area, so the above-mentioned photodiode array (+)
The area around the center of +) corresponds to unused pixels that are unnecessary for the automatic focus detection system. For this reason, the central photodiode (PD) of the photodiode array (1) corresponding to the unused pixel is removed, and a photodiode (9) for brightness monitoring (to be described later) is installed in this removed portion for output processing. A part of the circuit is inserted (see Figure 21).

Further, in order to control the integration time of the image sensor (13), a brightness monitoring photodiode (9) is provided as brightness monitoring means for monitoring the amount of light incident on the photodiode (PD).

This brightness monitor photodiode (9) has an elongated shape because it is formed across two blocks on both sides of the photodiode array (+) that detects pixels necessary for the automatic focus detection system. In addition, this brightness monitoring photodiode (9) is configured so as not to monitor the amount of light irradiated to the area corresponding to the unused pixel.
The portions corresponding to the unused pixels are shielded from light by an Ag film (9-1). In this way, the brightness monitoring photodiode (9) is arranged with the alignment direction of the photodiode array (+) in the elongated direction, and is configured to straddle the two blocks at both ends of the photodiode array (1). Ag film (9
-1), it is possible to accurately monitor the average output level of the portion corresponding to the used pixel. A part of the circuit for output processing of the brightness monitor photodiode (9) is inserted in the center of the first diode array (1) from which the photodiode (FD) has been removed, as shown in Figure 21. ing.

As mentioned above, the brightness monitoring photodiode (9) has an elongated shape, and when its length is Q and the output is taken out from one end, generally the length a and the response time τ
The relationship τcx: (1" holds true, and the longer the length ρ, the more rapidly the responsiveness deteriorates. Therefore, in order to prevent the responsiveness from deteriorating, the center of the brightness monitoring photodiode (9) is The output is extracted from the nearby extraction electrode.For this reason, the response time is shorter than that of the photodiode (9).
Compared to the case where a contact is provided at the end of the contact point, it is 1/4 as shown in the following equation.

In this way, since the extraction electrode is provided near the center and the response of the brightness monitoring photodiode (9) is fast, even if the integration time is determined based on the output of the brightness monitoring photodiode (9), it will not be excessive. Appropriate integration can be performed without performing excessive integration that stores charges in the storage section (ST).

A capacitor (10-1), which is a storage means, is connected to the brightness monitoring photodiode (9), and prior to the integration of the image sensor (13), an FET (10-3
), the capacitor (10-1) is charged to the power supply voltage VDD. A
After the GCRS signal is removed, the potential at the capacitor (10-1) drops due to charges generated in response to light irradiation. This potential is outputted as an AGCO8 signal via a buffer (10-2) which is an output means.

The compensation diode (11) is provided to remove the dark output of the brightness monitor photodiode (9), and a light-shielding A film (11-1) is provided on top of the compensation diode (11). . This compensation diode (11) is designed to obtain the same amount of output as the dark output of the brightness monitor photodiode (9), but if it has the same structure as the brightness monitor photodiode (9). requires the same area as the brightness monitoring photodiode (9), leading to an increase in chip size. Therefore, as shown in FIG. 7(a), this compensating diode (11) consists of a large number of parts whose N-type parts are separated from each other and arranged at regular intervals, and these are made into P-type parts. By embedding it in the dark area, the length (peripheral length) La of the PN junction on the surface, which is the source of the dark output, is increased, and the same amount of dark output can be achieved with a smaller size than the brightness monitor photodiode (9). It is designed to provide the following.

The above compensation diode (the other is a capacitor (12-1)
is connected to. This capacitor (12-1) is connected to the FET (12-3) before integration of the image sensor (I3).
It is charged to the power supply voltage VDD by the AGCR9 signal applied to the gate of. However, after the AGCR8 signal is removed, the potential of the capacitor (12-1) gradually decreases due to the dark output charge of the compensation diode (11). This potential is output as a DOS signal via a buffer (12-3). This concludes the description of the configuration of the image sensor (13).

Next, the overall 71-ware configuration will be explained along the block diagram of FIG. (14) in the middle of FIG. 2 is a microcomputer (μCom) which is an arithmetic control means for controlling the drive of the image sensor (13). The image sensor control section (16) of this microcomputer (14)
) are two signals MD, , MDt for switching the image sensor (13) between the four modes to be described later, and two signals NB for providing the output and operation timing of MDt.
At the same time, an ADT signal is input from the I10 buffer (22), which is the logical sum of the TINT signal indicating whether integration is completed or not, and the ADS signal indicating the start of A/D conversion of the image sensor output. and gain information Gl.

The G3 signal is input using the NB, , NB, signal line.

The circuit on the left side of the microcomputer (14) is
It is configured on a 1-deep IC. Among these, the above I
The 10 buffer (22) has the following functions: That is,
N B 1. A function of ORing the TINT signal and ADS signal and outputting the result to the microcomputer (14) as an ADT signal. NB When inputting, switch the input/output of the signal line of the signal.

The NB2 signal is input from the microcomputer (14), and at the time of output, the Gl and G3 signals are input to the microcomputer (14).
14), the signal level of the microcomputer (14), the frequency dividing circuit (19), the integration time control section (20), the signal processing timing generation section (21), and the transfer lock generation section (30). ), etc., has an interface function with the signal level in the circuit.

On the other hand, the mode selection circuit (23) is a circuit that decodes the MDl and MDt signals and selects one of the following four modes. M D +-“L”.

In the case of MD t-“L”, the mode selection circuit (23) sets only the INl signal to “H” and selects the INI mode. The INI mode is a mode for initializing the image sensor (13). MD , -“L”, M D
In the case of t-“H”, the mote selection circuit (23) is ■NT
Set only the signal to "H" and select TNT mode. TN
T mode is a mode for performing integration of the image sensor (13). When MD + - “H”, MD = “■4”, the mode selection circuit (23) selects only the DD+ signal as “I(”
and select DD+ mode. DDI mode is a mode to start reading out the image sensor (13),
It is also a mode in which sample and hold of black reference pixels, which will be described later, is performed using the NB, , NBt signals. MD,=“
H", in the case of MD2="L", the mode selection circuit (23)
sets only the DD2 signal to "H" and selects the DD2 mode. In the DD2 mode, the image sensor (13) is read out, and the read and processed output of the image sensor (13) is sent to the microcomputer (14) A/
This is the mode for transmitting to the D converter (15). The operation and functions of each mode will be described later.

The above frequency dividing circuit (19) is a microcomputer (14)
The reference clock CP generated by the clock generator (18) of
The image sensor (13) transfer lock φ3. The clock φ that is the source of φ. At the same time, the integral time control section (20) and the signal processing timing generation section (21) generate a clock φ. A timing clock φ is generated for synchronization with the

The above clock φ. is sent to the transfer lock generation section (30), where S sent from the integral time control section (20)
H times signal RG I CG signal and clock φ.

Accordingly, the clock φ1. φ is used as a transfer lock for the image sensor (13). The integral time control section (20) receives a timing signal N transmitted from the microcomputer (14) when in INI mode or INT mode.
Based on the signals B, , NB, the AGCR8 signal and the BG multiplied signal SH multiplied signal RGICG are generated in synchronization with the clock φ sent from the frequency dividing circuit (19), and the integration start operation is performed. Each of the above signals is transmitted to the image sensor (1) shown in Figure 1.
3) are given to each part. In addition, the integral time control section (20
) is a brightness determination circuit (
Timing signals N B + , N B t that are transmitted when the integration completion signal VFLG from 24) or the DDI signal from the mode selection circuit (23) are "H".
As a result, a BG multiplied signal is generated and the integration is completed.

Furthermore, this integration time control section (20) is configured so that the DDI signal is “
When the timing signal NB is high, the timing signal NB.

NB generates a signal times SH and performs an operation to start reading the output from the storage section (ST). At this time, a signal for obtaining luminance information, which will be described later, an SH multiplied signal, and φa, φb, and φC1φd signals are transmitted to the luminance determination circuit (24). The brightness determination circuit (24) is an image sensor (
13) Monitor the amount of light irradiated to the image sensor (13) by the AGCO9 signal and DO5 signal sent from the
When it is determined that the integral has reached an appropriate level, VF
A function to invert the LG signal and convert the integration to VFLG at low brightness.
If the integration is completed before the signal is inverted, it has a function of determining the level of integration and outputting the Gl, 03 signal for switching the gain of the image sensor (13) according to the determined level.

AGC differential amplifier circuit (25) is an image sensor (!3)
This circuit amplifies the output signal O9 sent from.

In this AGC differential amplifier circuit (25), the FET (8) of the image sensor (13) is turned on by the 0SR9 signal.
-3), the potential O8 immediately after the capacitor (8-I) is charged is sampled and held by the R3S/H signal sent from the signal processing timing generator (21), and then this potential O8 is transferred to the capacitor according to the lock. (8
-1) is transferred to the capacitor (8-1), which has dropped due to the generated charge, and the potential O5 of the capacitor (8-1) is taken, and this is amplified, and the OB subtraction AGC differential which is the subtraction means is used as the signal Vos'. It is output to the amplifier circuit (26).

The gain of this OB subtraction AGC differential amplifier circuit (26) during amplification is switched by the G3 signal output from the brightness determination circuit (24). The above OB subtraction AGC amplifier circuit (2
6), differential amplification between the output of the black reference pixel and the output of the normal pixel without AQ light shielding, that is, the effective pixel, and the output V os
Since the photodiode (PD) always produces a dark output, the pixel detected by the Ai2 light-shielded photodiode (PD) is used as the black reference pixel and is used as the reference for the dark output. pixel, and the value obtained by subtracting the black reference pixel component from the output of the normal pixel is the output of the image sensor (13).The above OB
The Seisan AGC amplifier circuit (26) is an AGC differential amplifier circuit (
Since the output Vos' from 25) is manually input repeatedly in synchronization with the transfer lock, the level of the signal output Vos' of the OSS/HSS/upstream and effective pixels sent from the signal processing timing generator (25) is sampled and held. Also, OBS sent from the signal processing timing generator (21)
/H signal causes the output Vos to change while the black reference pixel is being output.
'Sample and hold.

The OB subtraction AGC amplifier circuit (26) subtracts the sampled and held black reference pixel output level Vos' from the sampled and held valid pixel signal output level Vos',
Furthermore, the signal is multiplied by a gain that is switched by the G3 signal output from the brightness determination circuit (24), and is output as a signal Vos below the analog reference voltage Vref.

The temperature detection section (27), which is a fixed range voltage output means,
Temperature is detected by the resistance divider circuit shown in Figure 3. This resistance divider circuit (27) includes a diffusion resistance (32) formed by diffusion and a resistance (33) formed of polysilicon (Poly-9i), which are designed to have equal resistance values at room temperature. ing. Each resistor (32), (
33) have different temperature coefficients, the output VTMP output from their connection point via the buffer (34) is V
It depends on the temperature around ref/2. In addition, the analog switch (31) is DD in DD2 mode.
By turning off the analog switch (31), the current consumption is reduced. On the other hand, the analog switch (28) shown in FIG. 2 is turned on in the DD2 mode, that is, when DD2="H", and the analog switch (29) is turned on when DD2="L". As a result, in the DD2 mode, the signal Vos is output as the output Vout, and in other than the DD2 mode, the signal Vos is output as the output Vout.
The signal VTMP is output as ut. The above signal Vout
is the A/D converter (1) in the microcomputer (14).
5), where A/D conversion of the analog output on the voltage side lower than the analog reference voltage Vrer is started with the ADT signal and converted into digital data.

In this way, when the analog switches (28, 29) are switched and the OB subtraction AGC differential amplifier circuit (26) is outputting the signal Vos corresponding to the used pixel, the signal is transferred to the A/D converter ( In other cases, the voltage V T within a certain range is input from the temperature detection section (27).
Since MP is input to the A/D converter (15), OB
The negative output generated by subtracting the output corresponding to the black reference pixel from the output corresponding to the unused pixel from the subtraction AGC differential amplifier circuit (26), or the output of the black reference pixel from the output of the used pixel after pixel reading is completed. Even if negative outputs are generated due to subtraction, they are not input to the A/D converter (15), and the voltage VTMP within a certain range is output from the temperature detector (27) to the A/D converter (15). ) is done manually. Therefore, the A/D converter (15) does not exceed the human dynamic range and there is no risk of damage.

This concludes the explanation of the hardware configuration.

Next, the operation of the image sensor (13) described above in each mode will be explained in detail.

First, the initialize mode will be explained.

The microcomputer (14) is MD I = “L”.

When MD2-“L” is output, the mode selection circuit (23)
In this case, only the INI signal is set to “11”, and the integral time control section (2
0) to notify that it is in initialize mode (INI mode). [NI mode uses image sensor (I3)
This mode is for discharging unnecessary charges from the image sensor (13) immediately after the power is turned on. Image sensor (1
3), after the power is turned on, the photodiode (PD), which is a potential well, the storage section (S T), and the transfer lens star (R
G) has accumulated unnecessary charge, and it is necessary to quickly discharge this charge and start up the image sensor (13) so that it can be used. Therefore, in order to quickly discharge unnecessary charges, the INI mode was set, and the potential structure of the image sensor (I3) was changed to the structure shown in FIG. 3.

Hereinafter, explanation will be given along with the potential diagram of FIG. 3 and the time chart of FIG. 4. In Figure 3(a), from the left side, the overflow drain (OD2), overflow gate (
OG), photodiode (FD).

Barrier gate (BG), storage section (ST), transfer game 1
- (SH), transfer register (RG), integral clear gate (Rcc), overflow drain (O
Dl). When voltage is applied to the barrier gate (BG), transfer gate (SH), integral clear gate (RGICG), and transfer register (RG) (
φ1 is applied to the transfer register (RG)), as shown in FIG. 3(b), FD>BG>ST>SH>RG>
The potential is designed so that RG I CG > OD l, and the photodiode (PD) and storage section (S
T), unnecessary charges in the transfer register (RG) are discharged to the overflow drain (ODl) at this time. This operation will be explained along the time chart.

The state in FIG. 4(a) corresponds to FIG. 3(a).

At this time, in the state of NB, = "L", NB, = "L",
No voltage is applied to each gate of the barrier gate (BG), transfer gate (S H), and integral clear gate (RGICG), and the photodiode (PD).

Unnecessary charges are accumulated in each section of the storage section (ST) and transfer register (RG). When both NB and NB are "L", the integral time control section (20) that controls the image sensor (13) does not perform any operation on the image sensor (13).

The microcomputer (14) sets NBl="H-".

When outputting ``N B t''``L'', the integral time control section (
20) is a clock φ sent from the frequency dividing circuit (19). As shown in FIG. 4(b), SH="H
“.

Output B G - "H", RG I CG = "H" to the image sensor (13). Furthermore, SH double signal RG
f The CG multiplied signal is also sent to the transfer lock generation section (30), and the transfer lock generation section (30) uses the SH multiplied signal clock φ. The OR output of is transferred to lock φ1, and RGI
CG signal and φ. Transfer the Noah output of and use it as lock φ2,
In the case of SH-“H”, RGICG-“I]”, φl
The transfer lock to the image sensor (13) is stopped in the state of =="l-1", φ, = "L". and,
The image sensor (13) is SH, BG, RGI CG,
φ8. As shown in FIG. 3(b), the photodiode (FD), the storage section (ST),
Discharge unnecessary charges from the transfer register (RG).

The microcomputer (14) then reads NB, ==“
After outputting “H”, NB, = “H”, NB, - “I5”
.

N B t-"■(" is output. In response to this, the integral time control section (20) synchronizes with the clock φ. and returns the SH multiplied signal and BG multiplied signal to "L" (Fig. 3(C) ), 4th
Figure (C)). On the other hand, in the transfer lock generation section (30), S
As the H-times signal returns to "L", the transfer lock φ1 starts to move, and the transfer lock φ is at "L".

At this time, the potential difference between the transfer register (RG) and the overflow drain (ODI) increases, promoting the discharge of unnecessary charges from the transfer register (RG), and discharging them completely to the overflow drain (ODl) (the third Figure (d), Figure 4 (d)). Also, at this time, since the transfer lock φ remains stopped at "L", another transfer register (RG) adjacent to the above transfer register (RG) to which the transfer lock φ is applied is connected to the above register. No unnecessary charges (RG) will flow.

After the timer measures that a predetermined time has elapsed, the microcomputer (14) sets both NB and NB to "L".
”.The integral time control section (20) thereby returns to φ.

The RGICG signal is set to "L" in synchronization with. Then, the voltage applied to the RGICG terminal of the image sensor (13) becomes zero, and this integral clear gate (RGICG
) is closed. At the same time, the transfer lock generation unit (30
), the transfer lock φ also starts to move as the RG I CG double signal becomes “L” (Fig. 3(e), Fig. 4(
e)). This completes the I cycle of the unnecessary charge discharge operation.

Normally, when initializing the image sensor (13), the above-described unnecessary charge discharge operation is repeated several cycles, and then the initialization mode is ended.

In the present invention, the structure in which an integral clear gate (RGICG) is connected to each register (RG) eliminates the need to discharge unnecessary charge from each register (RG) by transferring it from the register (RG). It is possible to shorten the time for one cycle of the unnecessary charge discharge operation, and to shorten the time allocated to the initialization mode.

Next, the second mode, the integral mode, will be explained.

The microcomputer (14) is M D , = “L”
.

When outputting “M D t” “H”, the mode selection circuit (
23) sets only the INT signal to "H" and notifies the integration time control section (20) that it is in the integration mode (INT mode). In the INT mode, the image sensor (13) starts integrating and ends the integration during high brightness.

The operation will be explained along with FIGS. 5 and 6. The integration starting operation is exactly the same as the unnecessary charge discharge operation during initialization, except for the BG multiplication signal. BG double signal NB, = “H”
After the microcomputer (14) outputs . It is raised to "H" in synchronization with the rise of φ1 (in the figure). This is the same as in ■NI mode. However, the microcomputer (14) is NB, =“
When outputting "L", NBt - "■]", in INI mode, the BG double signal is returned to "L" in synchronization with φ., but in INT mode, the BG double signal remains "H". .BG multiplication signal becomes "Lo" at the end of integration, which will be described later.

At the time of Fig. 5(C) and Fig. 6(c), the transfer gate (SH
) becomes zero, the transfer gate (SH) returns to a higher potential than the photodiode (FD), storage section (ST), and overflow gate (OG), and from this point on, The accumulated charges flow into the storage section (ST) and begin to be accumulated in the storage section (ST), and integration is started at the image sensor (I3).

On the other hand, the time point at which the integration ends is monitored by the output of the brightness monitoring photodiode (9). The operation of the brightness determination circuit (24) will be explained below, and the operation of completing the integration will be explained.

The integration time control unit (20) transmits the AGCr (S signal) to the image sensor (I) at the same timing as the SH multiplication signal at the start of integration.
3) Output. As shown in FIG.
The signal is transmitted through a FET (I) connected to a capacitor (10-1) connected to a brightness monitoring photodiode (9).
FET (1) connected to the gate of FET (0-3) and capacitor (12-1) connected to compensation diode (11).
2-3) is applied to the gate. By applying the AGCRS signal, the capacitor (10-1)
(12-1) is charged to approximately the power supply voltage VDD. When the AGCR9 signal becomes "L" at the same timing as the SH double signal, the power supply is cut off, and from then on, the brightness monitoring photodiode (9) generates a charge according to the amount of light irradiated and is connected to it. The potential of the capacitor (10-1) begins to drop in accordance with the generated charge. On the other hand, the compensating diode (11) generates a charge due to its dark output, and the potential of the capacitor (11-1) connected thereto also begins to drop in accordance with the generated charge. Each potential is passed through each buffer (10-2) and (12-2) to the second
It is output to the analog circuit shown in FIG. 8 of the brightness determination circuit (24) shown in the figure. In Fig. 8, the AGCO8 signal is input to the positive input of an operational amplifier (hereinafter referred to as an operational amplifier) (43), the DO5 signal is input to the negative input of an operational amplifier (43), and the differential output is It is output from the operational amplifier (43). The output V43 of the operational amplifier (43) is expressed by the following formula.

V43-Vref-(DOS-AGCOS) This output V
43 is one comparator (45
) is input manually.

On the other hand, the positive input of the comparator (45) is connected to the FET (46°47.
A constant voltage generated by resistance division according to 48.49) is supplied. During integration, only φd is “H”, FET (49) is turned on, and the supplied constant voltage is V.
4e-(V ref V th). The output of the comparator (45) is “■(” when V43<V411
becomes. That is, Vre "-(DOS-AGCOS)<Vref-Vth
It becomes "H" when DO3-AGCOS>Vth.

(DOS-AGCOS) indicates a voltage dropped due to light irradiation from the brightness monitoring photodiode (9) (the dark output component is compensated by the output of the compensation diode (11)). Immediately after the start of integration, the amount of light irradiated to the brightness monitor photodiode (9) is insufficient, and DOS-
AGCOS is 0, and the output of the comparator (45) (
VFLG) becomes “L”. During integration 1. :(D.O.
At the point in time when S-AGCOS) becomes greater than the voltage v th , the integration for the image sensor (13) becomes appropriate, and the output (VFLG) of the comparator (45) is inverted from "L" to "H". As shown in the time chart of FIG. 6, the integral time control section (20) sets the BG multiplied signal to "OFF" when the output VFLG of the comparator (45) is inverted. When the BG double signal becomes “L”, the signal shown in Fig. 5 (e
), the potential of the barrier gate (BG) becomes larger than the potential of the photodiode (PD), which prevents the charge generated in the photodiode (FD) from flowing into the storage section (ST). (ST)
The charge accumulated in V P 'LG signal is "I]"
, that is, when the BG multiplied signal becomes "L", it is held and the integration is completed. The charge generated after the completion of integration is accumulated in the photodiode (PD), and even if the accumulation progresses, as shown in Fig. 5 (
As shown in e), cross the overflow gate (OG), which has a lower potential than the barrier gate (BG),
Because it is discharged to the overflow drain (OD2),
It does not flow into the storage section (ST).

Further, the integration time control unit (20) sets the BG multiplied signal to "L" and at the same time sets the TINT signal to "L", and notifies the microcomputer (14) of the inversion of the TINT signal via the ADT terminal. This concludes the explanation of the integration start operation in the integration mode and the integration end operation during high brightness.

Next, the third mode, data read mode 1 (DDI
mode).

The microcomputer (14) is M D + = ”
H”.

When MD = “H” is output, the mode selection circuit (23)
sets only the DDI signal to "H", and the integral time control section (20)
to notify that it is in DDI mode. The DDl mode is a mode in which the integration is completed when the luminance is low, and the reading of each pixel data of the image sensor (13) is started.

First, the integration termination operation at low luminance will be explained based on the time chart of FIG. 22. When the subject brightness is low, it may take a long time until the brightness determination circuit (24) determines that the appropriate integration time has been reached. If integration is performed for a long time, the dark output increases, leading to deterioration of the S/N ratio. Furthermore, an extremely long integration time is inconvenient from a system perspective.

For example, when used in a focus detection device for a camera, the focus detection cycle becomes long, causing problems such as the focus detection not being able to follow the movement of the subject. Therefore, the longest integration time allowable within the microcomputer (14) is set in advance, and if the TINT signal output to the ADT terminal has not been inverted even after this time, the M
It outputs Dl-“H”2MD,-“H”, shifts to the DDI mode, and performs the operation of terminating the integration in the DD1 mode. In the DDI mode, the integral time control section (20)
H”.

NBt-“L” signal to microcomputer (14)
When the signal is received from the BG signal, the BG multiplied signal is immediately set to "L". As a result, as in the previous case, the barrier gate (B
The potential of G) becomes higher than that of the photodiode (PD), the charge generated in the photodiode (P, D) stops flowing into the storage section (ST), and the integration ends (FIG. 22).

Next, the operation to start reading out each pixel data of the image sensor (13) will be explained. Regardless of whether the brightness is low or high, the microcomputer (14
) outputs NB, = "H", NB, = 'L', the integral time control unit (20) locks the transfer φ. Synchronize and transfer lock φ. generates an S H signal pulse at the timing of "I" (FIG. 6 or FIG. 22). As a result, as shown in FIGS. 5(f) and (g), a pulse voltage is applied to the SH gate of the image sensor (13), and the signal charges of each pixel accumulated in each accumulation section (ST) are Transferred to transfer register (RG). After that, transfer lock φ
, φ2, the signal charge of each pixel is transferred and read out. Transfer of the signal charges accumulated in each accumulation section (ST) to the transfer register (RG) is carried out by a microcomputer (1
4) is in DDI mode, N B l = “H”, NB, =
This is performed when "L" is output, but at this time, it is necessary that the transfer register (RG) returns from the unsteady state after the start of integration and is in a steady state.

In a steady state, each transfer register (RG) has a dark charge of 23
It is accumulated as shown in the figure. This dark charge is the sum of the dark charge generated in the potential well of each transfer register (RG) and the dark charge of the previous stage register that is sequentially transferred. At the start of integration, the integral clear gate (RG I
Apply a voltage to the gate terminal of the transfer register (CG) and transfer the voltage to the gate terminal of the transfer register (CG).
The integral clear gate (RGICG) between the transfer register (RG) and the overflow drain (ODI) is turned on, and all dark charges in the transfer register (RG) are cleared. After the integral clear gate (RGICG) is turned off, the dark charge in the transfer register (RG) reaches a steady state from the left side of FIG. 23 every time one cycle of the transfer lock φ1 passes.

It takes the number of pixels (N) x one transfer lock period (T) for all transfer registers (RG) to return to a steady state.

When an SH pulse is generated in an unsteady state, the dark charge component of the transfer register (RG) in the charge taken out as an output may be in an unsteady state depending on the pixel, so that a correct signal cannot be taken out. Therefore, the SH pulse is generated at least after the RGICG signal changes from "H" to "L", and then one lock cycle (NXT) after the number of pixels is transferred.
It has to be after some time has passed.

At high brightness, the integration is often completed within one period (NXT), but since the integration is terminated by closing the barrier gate (BG), when one period (NXT) elapses, the integration is completed.
It is possible to make the generation of the SH pulse wait.

Next, regarding the processing of the read pixel output, FIG.
This will be explained below with reference to FIG.

The signal charge of each pixel of the image sensor (13) is φ1=
At the timing of "L", φ, = "H", it is transferred to the capacitor (8-, 1) shown in FIG. In the signal processing timing generation section (21), prior to transferring this signal charge,
As shown in FIG. 12, φ1−“H”, φ,=“L
The 03RS signal pulse is generated at the timing of ", and this pulse is applied to the gate of the FET (8-3) shown in FIG. 1 to charge the capacitor (8-1) to approximately the power supply voltage and reset it. φ1= "L"

When the signal charge is transferred at the time when φ2 - "■]", the voltage of this capacitor (8-1) decreases due to the signal charge, and the output O8 of the image sensor (13) becomes the first
The output is as shown in Figure 2. The AGC differential amplifier circuit (25) uses the RSS/HSS/up and reset voltage levels sent from the signal processing timing generator (21) to the FET (52), capacitor (53), and buffer (51) shown in FIG. ), the sample and hold circuit consists of
It is stored and input to the plus input of the operational amplifier (54).

On the other hand, the O8 signal is input to the negative input of the operational amplifier (54) via the buffer (50), and is input to the negative input of the operational amplifier (54).
5゜56.57.58) Gl, G manually operated at the gate
The output differentially amplified with a gain determined by the two signals (see FIG. 2) is output from the operational amplifier (54) as V os' (see FIG. 12).

Next, the determination of the integral level will be explained.

If the integration is forcibly terminated when the brightness is low, the level of the pixel output of the image sensor (13) will naturally be lower than when it is appropriate. Therefore, in this case, the above-mentioned brightness determination circuit (24) is used to detect the level of integration, and a gain is applied to the output of the image sensor (13) according to the result, so that an output at an appropriate level is always obtained. I'm trying to be able to do that.

The following will explain the brightness determination analog circuit of FIG. 8, the pulse timing chart of FIG. 9, the brightness determination logic circuit of FIG. 10, and the truth table of FIG. 24. Note that the brightness determination circuit (23) is constituted by this brightness determination analog circuit and the brightness determination logic circuit. As shown in FIG. 8, the operational amplifier (43) outputs an output V43-Vref- (DOS-AGCOS) corresponding to the amount of light that the mermaid produces, and one comparator (45
) is input to the negative input. When determining the integration time, φd is applied as shown in FIG.
Vth) is input. Now, when the SHC pulse is generated, latch 1 (73) and latch 2 (74) in Figure 10 are activated.
), latch 3 (75) are all reset.

After that, as shown in FIG. 9, when the φC pulse is generated, the FET (4B) in FIG.
2) is input. Here, if DOS-AGCOS)>Vth/2, the output VFLG of the comparator (45) is “H”.
”, and the AND gate (7
0) becomes "H", and latch 1 (73) is set. After that, as shown in FIG. 9, when the φb pulse is generated, the FET (47) in FIG. 8 is turned on, and the positive input of the comparator (45) is
Vth/4) is input. Here, if DO
S-AGCOS)>Vth/4, the output VFLG of the comparator (45) is “H”.
”, and in FIG. 10, the output of the AND gate (71) becomes “I(”, and the latch 2 (74) is set.Furthermore, as shown in FIG. 9, when the φa pulse is generated, FET (46) in Figure 8 turns on,
The positive input of the comparator (45) has (V er
-V th/8) is manually applied. Here, (DOS
-AGCOS)>Vth/8, the output VFLG of the comparator (45) is “H”.
”, the output of the AND gate (72) shown in FIG.
G3 signal is generated. Based on this signal, the gains are selected as shown in the table below, and a substantially appropriate level of Vos is obtained for each gain.

In this way, by sequentially turning on the FETs (49, 48, 47, 46), the reference voltage generation circuit (RVC)
generates multiple reference voltages, one comparator (45) can judge the brightness at multiple stages, and the image sensor (
13) The number of comparators formed on the same chip can be reduced.

The FET (44) shown in Figure 8 is in INT mode and DD mode.
This is a switch for supplying power to the resistance divider circuit, that is, the reference voltage generation circuit (RVC) only in the + mode.

This FET (44) allows the reference voltage generation circuit (RV
C) is energized only when brightness determination is necessary, reducing current consumption. This saving effect on current consumption becomes greater at high brightness because the integration time becomes shorter than the readout time.

As shown in FIG. 11, the signal Vos' is connected to the FET (60)
, a capacitor (62), and a buffer (64).
65) is input to the negative input. This signal Vos'
Holding is the signal processing timing generation section (21)
This is performed by the OSS/H pulse signal generated at the timing of signal charge transfer from φ to −“H” and φ2=“H”. The signal Vos' is also input to a sample and hold circuit consisting of an FET (59), a capacitor (61), and a buffer (63). This sample and hold circuit samples and holds the output of the black reference pixel subjected to the AQ light shielding shown in FIG. The pulse that provides sample and hold timing is the OBS/H signal shown in FIG. 12, which is generated in the sequence shown below.

As shown in FIG. 2.12, after shifting from the INT mode to the DDI mode, the ADS signal that provides the timing to start A/D conversion appears in the ADT signal. The microcomputer (14) measures the timing of sampling and holding the black reference pixel output while monitoring this signal. The microcomputer (14) outputs NB while outputting the black reference pixel.

-"I]", NB, -"g" are output, and the signal processing timing generating section (21) thereby sets the OBS/H signal to "H". Next, the microcomputer (1
4) is NB until the next ADS signal rises.

= “L”, NBy-“H”, and the signal processing timing generation unit (21) thereby outputs the OBS/H signal “L”.
”.As a result of the above, the FET (59) shown in FIG.
, a capacitor (61), and a buffer (63) holds the input black reference pixel output and inputs it to the negative input of operational amplifier 2 (65). After sampling and holding the black reference pixel, the output of operational amplifier 2 (65) is subtracted by an amount corresponding to the held black reference pixel output, and G'3. It is amplified by the gain determined by the G4 signal (distinction table 11) and output as a signal Vos (FIG. 12).

As described above, the output signal O8 of the image sensor (13) is double sampled in the AGC differential amplifier circuit (25) and the OB subtraction AGC differential amplifier circuit (26), the reset level is subtracted from the signal level, and the reset level is subtracted from the signal level. A signal without the influence of noise is extracted, and the black reference level is further subtracted from the signal without the influence of reset noise, resulting in an output Vos in which the dark output is removed from the output of each pixel.
is obtained. Furthermore, this output Vos is applied to the AGC differential amplifier circuit (
25) and the OB subtraction AGC differential amplifier circuit (26), a gain of x8 to x64 is applied, as described later, according to the average level of each pixel output. In this way, since the two amplifier circuits (25, 26) perform two-stage amplification, the range of resistance values connected to the operational amplifier (54, 64) can be smaller than when amplifying with one amplifier circuit. , the area occupied by the resistor becomes smaller.

Next, the gain of the operational amplifier (54) of the AGC differential amplifier circuit (25) and the gain of the operational amplifier (65) of the OB subtraction AGC differential amplifier circuit (26) shown in FIG. 11 will be described. Here, for the output O8 of the image sensor (13), x8. X16. To switch the gains of X32 and
(65) performs two-stage gain switching. In this case, the operational amplifiers (54) and (65) always have an offset problem. When applying gain in two stages, the first stage gain is GNI, the second stage gain is GN2,
If the offset of each operational amplifier is ΔV1, the manual power is vi1, and the output is Vo, then the output is expressed by the following formula.

V o-((Vi + △V) X GNI+△V)X
GN2-Vi X GNI X GN2+△V -(G
NI X GN2 + GN2) - (Vi + △V)
X GNL

That is, the smaller GN2 is, the smaller the total offset will be.

Therefore, the first stage gain GNI is the second stage gain GN2.
The offset can be suppressed by choosing higher than , but even with this measure the offset remains. For this reason,
As shown in FIG. 11, the subsequent operational amplifier 2 (65) performs a level shift based on a voltage that is lower than the reference voltage Vref by one diode (99) serving as a bias means, so it always performs A l/D conversion. The offset is made to appear on the lower voltage side than the reference voltage V ref as much as possible.

After sampling and holding the signal representing the black reference pixel, the OB subtraction AGC differential amplifier circuit (26) outputs a signal representing the second black reference pixel subjected to Ai2 light shielding before outputting the signal representing the effective pixel. are doing. Since the previously held black reference pixel is subtracted from the output without representing this second black reference pixel, an output that matches the reference voltage V rer is obtained if there is no offset of the operational amplifier. However, since the output of the operational amplifier 2 (65) always has an offset Vorfset on the lower voltage side than the reference voltage V ref, the output becomes (V ref - Vorfset). This is A
When /D conversion is performed, a signal corresponding to Vofrset is obtained as digital data. Thereafter, the output of the effective pixel is subtracted by this Vofrset by the calculation of the microcomputer (14).
The data input to step 14) is substantially the same as the data with the offset component removed.

Next, the DD2 mode will be explained.

In the DD2 mode, the image sensor (I3) is not caused to perform any active operation.

For this reason, the NBl connected to the I10 buffer (22)
, switches the human output of the NB2 signal, outputs the Gl signal to NB, the G3 signal to NB, and the microcomputer (
I4) is notified of the gain information of the output of the image sensor (13). This I10 switching is performed by the DD2 signal.

Only in the DD2 mode, the signal output as Vout is the output Vos of the image sensor (13).

The pixels used in this system are image sensors (13)
are pixels detected in two separate regions of
No photodiode (PD) is provided between the two regions. When outputting the output of these pixels to the A/D converter (15) as Vout, there is a problem that will be described later, so by switching between DD2 mode and DDI mode,
Vos is output as Vout only when valid pixels are output. Output V os' of the AGC differential amplifier circuit (25)
is the output component V corresponding to the optical signal when outputting from an effective pixel.
os' (s ig) and the dark output component V os' (
(V os' = V
os' (sig) + V os' (dark)
). V os in the OB subtraction AGC differential amplifier circuit (26)
' (dark) is subtracted, and Vos= V er - G N 2 X (Vos'
-Vos' (dark)) as the A/D converter (15
).

At this time, since the output of the pixel from which the photodiode (PD) has been removed has neither an output corresponding to an optical signal nor a dark output component, Vos'=O. Here, when Vos' (dark) is subtracted by the OB subtraction AGC differential amplification (26), Vos=Vrer-GN2 x (0-Vos' (da
rk))>Vref, and Vos is on the lower voltage side than the A/D convertible reference voltage Vref.
The voltage becomes higher than ref, which may exceed the dynamic range of A/D conversion and cause damage to the A/D conversion section (15). For this purpose, except for the output of effective pixels, the analog switches (28) and (29) are switched.
It always outputs a temperature detection output VTMP that can be converted into an A/D converter. In this way, only when outputting effective pixels, DD2-“I
]” is output as Vos, and D when outputting an invalid pixel.
By outputting VTMP as D2-“L”, A/D conversion is always performed within the dynamic range of A/D conversion.

This concludes the explanation of the DD2 mode and the explanation of the first embodiment.

Next, a second embodiment will be described in which the means for removing the dark output component in the first embodiment is modified. here,
Only the differences from the first embodiment will be explained with reference to the block diagram in FIG. 14 and the circuit diagram of the AGC differential amplifier circuit in FIG. 15.

First, the block diagram of FIG. 14 showing the second embodiment and the block diagram of FIG.
As shown by the differences in the block diagram of FIG. 2 illustrating an embodiment of the analog reference voltage V re
This embodiment differs from the first embodiment in that f' is output from the AGC differential amplifier circuit (125). Furthermore, in FIG. 14, the oBirJt calculation AGC differential amplifier circuit in the first embodiment is removed.

The operation of the second embodiment will be explained with reference to FIG. As in the first embodiment, the image sensor (I3) outputs the output of the black reference pixel before outputting the effective pixel. Here, A
FET (+59) in the GC differential amplifier circuit (125),
A sample and hold circuit consisting of a capacitor (161) and a buffer (163) samples and holds the output of the black reference pixel using the OBS/H pulse. In the first embodiment, the held output was connected to the negative input of the operational amplifier 2 (65), and subtraction was performed by the operational amplifier 2 (65), but in the second embodiment, the held output was connected to the negative input of the operational amplifier 2 (65). It is output as ref'. This V ref″
is supplied to the A/D converter (I 15) as an analog reference voltage, and the A/D converter (115) uses this voltage as a language to A/D convert the input voltage.

That is, in order to take the difference between the human power Vout and the reference voltage Vref and convert it into a digital value, an A/D converter (l
This is equivalent to subtracting the black reference pixel output in l5).

In addition, the output of the black reference pixel sampled and held by the sample and hold circuit consisting of PET (160), capacitor (162), and buffer (164) and the output of each effective pixel are the outputs of operational amplifier 2 (165). Since these differentials are taken within the A/D converter (115), the offset of operational amplifier 2 (165) is completely removed. Therefore, in the second embodiment, the dark output of the image sensor (13) is removed and the operational amplifier 2 (+6
5) Offset removal is performed.

Next, a third embodiment will be described with reference to FIGS. 16, 17, and 18. This third embodiment differs from the first and second embodiments in the dark output removal means.

First, let us look at the block diagram of the third embodiment (Fig. 16) and the block diagram of the first embodiment.
Differences from the block diagram of the embodiment (FIG. 2) will be described.

In the third embodiment, the sample and hold pulse OBS/H for the black reference pixel is manually input to the A/D converter (215), and the OB subtraction A(, C) differential amplifier circuit is removed.

In this third embodiment, subtraction of the black reference pixel is performed within the A/D converter (215).

FIG. 18 shows the A/D converter (215), and this A/D converter (215)
The conversion section (215) includes an A/D conversion circuit (206) and an internal circuit provided on the same chip. The output of the image sensor inputted as Vin in FIG. 18 consists of the output of the black reference pixel and the subsequent effective pixels. The output of the black reference pixel is output from the FET (
201), capacitor (202) and buffer (20
3) is sampled and held by a sample and hold circuit consisting of the following. Then, the effective pixel output that is input thereafter is subtracted by the sampled and held black reference pixel output by the operational amplifier (205), and then the A/D conversion circuit (205) subtracts the sampled and held black reference pixel output.
6).

FIG. 17 shows an AGC differential amplifier circuit (225).

In the first embodiment, there was a sample and hold circuit for the output of the black reference pixel, but in the third embodiment, this is removed. Further, as in the second embodiment, since the black reference pixel output is also output from the same operational amplifier (165) as the black pixel output, the offset of this operational amplifier (165) is completely canceled.

Next, a fourth example in which the dark time output removing means is different from the above-mentioned embodiment.
An example will be explained. FIG. 19 is a hardware block diagram according to the fourth embodiment. This is different from FIG. 16, which is a block diagram of the third embodiment, when the reference voltage V re
The difference is that f is not manually input to the A/D converter (315), and the AGC differential amplifier circuit (225) has exactly the same configuration as the third embodiment.

FIG. 20 shows the A/D converter (315), and this A/D converter (315)
The conversion section (315) includes an A/D conversion circuit (405) and an internal circuit provided on the same chip. While the image sensor (13) is outputting the black reference pixel,
The OBS/H pulse is given to the /D converter (315), and the output of the black reference pixel input to the terminal Vin is sent to the FET (401), the capacitor (402), and the buffer (
Sample and hold is performed by a sample and hold circuit consisting of 403). The held black reference pixel output is input to the A/D conversion circuit (405) as an analog reference voltage (Vr, ef'). From then on, the effective pixel output of the image sensor (13) input to the terminal Vin is the output of the held black reference pixel (
Vrcf') is subtracted and then A/D converted. This removes the dark output component.

In the above embodiment, the AGC amplifier circuit (25) and the OB subtraction circuit
Amplification was performed in two stages with a C-operated amplifier circuit (26), that is, a first stage and a second stage, but this amplification is not limited to two stages, but multistages such as three stages, four stages, etc. You can also do it with

<Effects of the Invention> As is clear from the above, the solid-state imaging device of the present invention has the following effects:
A photoelectric conversion section, an accumulation section for accumulating charges generated in the photoelectric conversion section, and the charges stored in the accumulation section are sequentially transferred. A brightness monitor means for monitoring the amount of light irradiated to the transfer register and the photoelectric conversion section, an accumulation means for accumulating the charge generated in the brightness monitor means, a brightness determination circuit for determining the brightness based on the output from the accumulation means, A first-stage amplifier circuit that amplifies the output of the transfer register and a second-stage amplifier circuit that amplifies the output of the first-stage amplifier circuit are provided to adjust the gains of the first-stage and second-stage amplifier circuits. Multiplication is amplified by the combined number of gains, so
The number of switching stages in each stage of the amplifier circuit may be small, and therefore the width between the minimum and maximum resistance values in each stage of the amplifier circuit becomes small, and the area occupied by the resistor on the chip becomes small.

Further, by increasing the gain of the first-stage amplifier circuit and decreasing the gain of the second-stage amplifier circuit, the total offset becomes relatively small.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the image sensor in the solid-state imaging device of the present invention, FIG. 2 is a block diagram of the fixed imaging device of the first embodiment of the invention, and FIG. 3 shows the potential structure of the image sensor at the time of initialization. 4 is a time chart of the signal in the initialization mode of the first embodiment, FIG. 5 is a diagram showing the potential structure of the image sensor in the integral mode, and FIG. 6 is a time chart of the signal in the integral mode. Fig. 7 is a structural diagram of a compensation diode, Fig. 8 is a circuit diagram of a luminance judgment analog circuit, Fig. 9 is a time chart of signals during luminance judgment,
FIG. 10 is a circuit diagram of the brightness determination logic circuit, FIG. 1I is a circuit diagram of the AGC differential amplifier circuit and the OB subtraction AGC differential amplifier circuit in the first embodiment, FIG. 12 is a time chart regarding pixel output processing, and FIG. The figure is a circuit diagram of the temperature detection section, Figure 14 is a block diagram of the solid-state imaging device of the second embodiment, Figure 15 is a circuit diagram of the AGC operational amplifier circuit of the second embodiment, and Figure 16 is the third embodiment. 17 is a circuit diagram of the AGC operational amplifier circuit of the third embodiment, FIG. 18 is a circuit diagram of the A/D conversion section, and FIG. 19 is a block diagram of the solid-state imaging device of the fourth embodiment. 20 is a circuit diagram of the A/D conversion section of the fourth embodiment, FIG. 21 is a structural diagram of the image sensor, and FIG. 22 is a time chart of signals in the integration mode of the fourth embodiment. FIG. 23 is a diagram explaining the transfer of dark charges, and FIG. 24 is a diagram showing a truth table of the brightness determination logic circuit. FD, BG, ST...Storage means, SI (...Shift gate, RG...Transfer register, RG [CG, Integral clear gate, 14...Microcomputer, 20...Integration time control unit, 23...・Mode selection circuit, 24... Brightness judgment circuit, 30... Transfer lock generation unit. Patent applicant: Minolta Camera Co., Ltd. Agent: Patent attorney: Mr. Fuki and two others Figure 3 (a) (]) Peripheral table Lb 7 Figure Shu & La La-7, 71-b

Claims (2)

[Claims] (1) A photoelectric conversion section that generates charges corresponding to each pixel, an accumulation section that accumulates the charges generated in the photoelectric conversion section, and a transfer register that sequentially transfers the charges accumulated in this accumulation section. brightness monitoring means for generating charges according to the amount of light and monitoring the amount of light irradiated to the photoelectric conversion section; storage means for accumulating the charges generated in the brightness monitoring means; and based on the output from the storage means. a first stage amplifier circuit whose gain is switched based on the output from the brightness determination circuit and amplifies the output of the transfer register; and a second stage amplifier circuit whose gain is switched by the second stage amplifier circuit and which amplifies the output of the first stage amplifier circuit. (2) The solid-state imaging device according to claim 1, wherein the gain of the first stage amplifier circuit is higher than the gain of the second stage amplifier circuit.