JPH01205681A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent superfluous integration and to integrate to an appropriate level all the time by providing a fetching electrode at the approximately central part of the longitudinal direction of a photodiode for a luminance monitor and promptly outputting from the photodiode for the luminance monitor. CONSTITUTION:When light is irradiated on plural photoelectric converting parts PDs aligned correspondingly to picture elements, a charge is generated, and the charge is accumulated in an accumulating part ST. On the other hand, a photodiode 9 for the luminance monitor has a thin and long shape in which the aligning direction of the picture elements is made into the longitudinal direction, and the fetching electrode from the photodiode 9 for the luminance monitor is provided at the approximately central part of the longitudinal direction. Consequently, response time for the output from the photodiode 9 for the luminance monitor becomes 1/4 of that at the time of fetching the charge from the edge of the photodiode 9 for the luminance monitor. Thus, since the output of the photodiode 9 for the luminance monitor responds promptly, as the result, a signal from an integral action time control part is outputted promptly, and the superfluous integration in the accumulating part ST can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a solid-state imaging device used in an automatic focus detection device of a camera or the like.

<Prior Art> In a solid-state imaging device, charges generated in a photoelectric conversion section are accumulated in a storage section and integrated, and this integration time needs to be determined according to the amount of light incident on the photoelectric conversion section.

Therefore, conventional solid-state imaging devices include a plurality of photoelectric conversion units arranged in correspondence with pixels, an accumulation unit that accumulates charges from the photoelectric conversion units, and a detection unit that detects the amount of light irradiated to the photoelectric conversion units. For this purpose, a photodiode for brightness monitoring is provided to take out charge from one end, and the integration time in the storage section is controlled based on the output of this photodiode for brightness monitoring (Japanese Patent Laid-Open No. 125817/1983). .

<Problems to be Solved by the Invention> However, the conventional solid-state imaging device described above has a problem in that the response time is long because the brightness is monitored by extracting the charge from one end of the brightness monitoring photodiode. In other words, the photoelectric conversion sections are aligned corresponding to the pixels, and the photodiodes for brightness monitoring that detect the amount of light irradiated to the photoelectric conversion sections have correspondingly elongated shapes in the direction in which the pixels are aligned. . When the charge is taken out from one end of this elongated brightness monitoring photodiode,
The response time is proportional to the square of the lengthwise dimension of the brightness monitoring photodiode, so if the length of the photodiode is doubled, the response time is quadrupled.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to prevent excessive integration and to always perform integration at an appropriate level by quickly outputting from a brightness monitoring photodiode.

<Means for Solving the Problems> In order to achieve the above object, the solid-state imaging device of the present invention has the following features:
As illustrated in FIG. 1.2, a plurality of photoelectric conversion units (PD) are arranged corresponding to a plurality of aligned pixels and generate charges according to the illuminance of incident light, and each of the above-mentioned photoelectric conversion units (
A storage section (ST) that accumulates charges from the photoelectric conversion section (PD), which is arranged with the longitudinal direction of the pixel alignment direction as the longitudinal direction, generates charges according to the illuminance of the incident light and irradiates the photoelectric conversion section (ST) with the photoelectric conversion section (PD). A photodiode for brightness monitoring that monitors the amount of light and has an extraction electrode approximately at the center in the longitudinal direction.
9), and a brightness determining means (24) for determining brightness based on the output of the brightness monitoring photodiode (9);
and an integral time control section (20) that controls an integral time for accumulating the charge from the photoelectric conversion section (PD) in the storage section (ST) based on the output from the luminance determination section (24). It is characterized by

<Operation> A plurality of photoelectric conversion units (FD) aligned corresponding to pixels
When light is irradiated on the surface, an electric charge is generated, and this electric charge is transferred to the metallurgical part (
ST). On the other hand, the brightness monitor photodiode (9) has an elongated shape with the pixel alignment direction as the longitudinal direction;
) is provided approximately at the center in the longitudinal direction. Therefore, the brightness monitor photodiode (9)
The response time of the output from the terminal is one-fourth that of the case where the charge is extracted from the terminal.

The output of the brightness monitoring photodiode (9) is manually input to the brightness determination means (24) to determine the brightness, and the output of the brightness determination means (24) is input to the integral time control section (24).
0), and the integral time control section (20) controls the storage section (ST) according to the luminance determined by the luminance determination means (24).
Controls the integration time at .

Since the response of the output of the luminance monitoring photodiode (9) is fast in this way, the signal from the integration time control section (20) is eventually output quickly, and excessive integration in the storage section (ST) is prevented. Ru.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

First, a first example will be described. FIG. 1 shows the configuration of an image sensor (13) manufactured as a COD.

(1) is a photodiode array consisting of a plurality of photodiodes (PD) as photoelectric conversion means that generate charges according to the amount of incident light; (s'r) accumulates charges generated by the photodiodes (PD) Accumulation part, (B
G) is a barrier gate consisting of a field effect transistor (hereinafter referred to as FET), which is a gate provided between the photodiode (PD) and the storage section (ST), and this barrier gate (BG) is The photodiode (PD) and the storage section (ST) are connected to allow the charge generated in the photodiode (PD) to flow into the storage section (S'l''), while the photodiode (PD) and the storage section (ST) are connected when no voltage is applied. The storage section (ST) is divided to stop the charge generated in the photodiode (PD) from flowing into the storage section (ST).Also, (RG) uses two-phase drive to transfer the charge from the left to the right in the drawing. The transfer register (ST-1) is a transfer gate consisting of an FET, which is a gate provided between the storage section (ST) and the transfer register (RG).This transfer gate (Sl-1) Sometimes the storage section (ST
) and the transfer register (RG) to connect the storage section (ST
) is transferred to the transfer register (RG), while the storage section (ST) and transfer register (RG) are separated when no voltage is applied, and the charges accumulated in the storage section (ST) are transferred to the transfer register (RG). (RG).

Further, (RGICC;) is an integral clear gate consisting of an FET as a gate. This integral clear gate (RG
ICG) connects the transfer register (RG) and overflow drain (ODI) when voltage is applied, and transfers unnecessary charges from the photodiode (FD) and storage section (ST) of each pixel to the transfer register (RG) before integration. to the overflow drain (ODI). The overflow drain (ODI) is connected to the power supply voltage VDD and has the lowest potential.

On the other hand, an overflow gate (OG) is provided between the photodiode (PD) and the overflow drain (OD2).
No voltage is applied to G), and the potential is always fixed to be lower than the potential of the barrier gate (BG) when no voltage is applied. The charge of each pixel transferred to the transfer register (RG) is transferred to the transfer lock φ8. φ is sequentially transferred to the capacitor (8-1) from the right side in the drawing. The capacitor (8-1) is connected to the FE before the charge is transferred.
Charging is reset to the power supply voltage by the OSR3 signal applied to the gates of T(8-3). Then the capacitor (
S-t) is lowered in potential from the charging voltage by the transferred charge. The voltage between the terminals of this capacitor (8-1) is taken out as an O8 signal by a buffer (8-2). Although (8-1) has been described here as a capacitor for convenience of explanation, it can be replaced with a PN junction of a diode, and when the circuit is integrated, this capacitor is manufactured as a diode. Hereinafter, the same applies when referring to a capacitor.

On the plurality of photodiodes (PD) at the ends of the photodiode array (1), a light-shielding AQ and a film (1-ri) are provided to take out a black reference pixel output, which will be described later.

The photodiode array (1) detects pixels necessary for the automatic focus detection system using blocks on both sides except for the central area.
) corresponds to unused pixels that are unnecessary for the automatic focus detection system. For this reason, the central photodiode (PD) of the photodiode array (1) corresponding to the unused pixel is removed, and a photodiode (9) for brightness monitoring (to be described later) is installed in this removed portion for output processing. A part of the circuit is inserted (see Figure 21).

Further, in order to control the integration time of the image sensor (13), a brightness monitoring photodiode (9) is provided as brightness monitoring means for monitoring the amount of light incident on the photodiode (PD).

The brightness monitor photodiode (9) has an elongated shape because it is formed across two blocks on both sides of the photodiode array (1) that detects pixels necessary for the automatic focus detection system. In addition, this brightness monitoring photodiode (9) is configured so as not to monitor the amount of light irradiated to the area corresponding to the unused pixel.
The portions corresponding to the unused pixels are shielded from light by an A12 film (9-D).In this way, the brightness monitoring photodiodes (9) are arranged with the alignment direction of the photodiode array (1) as the longitudinal direction. , is configured to span two blocks at both ends of the photodiode array (1), and the portions corresponding to unused pixels are covered with an Al1 film (
9-1), it is possible to accurately monitor the average output level of the portion corresponding to the used pixel. A part of the circuit for output processing of the brightness monitoring photodiode (9) is inserted in the center of the photodiode array (1) from which the photodiode (PD) has been removed, as shown in FIG.

As mentioned above, the brightness monitoring photodiode (9) has an elongated shape, and when its length is Q, and the output is taken out from one end, generally the length Q and the response time τ
The relationship τcc (l '' holds between The output is taken out from the extraction electrode of the photodiode (9).For this reason, the response time is
Compared to the case where a contact is provided at the end of the contact point, it is 1/4 as shown in the following equation.

In this way, since the extraction electrode is provided near the center and the response of the brightness monitoring photodiode (9) is fast, even if the integration time is determined based on the output of the brightness monitoring photodiode (9), it will not be excessive. Appropriate integration can be performed without performing excessive integration that stores charges in the storage section (ST).

A capacitor (10-1), which is a storage means, is connected to the photodiode (9) for brightness monitoring.
), the capacitor (10-1) is charged to the power supply voltage VDD. A
After the GCR9 signal is removed, the potential at the capacitor (10-1) drops due to charges generated in response to light irradiation. This potential is outputted as an AGCO8 signal via a buffer (10-2) which is an output means.

The compensation diode (+1) is provided to remove the dark output of the brightness monitoring photodiode (9), and a light-shielding AQ film (11-1) is provided on top of the compensation diode (+1). This compensation diode (11) is designed to obtain the same amount of output as the dark output of the brightness monitor photodiode (9), but if it has the same structure as the brightness monitor photodiode (9). requires the same area as the brightness monitoring photodiode (9), leading to an increase in chip size. Therefore, as shown in FIG. 7(a), this compensating diode (11) consists of a large number of parts whose N-type parts are separated from each other and arranged at regular intervals, and these are made into P-type parts. By embedding it in the dark area, the length (peripheral length) La of the PN junction on the surface, which is the source of the dark output, is increased, and the same amount of dark output can be achieved with a smaller size than the brightness monitor photodiode (9). It is designed to provide the following.

The compensation diode (11) is connected to the capacitor (12-1
). This capacitor (12-1) is connected to the FET (12-3) prior to integration of the image sensor (13).
) is charged to the power supply voltage VDD by the AGCR9 signal applied to the gate. However, after the AGCR8 signal is removed, the potential of the capacitor (12-1) gradually decreases due to the dark output charge of the compensation diode (11). This potential is output as a DOS signal via a buffer (12-3). This concludes the description of the configuration of the image sensor (13).

Next, the overall hardware configuration will be explained along the block diagram of FIG. (14) in the middle of FIG. 2 is a microcomputer (μCon) which is an arithmetic control means for controlling the drive of the image sensor (13). Image sensor control section (16) of this microcomputer (14)
are two signals M D + , M D for switching the four modes of the image sensor (13), which will be described later.
In addition to outputting two signals NBI and NB for giving the output of t and operation timing, the I10 buffer (22) starts A/D conversion of the TINT signal indicating whether integration is completed or not and the image sensor output. An ADT signal which is a logical sum with the ADS signal shown is input, and gain information Gl is input.

The G3 signal is manually input using the signal lines of the N B r and N B signals.

The circuit on the left side of the microcomputer (14) is
It is constructed on a 1-chip IC. Among these, the above I
The 10 buffer (22) has the following functions: That is,
A function of ORing the above TINT signal and ADS signal and outputting it to the microcomputer (14) as an ADT signal, and switching the input/output of the signal line of the NB + signal and NB + when inputting.

A function of inputting the N B signal from the microcomputer (14) and outputting the Gl and G3 signals to the microcomputer (14) at the time of output, as well as the signal level of the microcomputer (14) and the frequency dividing circuit (19). Integral time control section (20), signal processing timing generation section (21)
) and a signal level in a circuit such as a transfer lock generating section (30).

On the other hand, the mode selection circuit (23) selects M D 1. M
Decodes the D2 signal and selects one of the following four modes.
This circuit selects two modes. MD, = “L”.

When MD=“L”, the mode selection circuit (23) is ■N
Set only the T signal to "H" and select INI mode. I
The NI mode is a mode for initializing the image sensor (13). MD,=“L”.

In the case of MD, -“H”, the mode selection circuit (23)
Set only the NT signal to "H" and select NT mode.

The INT mode is a mode in which the image sensor (13) performs integration. When MD, -“I-1” and MD2 are “H”, the mode selection circuit (23) sets only the DDI signal to “H”.
Bind and select DDI mode. DDI mode is a mode to start reading out the image sensor (13),
It is also a mode in which sample and hold of black reference pixels, which will be described later, is performed using the NB, , NB2 signals. MD, -“I
4”, if MDt="L", mode selection circuit (23)
sets only the DD2 signal to "H" and selects the DD2 mode. In the DD2 mode, the image sensor (13) is read out, and the read and processed output of the image sensor (13) is sent to the microcomputer (I4) A/
This is the mode for transmitting to the D converter (15). The operation and functions of each mode will be described later.

The above frequency dividing circuit (19) is a microcomputer (I4)
The base q clock CP generated by the clock generator (18) of
The image sensor (13) transfer lock φ1. The clock φ that is the source of φ. At the same time,
Integral time control section (20) and signal processing timing generation section (
21) clock φ. A timing clock φ is generated for synchronization with the

The above clock φ. is sent to the transfer lock generation section (30), where S sent from the integral time control section (20)
H times signal 1'lG I CG times signal clock φ0 causes clock φ7. φ, and image sensor (+
3) transfer lock. Integral time control section (20
) is IN! mode, timing signal NB transmitted from the microcomputer (14) when in INT mode,
Based on NB2, the AGCR8 signal and the BG multiplied signal SH multiplied signal RGICG signal are generated in synchronization with the clock φ sent from the frequency divider circuit (19), and the integration start operation is performed.

Each of the above signals is applied to each part of the image sensor (13) shown in FIG. Moreover, the integral time control section (20)
“L” when the image sensor (I3) integration becomes appropriate
- Luminance judgment circuit (24) which is a subtraction means to obtain “■]”
Integration completion signal VFLG from , or mode selection circuit (
23) is transmitted when the DDI signal is "H", a BG multiplied signal is generated by the timing signals NB, . . . NEt, and the integration is completed.

Furthermore, this integration time control section (20) is configured so that the DDI signal is “
When it is H#, the timing signal N B +.

NB generates a signal times SH and performs an operation to start reading the output from the storage section (ST). At this time, signals for obtaining luminance information, which will be described later, as well as φa, φb, and φC1φd signals are transmitted to the luminance determination circuit (24). The brightness determination circuit (24) monitors the amount of light irradiated to the image sensor (13) using the AGCO8 signal and DOS signal sent from the image sensor (13), and when it is determined that the integral level has reached an appropriate level. , V
r;' A function to invert the LG signal and change the integral to V at low brightness.
If the integration is completed before the FLG signal is inverted, it has a function of determining the level of integration and outputting Gl and G3 signals for switching the gain of the image sensor (13) according to the determined level.

AGC differential amplifier circuit (25) is image sensor (I3)
This circuit amplifies the output signal O8 sent from.

In this AGC differential amplifier circuit (25), the FET (8) of the image sensor (13) is turned on by the 08RS signal.
-3), the potential O8 immediately after the capacitor (8-1) is charged is sampled and held by RSS/HSS/ sent from the signal processing timing generator (21), and then this potential O8 is transferred and locked. According to the capacitor (8
-1) is transferred to the capacitor (8-1), which has dropped due to the generated charges, and the potential O8 of the capacitor (8-1) is taken, amplified, and used as a signal Vos'. It is output to the amplifier circuit (26).

The gain of this OB subtraction AGC differential amplifier circuit (26) during amplification is switched by the G3 signal output from the brightness determination circuit (24). The above OB subtraction AGC amplifier circuit (2
6), differential amplification between the output of the black reference pixel and the output of the normal pixel without AQ light shielding, that is, the effective pixel, and the output Vos'
Sample hold is being carried out. Photodiode(
PD) always has a dark output, so the pixel detected by a photodiode (PD) with Aρ light shielding is used as a black reference pixel, and the dark output is defined as a quasi-pixel, and the black reference is determined from the output of the normal pixel. The value obtained by subtracting the pixel components is the output of the image sensor (13). The OB subtraction AGC amplifier circuit (26) includes an AGC differential amplifier circuit (25).
) is repeatedly input in synchronization with the output Vos' from the transfer lock, so the signal processing timing generator (2
1) The level of the signal output V as' of the effective pixel is sampled and held by the O9S/H signal sent from the O9S/H signal sent from the OBS signal sent from the signal processing timing generation section (21).
/H signal causes the output Vos to change while the black reference pixel is being output.
'Sample and hold.

The OB subtraction AGC amplifier circuit (26) subtracts the sampled and held black reference pixel component level Vos' from the sampled and held valid pixel signal output level Vos',
Furthermore, the signal is multiplied by a gain that is switched by the G3 signal output from the brightness determination circuit (24), and is output as a signal Vos below the analog reference voltage V ref.

The temperature detection section (27), which is a fixed range voltage output means,
Temperature is detected by the resistance divider circuit shown in Figure 3. This resistance divider circuit (27) includes a diffusion resistance (32) formed by diffusion and a resistance (33) formed of polysilicon (Poly-Si), which are designed to have equal resistance values at room temperature. ing. Each resistor (32), (
33) have different temperature coefficients, the output V TMP output from their connection point via the buffer (34) is:
It corresponds to the 1L degree with Vref/2 as the center.

Note that in the DD2 mode, the analog switch (31) is set to DD=“L”, and the current consumption is reduced by turning off the analog switch (31). On the other hand, the analog switch (28) shown in Fig. 2 is in DD2 mode.
That is, when DD2 is "H", it is turned on, and conversely, when DD2 is "L", the analog switch (29) is turned on. As a result, in the DD2 mode, the output V ou
The signal Vos is output as output t, and the signal V TMP is output as output V out in modes other than DD2 mode. The above signal Vout is the A/D in the microcomputer (14).
The analog reference voltage V
A/D conversion of analog output on the lower voltage side than rer
It starts with the D'I'' signal and converts it into digital data.

In this way, when the analog switches (28, 29) are switched and the OB subtraction AGC differential amplifier circuit (26) is outputting the signal Vos corresponding to the used pixel, the signal is transferred to the A/D converter ( 15), while in other cases, the voltage VTM within a certain range from the temperature detection part (27)
Since P is input manually to the A/D converter (15), the negative output generated by subtracting the output corresponding to the black reference pixel from the output corresponding to the unused pixel from the OB subtraction AGC differential amplifier circuit (26), , if a negative output is generated by subtracting the output of the black reference pixel from the output of the used pixel after pixel reading is completed, these are not input manually to the A/D converter (I5) and are sent to the temperature detector ( 27), the voltage VTMP within a certain range is input to the A/D converter (15). Therefore, the A/D converter (15) does not exceed the input dynamic range and there is no risk of damage.

This concludes the explanation of the hardware configuration.

Next, the operation of the image sensor (13) described above in each mode will be explained in detail.

First, the initialization mode will be explained.

The microcomputer (14) is MD l = “L”.

When MD2="L" is output, the mode selection circuit (23)
In this case, only the INI signal is set to “H”, and the integral time control section (20
) is notified that it is in initialization mode (INI mode). The INI mode is a mode for discharging unnecessary charges from the image sensor (13) immediately after the image sensor (13) is powered on. Image sensor (13
) is a potential well, which is a photodiode (PD), a storage section (ST), and a transfer register (rtG) after power is turned on.
) has accumulated unnecessary charge, and it is necessary to quickly discharge this charge and start up the image sensor (I3) so that it can be used. Therefore, in order to quickly discharge unnecessary charges, the INI mode was set, and the potential structure of the image sensor (13) was changed to the structure shown in FIG. 3.

Hereinafter, explanation will be given along with the potential diagram of FIG. 3 and the time chart of FIG. 4. In Figure 3(a), from the left side, the overflow drain (OD2), overflow gate (
OG), photodiode (PD).

Barrier gate (BG), storage section (ST), transfer game 1
- (SH), transfer register (RG), integral clear gate (RG I CG), overflow drain (ODl
). Barrier gate (BG), transfer gate (
When a voltage is applied to each gate of the integral clear gate (RGICG) and the transfer register (RG) (φ1 is applied to the transfer register (RG)), Fig. 3 (
As shown in b), PD>BG>ST>SH>RG>r
The potential is designed so that LG I CG > OD 1, and the photodiode (PD) and storage section (S
T), unnecessary charges in the transfer register (RG) are discharged to the overflow drain (ODl) at this time. This operation will be explained along the time chart.

The state in FIG. 4(a) corresponds to FIG. 3(a).

At this time, in the state of NB,="L", NB,="L",
No voltage is applied to each gate of the barrier gate (BG), transfer gate (S H), and integral clear gate (RG I CG), and also to the photodiode (PD).

Unnecessary charges are accumulated in each section of the storage section (ST) and transfer register (RG). NB+, NB! When both are "L", the integral time control section (20) that controls the image sensor (13) does not perform any operation on the image sensor (13).

Microcomputer (14) is NB, = “■(”.

When NB = "S" is output, the integral time control section (20)
is the clock φ sent from the frequency dividing circuit (19). In synchronization with, SH-“H” as shown in FIG. 4(b).

Output BG="H" and RG I CG="H" to the image sensor (!3). Furthermore, the SH multiplied signal RG I
It is also sent to the CG double signal transfer lock generation unit (30),
In the transfer lock generation section (30), the SH multiplied signal clock φ
. The OR output of is transferred to lock φ1, and RGICG
signal and φ. Transfers the Noah output of and locks φ.

In the case of SH="I" and RGICG="H", the transfer to the image sensor (13) is stopped in the state of φ1="H" and φ="L". And the image sensor (13) is SH, BG, RGI CG
,φhφ! As shown in FIG. 3(b), each signal causes the photodiode (PD), storage section (ST),
Discharge unnecessary charges from the transfer register (RG).

The microcomputer (14) then NB, = “H”
, NBt-“H” is output, then NB,=“Lo.

NB, outputs ="H". In response to this, the integral time control section (20) sets the clock φ. and returns the SH double signal and BG double signal to "L" (Figure 3 (C), Figure 4 (C)
)). On the other hand, in the transfer lock generation unit (30), the S■■ signal returns to "L", so that the transfer lock φ1 starts moving, and the transfer lock φ2 is at "L".

At this time, the potential difference between the transfer register (RG) and the overflow drain (ODI) increases, promoting the discharge of unnecessary charges from the transfer register (RG), and completely discharging them to the overflow drain (ODI) (see Figure 3). d), Figure 4(d)). Also, at this time, since the transfer lock φ remains stopped at "L", another transfer register (rtG) adjacent to the transfer register (RG) to which the transfer lock φ is applied is connected to the above register. (RG)
No unnecessary charge flows into the circuit.

After the timer measures that the predetermined time has elapsed, the microcomputer (14) returns both N B and N B t to "L". The integral time control section (20) thereby adjusts φ. The RGICG signal is set to "L" in synchronization with. Then, the voltage applied to the RGICG terminal of the image sensor (i3) becomes zero, and this integral clear gate (RG
ICG) is closed. At the same time, in the transfer lock generating section (30), the RGICG signal becomes L'', and the transfer lock φ also starts moving (Fig. 3(e), Fig. 4(
e)). With this, one cycle of unnecessary charge discharging operation is completed.

Normally, when initializing the image sensor (13), the above-described unnecessary charge discharge operation is repeated several cycles, and then the initialization mode is ended.

In the present invention, the structure in which an integral clear gate (RGICG) is connected to each register (RG) eliminates the need to discharge unnecessary charge from each register (RG) by transferring it from the register (RG). It is possible to shorten the time for one cycle of the unnecessary charge discharge operation, and to shorten the time allocated to the initialization mode.

Next, the second mode, the integral mode, will be explained.

Microcomputer (14) is M D + = “L”
.

When M D 2 = “H” is output, the mode selection circuit (
23) sets only the INT signal to "H" and notifies the integration time control section (20) that it is in the integration mode (INT mode). In the INT mode, the image sensor (13) starts integrating and ends the integration during high brightness.

The operation will be explained along with FIGS. 5 and 6. The start operation of integration is the discharge operation of unnecessary charges at the time of initialization, and the operation of 100
Exactly the same except for the signal. I3G signal is NB, =“
I-1", Nl32-"L" by microcomputer (
14), the integral time controller (20) outputs φ
. (In the figure, this is the timing of the rising of φ). This is the same as in INT mode. However, if the microcomputer (14) outputs NB,="L", NB,="l(", then T
φ in NI mode. synchronized with the BG double signal “L” again.
”, but in INT mode, the BG double signal “■1
''.The I3G signal remains as `` at the end of integration, which will be described later
It becomes “L”.

At the time of FIG. 5(C) and FIG. 6(c), the transfer gate (ST)
-■) becomes zero, the transfer gate (SH)
returns to a higher potential than the photodiode (PD), storage section (ST), and overflow gate (OG), and from this point on, the charge generated in the photodiode (PD) flows into the storage section (ST), Accumulation begins in the storage section (ST), and integration begins in the image sensor (13).

On the other hand, the time point at which the integration ends is monitored by the output of the brightness monitoring photodiode (9). The operation of the brightness determination circuit (24) will be explained below, and the operation of completing the integration will be explained.

The integration time control section (20) transmits the AGCRS signal to the image sensor (13) at the same timing as the SH multiplication signal at the start of integration.
). As shown in FIG. 1, the AGCR3 signal is transmitted through a FET (10-1) connected to a capacitor (10-1) connected to a brightness monitoring photodiode (9).
3) and a capacitor (12-1) connected to a compensation diode (11).
-3) is applied to the gate. By applying the AGCR9 signal, the capacitor (10-1), (
12-1) is charged to approximately the power supply voltage VDD. When the AGCR9 signal becomes “L” at the same timing as the SH double signal,
The power supply is cut off, and from this point on, the brightness monitoring photodiode (9) generates a charge according to the amount of light irradiated, and the capacitor (10-1) connected to it generates a charge according to the generated charge. The potential begins to drop. On the other hand, the compensating diode (11) generates a charge due to its dark output, and the potential of the capacitor (12-1) connected thereto also begins to drop in accordance with the generated charge. Each potential is outputted to the analog circuit shown in FIG. 8 of the brightness determination circuit (24) in FIG. 2 via each buffer (lO-2) and (12-2). In Fig. 8, the AGCOS signal is input to the positive input of an operational signal amplifier (hereinafter referred to as an operational amplifier) (43), and the DO8 signal is input to the negative input of an operational amplifier (43), and the differential output thereof is input. is output from the operational amplifier (43).

The output V43 of the operational amplifier (43) is expressed by the following formula.

V43=Vref (DO9AGCOS) This output V
43 is a comparator (45) which is a brightness determination means.
The negative input is done manually.

On the other hand, the positive input of the comparator (45) is connected to the FET (46°47.
A constant voltage generated by resistance division according to 48.49) is supplied. During integration, only φd is 'H', FET (49) is turned on, and the constant voltage supplied is V.
+e-(Vref-vth). Comparator (4
The output of 5) becomes "H" when V43<V49. That is, Vref-(DOS-AGCOS)<Vref-Vth
When DO9-AGCOS>Vth, it becomes H''.

(DOS-AGCOS) indicates the voltage dropped by the light irradiation of the photodiode (9) for brightness monitoring (the dark output component is compensated by the compensation diode (one output). Immediately after the start of integration The amount of light irradiated to the brightness monitor photodiode (9) is insufficient, and DOS-A
GCO9=O, and the output of the comparator (45) (V
FLG) is set to L”.During integration, (DOS-AG
When COS) becomes larger than the voltage vth, the integration for the image sensor (I3) becomes appropriate, and the output (VPLG) of the comparator (45) is inverted from "L" to "H". As shown in the time chart of FIG. 6, the integral time control section (20) sets the BG multiplied signal to "L" when the output VFLG of the comparator (45) is inverted. When the BG multiplied signal becomes "L", the potential of the barrier gate (BG) becomes larger than the potential of the photodiode (PD), as shown in FIG. 5(e).
The charge generated in the photodiode (PD) is transferred to the storage section (S
The charges stored in the storage section (ST) are prevented from flowing into the VFLG signal "I", that is, the BG multiplied signal "L".
”, and the integration ends. The charge generated after the integration is accumulated in the photodiode (PD), and even if the accumulation progresses, as shown in FIG. It crosses the overflow gate (OG), which has a lower potential than (BG), and is discharged to the overflow drain (OD2), so it does not flow into the storage section (ST).

Further, the integral time control section (20) sets the BG multiplied signal "L" and at the same time sets the TINT signal "L", and notifies the microcomputer (14) of the inversion of the Tl!IT signal via the ADT terminal. This concludes the explanation of the integration start operation in the integration mode and the integration end operation during high brightness.

Next, the third mode, data read mode 1 (DDI
mode).

The microcomputer (14) is M D + = ”
H”.

When M D t "H" is output, the mode selection circuit (
23) sets only the DDl signal to "H" and notifies the integration time control section (20) that it is in the DDI mode. DDl
The mode is a mode in which an operation of completing the integration is performed when the brightness is low, and an operation of starting reading out each pixel data of the image sensor (13) is performed.

First, the integration termination operation at low luminance will be explained based on the time chart of FIG. 22. When the subject brightness is low, it may take a long time until the brightness determination circuit (24) determines that the appropriate integration time has been reached. If integration is performed for a long time, the dark output increases, leading to deterioration of the S/N ratio. Furthermore, an extremely long integration time is inconvenient from a system perspective.

For example, when used in a focus detection device for a camera, the focus detection cycle becomes long, causing problems such as the focus detection not being able to follow the movement of the subject. Therefore, the longest integration time allowable within the microcomputer (14) is set in advance, and if the TINT signal output to the ADT terminal has not been inverted even after this time, the M
D,=“H” 1MDt” “H” is output, the mode is shifted to DD! mode, and the operation of terminating the integration is performed in DD1 mode.In the DD! mode, the integral time control section (20) outputs N B +
”“I]”.

NB, = “L” signal to the microcomputer (14)
When the signal is received from the BG signal, the BG multiplied signal is immediately set to "L". As a result, as in the previous case, the barrier gate (B
The potential of G) becomes higher than that of the photodiode (PD), the charge generated in the photodiode (PD) stops flowing into the storage section (ST), and the integration ends (second
Figure 2).

Next, the operation to start reading out each pixel data of the image sensor (13) will be explained. Regardless of whether the brightness is low or high, the microcomputer (14
) outputs NB, -“H”, NB,=“L”, the integral time control unit (20) transfers and locks φ. Synchronize and transfer lock φ. SI-I signal pulse is generated at the timing of "H" (FIG. 6 or FIG. 22). As a result, as shown in FIG. 5 (D, (g)), a pulse voltage is applied to the SH gate of the image sensor (13), and the signal charge of each pixel accumulated in each accumulation section (ST) is transferred. Transferred to register (RG). After that, transfer lock φ
3. The signal 1X of each pixel is transferred and read out by φ. The microcomputer (14) transfers the signal charges accumulated in each accumulation section (ST) to the transfer register (RG) by setting N B l="I-1" in the DDI mode.
This is performed when NB, -"Ll is output, but at this time, it is necessary that the transfer register (rtG) returns from the unsteady state after the start of integration and becomes a steady state.

In a steady state, each transfer register (RG) has a dark charge of 23
It is accumulated as shown in the figure. This dark charge is the sum of the dark charge generated in the potential well of each transfer register (R(',) and the dark charge of the previous stage register that is sequentially transferred. At the start of integration, the integral clear gate) (RG
A voltage is applied to the gate terminal of the transfer register (NC) and the integral clear gate CRGICG) between the transfer register (nc) and the overflow drain (ODI) is turned on, and all dark charges in the transfer register (RG) are cleared. After the integral clear gate (RGICG) is turned off, the dark charge in the transfer register (RG) reaches a steady state from the left side of FIG. 23 every time one cycle of the transfer lock φ1 passes.

It takes a time equal to the number of pixels (N) x transfer lock I period (T) until all transfer registers (rtG) return to a steady state.

When an SH pulse is generated in an unsteady state, the dark charge component of the transfer register (RG) in the charge taken out as an output may be in an unsteady state depending on the pixel, so that a correct signal cannot be taken out. For this reason, the SH pulse is generated at least after the RGICG signal changes from "H" to "off", and then after one lock cycle (NXT) for X number of pixels.
It has to be after some time has passed.

At high brightness, the integration is often completed within one cycle (NXT), but since the integration is completed by closing the barrier gate (BG), the SH pulse is delayed after one cycle (Nx'l'') has elapsed. It is possible to wait for it to occur.

Next, regarding the processing of the read pixel output, FIG.
This will be explained below with reference to FIG.

The signal charge of each pixel of the image sensor (13) is φ1=
At the timing of "L", φ, = "H", it is transferred to the capacitor (S-t) shown in FIG. In the signal processing timing generation section (21), prior to the transfer of this signal charge, as shown in FIG.
The 0SR9 signal pulse is generated at the timing of ", and this pulse is applied to the gate of the FET (8-3) shown in FIG. 1 to charge the capacitor (8-1) to approximately the power supply voltage and reset it. φ, = “L”.

When the signal charge is transferred at the time when φ becomes -“H”, the voltage of this capacitor (8-1) decreases due to the signal charge, and the output O8 of the image sensor (13) becomes the 12th
The output is as shown in the figure. AGC differential amplifier circuit (
25), the voltage level at the time of reset is determined by the R6S/H signal sent from the signal processing timing generator (21) to the sample and hold circuit consisting of the PET (52), capacitor (53), and buffer (51) shown in Figure 11. According to
It is stored and input to the plus input of the operational amplifier (54).

On the other hand, the O8 signal is input to the negative input of the operational amplifier (54) via the buffer (50), and is input to the negative input of the operational amplifier (54).
Gl, G input to the gate of 5゜56.57.58)
The output differentially amplified with a gain determined by the two signals (see FIG. 11) is output from the operational amplifier (54) as Vos' (see FIG. 12).

Next, the determination of the integral level will be explained.

If the integration is forcibly terminated when the brightness is low, the level of the pixel output of the image sensor (13) will naturally be lower than when it is appropriate. Therefore, in this case, the above-mentioned brightness determination circuit (24) is used to detect the level of integration, and a gain is applied to the output of the image sensor (13) according to the result, so that an output at an appropriate level is always obtained. I'm trying to be able to do that.

The following will explain the brightness determination analog circuit of FIG. 8, the pulse timing chart of FIG. 9, the brightness determination circuit of FIG. 10, and the truth table of FIG. 24. Note that the brightness determination circuit (23) is constituted by this brightness determination analog circuit and the brightness determination Ronok circuit. As shown in FIG. 8, the operational amplifier (43) outputs an output V43=Vre" (DOS-AGCOS) corresponding to the amount of light to be detected, and a comparator (45) which is a brightness determination means
The negative input is done manually. When determining the integration time, φd is applied as shown in FIG. 9, and the FET (49) of the reference voltage generation circuit (RVC) is turned on.
The positive input of the comparator (45) is (Vref-V
th) is input. Now, when the SH pulse occurs, latch + (73) and latch 2 (74) in Figure 1O are activated.
, latch 3 (75) are all reset.

After that, as shown in FIG. 9, when the φC pulse is generated, the PET (48) in FIG. 8 is turned on, and the positive input of the comparator (45) is
2) is input. Here, if DOS-AGCOS)>vth/2, the output VFLG of the comparator (45) is “I
4”, and the AND gate shown in Figure 10 (
70) becomes "H", and latch 1 (73) is set. After that, as shown in FIG. 9, when the φb pulse is generated, the FET (47) in FIG. 8 is turned on.
The positive input of the comparator (45) has (V er
-V th/4) is input. Here, like D
OS-AGCOS)>Vth/4, the output VFLG of the comparator (45) is “1”.
1”, and in FIG. 10, the AND gate (71)
The output becomes "I("), and latch 2 (74) is sent.Furthermore, as shown in FIG. 9, when the φa pulse is generated, the FET (46) in FIG. 8 is turned on, and the comparator The positive input of (45) has (V ref
-V th/8 ) is input. Here, (D.O.
S-AGCOS)>Vth/8, the output VFLG of the comparator (45) is “H”.
”, the output of the AND gate (72) shown in FIG. 10 becomes “H”, and the latch 3 (75) is set. In each of the above cases, as shown in the truth table of FIG. 24, Gl,
G3 signal is generated. Based on this signal, the gains are selected as shown in the table below, and a substantially appropriate level of Vos is obtained for each gain.

In this way, by sequentially turning on the FETs (49, 48, 47, 46), the reference voltage generation circuit (RVC)
generates multiple reference voltages, one comparator (45) can judge the brightness at multiple stages, and the image sensor (
13) The number of comparators formed on the same chip can be reduced.

The PET (44) shown in Figure 8 is in INT mode and DD mode.
Only in I mode is the resistor divider circuit, i.e. the group Q? This is a switch for supplying power to the 1X pressure generation circuit (RVC). This PET (44) allows the reference voltage generation circuit (
RVC) is energized only when brightness determination is necessary, reducing current consumption. This saving effect on current consumption becomes greater at high brightness because the integration time becomes shorter than the readout time.

As shown in FIG. 11, the signal V os' is
), a capacitor (62), and a buffer (64).
It is input to the minus input of (65). This signal V o
The holding of s' is carried out by the signal processing timing generator (2
This is performed by the OSS/I-1 pulse signal generated at the timing of signal charge transfer from 1) to φ1=“L” and φ2=“H”. In addition, the signal V os'' is F'ET (5
9), a capacitor (61), and a buffer (63). This sample and hold circuit performs sample and hold of the output of the black pixel subjected to Ad light shielding as shown in FIG. The pulse that provides the sample and hold timing is OBS/ as shown in Figure 12.
This is an H signal, which is generated in the sequence shown below.

As shown in FIGS. 2 and 12, after shifting from the INT mode to the DDI mode, the ADS signal that provides the timing to start A/D conversion appears in the ADT signal. The microcomputer (14) measures the timing of sampling and holding the black reference pixel output while monitoring this signal. The microcomputer (14) outputs NB while outputting the black reference pixel.

= "H", NBt - "H", and the signal processing timing generation section (21) thereby outputs the OBS/H signal as "
H”.Continue with the microcomputer (14)
is NB until the next ADS signal rises.

= “L”, NB, = “H”, and the signal processing timing generation unit (21) thereby outputs the OBS/H signal “L”.
”.As a result of the above, the FET (59) shown in FIG.
, a capacitor (61), and a buffer (63) hold the inputted black reference pixel output and output it to the negative output of operational amplifier 2 (65). After sampling and holding the black reference pixel, the output of the operational amplifier 2 (65) is subtracted by the amount corresponding to the held black reference pixel output, and the output of the operational amplifier 2 (65) is subtracted by the amount corresponding to the held black reference pixel output, and the output of the G3. It is amplified by the gain determined by the G4 signal (distinction table 11) and output as the signal Vos (FIG. 12).

As described above, the output signal O8 of the image sensor (13) is double sampled in the AGC differential amplifier circuit (25) and the OB subtraction AGC differential amplifier circuit (26), the reset level is subtracted from the signal level, and the reset level is subtracted from the signal level. A signal without the influence of noise is extracted, and the black reference level is further subtracted from the signal without the influence of reset noise, resulting in an output Vos in which the dark output is removed from the output of each pixel.
is obtained. Furthermore, this output Vos is compared to the output OS of the image sensor (13) from the AGC differential amplifier circuit (
25) and the OB subtraction AGC differential amplifier circuit (26), a gain of x8 to x64 is applied, as described later, according to the average level of each pixel output. In this way, since the two amplifier circuits (25, 26) perform two-stage amplification, the range of resistance values connected to the operational amplifier (54, 64) can be smaller than when amplifying with one amplifier circuit. , the area occupied by the resistor becomes smaller.

Next, the gain of the operational amplifier (54) of the AGC differential amplifier circuit (25) and the gain of the operational amplifier (65) of the OB subtraction AGC differential amplifier circuit (26) shown in FIG. 11 will be described. Here, for the output O8 of the image sensor (13), x8. x16. To switch the gain of x32° x 64, operational amplifier 1 (54) has two stages, operational amplifier 2
(65) performs two-stage gain switching. In this case, the operational amplifiers (54) and (65) always have an offset problem. When applying gain in two stages, the first stage gain is GNI, the second stage gain is GN2,
If the offset of each operational amplifier is 671, the human power is vi1, and the output is Vo, the output is expressed by the following formula.

Vo=((Vi+△V) x GN l+△v)xGN
2= Vi X GNI X GN2+△V −(GN
I X GN2 + GN2) = (Vi+△V)XGN
lxGN2+ΔVxGN If the total gain GNIXGN2 of the 22-stage operational amplifier does not change, an offset due to GN2 appears in the second term (ΔV×GN2) of the above equation.

That is, the smaller GN2 is, the smaller the total offset will be.

Therefore, the first stage gain GNI is the second stage gain GN2.
The offset can be suppressed by choosing higher than , but even with this measure the offset remains. For this reason,
The operational amplifier 2 (65) in the latter stage is as shown in Fig. 2.
Since the level is shifted based on the voltage that is lowered by one diode (99) serving as a biasing means from the reference voltage Vrer, the offset is on the lower voltage side than the reference voltage Vref so that A/D conversion can be performed at all times. That's what I do.

After sampling and holding the signal representing the black reference pixel, the OB subtraction AGC differential amplifier circuit (26) outputs a signal representing the second black reference pixel subjected to AQ light shielding before outputting the signal representing the effective pixel. are doing. Since the previously held black reference pixel is subtracted from the output representing this second black reference pixel, if there is no offset of the operational amplifier, the reference voltage V
You will get an output that matches rer. However, since the output of the operational amplifier 2 (65) always has an offset Voffset on the lower voltage side than the reference voltage V rer, the output becomes (V ref - V offset). This is A
When /D conversion is performed, a signal corresponding to Voffset is obtained as digital data. Thereafter, the output of the effective pixel is subtracted by this Voffset by the calculation of the microcomputer (14).
The data entered manually in step 14) is substantially the same as the data with the offset component removed.

Next, the DD2 mode will be explained.

In the DD2 mode, the image sensor (13) is not caused to perform any active operation.

Therefore, the NB connected to the I10 buffer (22),
, NB, switches the input/output of the signals, outputs the Gl signal to NB, the G3 signal to NBt, and connects the microcomputer (
14), the gain information of the output of the image sensor (13) is notified. This I10 switching is performed by the DD2 signal.

Only in the DD2 mode, the signal output as Vout is the output Vos of the image sensor (13).

The pixels used in this system are image sensors (I3)
are pixels detected in two separate regions of
No photodiode (r'D) is provided between the two regions. A/D with output of these pixels as Vout
Since there is a problem described later when outputting to the converter (15), Vos is output as Vout only when an effective pixel is output by switching between DD2 mode and DDI mode. Output V os of AGC differential amplifier circuit (25)
' is the output component V os' (sig) corresponding to the optical signal and the dark output component V os' when the effective pixel is output.
(dark) (V os' =
V os' (sig) + V os' (dark
)). V o in the OB subtraction AGC differential amplifier circuit (26)
The component corresponding to s' (dark) is subtracted, and Vos=V ref - G N 2 X (Vos'
-Vos' (dark)) as the A/D converter (15
).

At this time, the output of the pixel from which the photodiode (PD) has been removed does not have an output corresponding to an optical signal or a dark output component, so Vos'=O. Here, when Vos' (dark) is subtracted by the OB subtraction AGC differential amplification (26), Vos=Vref-GN2 x(0-Vos'(dark)
k))>Vref, and the reference voltage V that can be A/D converted
Contrary to the lower voltage side than ref, Vos is the reference voltage V
The voltage becomes higher than rer, which may exceed the dynamic range of A/D conversion and cause damage to the A/D conversion section (15). For this purpose, except for the output of effective pixels, the analog switches (2B) and (29) are switched.
It always outputs a temperature detection output VTMP that can be converted into an A/D converter. In this way, only when outputting effective pixels, DD2-“
By outputting Vos as "I" and outputting VTMP with DD2="L" when an invalid pixel is output, the A/D conversion is always within the dynamic range of A/D conversion.
I am trying to perform D conversion.

This concludes the explanation of the DD2 mode and the explanation of the first embodiment.

Next, a second embodiment will be described in which the means for removing the dark output component in the first embodiment is modified. here,
Only the differences from the first embodiment will be explained with reference to the block diagram in FIG. 14 and the circuit diagram of the AGC differential amplifier circuit in FIG. 15.

First, the block diagram of FIG. 14 showing the second embodiment and the block diagram of FIG.
As shown by the differences in the block diagram of FIG. 2 illustrating an embodiment of the analog reference voltage V re
This embodiment differs from the first embodiment in that f' is output from the AGC differential amplifier circuit (125). Further, in FIG. 14, the OB calculation AGC differential amplifier circuit in the first embodiment is removed.

The operation of the second embodiment will be explained with reference to FIG. As in the first embodiment, the image sensor (13) outputs the output of the black reference pixel before outputting the effective pixel. Here, A
A sample and hold circuit including an FET (159), a capacitor (161), and a buffer (1, 63) in the GC differential amplifier circuit (125) samples and holds the output of the black reference pixel using the 0I3S/I-1 pulse. 1st
In the embodiment, the held output is input to operational amplifier 2 (6
5), and subtraction was performed using operational amplifier 2 (65), but in the second embodiment, the held output is output as V ref.This Vre
f'' is supplied to the A/D converter (115) as an analog reference voltage, and the A/D converter (115) A/D converts the input voltage using this voltage as a reference.

That is, in order to take the difference between the human power Vout and the reference voltage V ref' and convert it into a digital value, an A/D converter (
This is equivalent to subtracting the black reference pixel output in 115).

In addition, the output of each effective pixel including the output of the black reference pixel sampled and held by the sample and hold circuit consisting of F'ET (+60), capacitor (162) and buffer (164) also becomes the output of operational amplifier 2 (+65). Since these differentials are taken within the A/D converter (+15), the offset of operational amplifier 2 (165) is completely removed. Therefore, in the second embodiment, the dark output of the image sensor (I3) is removed and the operational amplifier 2 (
+65) offset is removed.

Next, a third embodiment will be described with reference to FIGS. 16, 17, and 18. This third embodiment differs from the first and second embodiments in the dark output removal means.

First, let us look at the block diagram of the third embodiment (Fig. 16) and the block diagram of the first embodiment.
Differences from the block diagram of the embodiment (FIG. 2) will be described.

In the third embodiment, the sample and hold pulse OBS/H of the black reference pixel is input to the A/D converter (215), and the OB subtraction AGC differential amplifier circuit is removed. In this third embodiment, subtraction of the black reference pixel is performed within the A/D converter (215).

FIG. 18 shows the A/D converter (215), and this A/D converter (215)
The conversion section (215) includes an A/D conversion circuit (206) and an internal circuit provided on the same chip. The output of the image sensor inputted as Vin in FIG. 18 consists of the output of the black reference pixel and the subsequent effective pixels. The output of the black reference pixel is OBS/H pulse unit, PET (201),
:] is sampled and held by a sample and hold circuit consisting of a capacitor (202) and a buffer (203). After that, the effective pixel output that is to be measured is subtracted by the sampled and held black reference pixel output by an operational amplifier (205), and then input to the A/D conversion circuit (206).

FIG. 17 shows an AGC differential amplifier circuit (225).

In the first embodiment, there was a sample and hold circuit for the output of the black reference pixel, but in the third embodiment, this is removed. Further, as in the second embodiment, since the black reference pixel output and the effective pixel output are output from the same operational amplifier (+65), the offset of this operational amplifier (165) is completely canceled.

Next, a fourth example in which the dark time output removing means is different from the above-mentioned embodiment.
An example will be explained. FIG. 19 is a hardware block diagram according to the fourth embodiment. This is different from FIG. 16, which is a block diagram of the third embodiment, in that the reference voltage Vre "
is different in that it is not input to the A/D converter (315), and the AGC differential amplifier circuit (225) is
The configuration is exactly the same as that of the embodiment.

FIG. 20 shows the A/D converter (315), and this A/D converter (315)
The conversion section (315) includes an A/D conversion circuit (405) and an internal circuit provided on the same chip. While the image sensor (13) is outputting the black reference pixel,
The OBS/I-[pulse is given to the /D converter (315), and the output of the black reference pixel inputted to the terminal Vin is sent to the FET (401), the capacitor (402), and the buffer (
Sample and hold is performed by a sample and hold circuit consisting of 403). The held black reference pixel output is input to the A/D conversion circuit (405) as an analog reference voltage (V ref"). From then on, the effective pixel output of the image sensor (13) inputted to the terminal Vin is:
As in the second embodiment, the held black reference pixel output (Vref'') is subtracted and then A/D converted.

This removes the dark output component.

<Effects of the Invention> As is clear from the above, the solid-state imaging device of the present invention has the following effects:
The direction in which the pixels are aligned is the longitudinal direction, and the amount of light irradiated to the photoelectric conversion unit is monitored by a brightness monitoring photodiode that has an extraction electrode approximately in the center of this longitudinal direction, and the output from this brightness monitoring photodiode is Since the brightness is determined by the brightness determination means based on the brightness determination means, and the integration time in the storage section is determined by the integral time control section based on the output from the brightness determination means, the response speed of the output of the brightness monitoring photodiode is Therefore, the integration in the storage section can be performed appropriately, and over-integration can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the image sensor in the solid-state imaging device of the present invention, FIG. 2 is a block diagram of the fixed imaging device of the first embodiment of the invention, and FIG. 3 shows the potential structure of the image sensor at the time of initialization. 4 is a time chart of the signal in the initialization mode of the first embodiment, FIG. 5 is a diagram showing the potential structure of the image sensor in the integral mode, and FIG. 6 is a time chart of the signal in the integral mode. Fig. 7 is a structural diagram of a compensation diode, Fig. 8 is a circuit diagram of a luminance judgment analog circuit, Fig. 9 is a time chart of signals during luminance judgment,
FIG. 1O is a circuit diagram of the brightness determination logic circuit, FIG. 11 is a circuit diagram of the AGC differential amplifier circuit and the OB subtraction AGC differential amplifier circuit in the first embodiment, FIG. 12 is a time chart regarding pixel output processing, and FIG. The figure is a circuit diagram of the temperature detection section, Figure 14 is a block diagram of the solid-state imaging device of the second embodiment, Figure 15 is a circuit diagram of the AGC operational amplifier circuit of the second embodiment, and Figure 16 is the third embodiment. 17 is a circuit diagram of the AGC operational amplifier circuit of the third embodiment, FIG. 18 is a circuit diagram of the A/D conversion section, and FIG. 19 is a block diagram of the solid-state imaging device of the fourth embodiment. 20 is a circuit diagram of the A/D conversion section of the fourth embodiment, FIG. 21 is a structural diagram of the image sensor, and FIG. 22 is a time chart of signals in the integration mode of the fourth embodiment. FIG. 23 is a diagram explaining the transfer of dark charges, and FIG. 24 is a diagram showing a truth table of the brightness determination logic circuit. PD, BG, ST...Storage means, SH...Shift gate, RG...Transfer register, RG I CG...Integration clear gate, 14...
Microcomputer, 20... Integral time control unit, 23... Mode selection circuit, 24... Brightness determination circuit, 30... Transfer lock generation unit. 7th Perimeter Lb Circumferential &La La” 7.7Lb

Claims (1)

[Claims] (1) A plurality of photoelectric conversion units that are aligned corresponding to the plurality of aligned pixels and generate charges according to the illuminance of incident light; and an accumulation unit that accumulates the charges from each of the photoelectric conversion units; The luminance device is arranged with the pixel alignment direction as the longitudinal direction, generates a charge according to the illuminance of incident light, monitors the amount of light irradiated to the photoelectric conversion section, and has an extraction electrode approximately at the center in the longitudinal direction. a monitor photodiode; a brightness determination unit that determines brightness based on the output of the brightness monitor photodiode; and a storage unit that stores charges from the photoelectric conversion unit based on the output from the brightness determination unit. A solid-state imaging device comprising: an integration time control section that controls an integration time.