JPH01205626A - A/d converter - Google Patents

Abstract

PURPOSE:To relieve the processing of an image sensor side by providing a sample and hold means for an input voltage, a subtraction means subtracting another input voltage and a voltage subject to sample and hold by a sample and hold means, and an A/D conversion circuit applying A/D conversion to the output of the subtraction means on one and same chip. CONSTITUTION:A sample and hold means sampling and holding an input voltage, a subtraction means 205 subtracting another input voltage and a voltage subject to sample and hold by the sample and hold means and an A/D conversion circuit 206 applying A/D conversion to the output of the subtraction means 205 are provided on one and same chip. The sample and hold means consists of a FET 201, a capacitor 202 and a buffer 203. Thus, the chip area of the image sensor is reduced, the difference between the effective picture element output and the black reference picture element output is taken by the A/D converter and the difference is subject to A/D conversion, then the output processing at the image sensor side is reduced and its circuit constitution is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an A/D conversion device used in a solid-state imaging device of an automatic focus detection device of a camera, and the like.

<Prior art> Conventionally, an A/D conversion device inputs a reference voltage and an input voltage to a differential amplifier, and converts the output of the differential amplifier into an A/D converter.
A device in which A/D conversion is performed using a D converter is known (Japanese Unexamined Patent Publication No. 83627/1983).

In addition, in solid-state imaging devices, when converting the output of the image sensor into an A/D converter, the output of the black reference pixel of the image sensor is converted into an A/D converter in order to remove the dark output component in the output of the image sensor. It is necessary to level shift the voltage to an analog reference voltage.

Therefore, a sample and hold circuit and a differential amplifier are provided on the same chip as the image sensor, and the sample and hold circuit samples and holds the black reference pixel output that is output before the image sensor's effective pixel output. The black reference pixel output and the effective pixel output are input to a differential amplifier, and the difference between them is calculated.

The output of this operational amplifier is then input to an A/D converter for A/D conversion.

<Problems to be Solved by the Invention> However, in the above-mentioned solid-state imaging device, a sample-hold circuit and a differential amplifier for level-shifting the black reference pixel output to an analog reference voltage are provided on the same chip as the image sensor. There is a problem that the chip area increases. Furthermore, since the sample-and-hold circuit and the operational amplifier are provided on the image sensor chip, there is a problem in that the burden of output processing on the image sensor side increases and the circuit configuration becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide an A/D conversion device that can reduce the chip area on the image sensor side and simplify output processing on the image sensor side.

<Means for Solving the Problems> In order to achieve the above object, the A/D converter of the present invention includes a sample and hold means for sampling and holding an input voltage, and another input voltage. subtraction means (205) for subtracting the voltage sampled and held by the sample and hold means; and an A/D conversion circuit (205) for A/D converting the output of the subtraction means (205).
206) are provided on the same chip.

<Operation> The sample bold means samples and holds the black reference pixel output, for example. The subtraction means (205) subtracts the effective pixel output and the black reference pixel output sampled and held by the sample and hold means.
The output of 205) is input to an A/D conversion circuit (206) and A/D converted.

In this way, since this A/D conversion device has the sample hold means, the subtraction means (205), and the A/D conversion circuit (206) on the same chip, the chip area of the image sensor is reduced. In addition, since the A/D conversion device calculates the difference between the effective pixel output and the black reference pixel output and converts this difference into A/D, the output processing on the image sensor side is reduced and the circuit configuration thereof is simplified. .

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

First, a first example will be described. FIG. 1 shows the configuration of an image sensor (13) manufactured as a COD.

(1) is a photodiode array consisting of a plurality of photodiodes (PD) as photoelectric conversion means that generate charges according to the amount of incident light, and (s'r) accumulates charges generated by the photodiodes (PD). Storage part, (1
3G) is a barrier gate consisting of a field effect transistor (hereinafter referred to as FET), which is a gate provided between a photodiode (PD) and a storage section (ST), and this barrier gate (BG) is connected to a voltage When voltage is applied, the photodiode (PD) and storage section (ST) are connected to allow the charge generated in the photodiode (PD) to flow into the storage section (ST), while when no voltage is applied, the photodiode (PD) and storage section (ST) are connected. (ST) to stop the charge generated in the photodiode (PD) from flowing into the storage section (ST). The above photodiode (PD) and storage section (
ST) and barrier gate (BG) constitute storage means. In addition, (RG) is a transfer register that transfers charge from the left to the right in the drawing by two-phase drive, and (SH) is a storage unit (ST).
This is a transfer gate consisting of an FET, which is a gate provided between the transfer register (RG) and the transfer register (RG). This transport game) (
SH) connects the storage section (ST) and transfer register (RG) when voltage is applied, and transfers the charge accumulated in the storage section (ST) to the transfer register (RG), while when no voltage is applied, the charge is transferred to the transfer register (RG). The storage section (ST) and transfer register (RG) are separated to prevent charges accumulated in the storage section (ST) from flowing into the transfer register (RG). Also, (RGIC
G) is an integral clear gate consisting of an FET as a gate. This integration clear gate (RGICG) connects the transfer register (RG) and overflow drain-in (ODI) when voltage is applied, and clears unnecessary charges in the photodiode (PD) and storage section (ST) of each pixel prior to integration. from the transfer register (RG) to the overflow drain (
ODI). Above overflow drain (O
DI) is connected to the power supply voltage VDD and has the lowest potential.

On the other hand, an overflow gate (OG) is provided between the photodiode (PD) and the overflow drain (OD2).
No voltage is applied to G), and it is always fixed at a potential lower than the potential of Parigate 1-(BG) when no voltage is applied. The charge of each pixel transferred to the transfer register (rtG) is transferred to the transfer lock φ8. φ is sequentially transferred to the capacitor (8-1) from the right side in the drawing. Before the charge is transferred to the capacitor (8-1),
Charging is reset to the power supply voltage by the 08R8 signal applied to the gate of PET (8-3). Thereafter, the potential of the capacitor (8-1) decreases from the charging voltage by the transferred charge. The voltage across this capacitor (8-1) is taken out as an O8 signal by a buffer (8-2). Although (8-1) has been described here as a capacitor for convenience of explanation, it can be replaced with a PN junction of a diode, and when the circuit is integrated, this capacitor is manufactured as a diode. Hereinafter, the same applies when referring to a capacitor.

A light-shielding A12 film (l-1) is placed on the plurality of photodiodes (PDs) at the end of the photodiode array (1).
is provided to extract the black reference pixel output, which will be described later. The photodiode array (1) detects pixels necessary for the automatic focus detection system using blocks on both sides except for the central area.
The vicinity of the center of 1) corresponds to unused pixels that are unnecessary for the automatic focus detection system. Therefore, the central photodiode (PD) of the photodiode array (1) corresponding to the unused pixel is removed, and a brightness monitoring photodiode (9), which is a brightness monitoring means to be described later, is installed in the removed portion.
) is inserted a part of the circuit for output processing (second
(See Figure 1).

Further, in order to control the integration time of the image sensor (13), a brightness monitoring photodiode (9) is provided as brightness monitoring means for monitoring the amount of light incident on the photodiode (PD).

The brightness monitor photodiode (9) has an elongated shape because it is formed across two blocks on both sides of the photodiode array (1) that detects pixels necessary for the automatic focus detection system. In addition, this brightness monitoring photodiode (9) is configured so as not to monitor the amount of light irradiated to the area corresponding to the unused pixel.
Af2 film (9-1) is placed on the part corresponding to the above unused pixel.
It is shaded by. In this way, the brightness monitoring photodiode (9) is arranged with the alignment direction of the photodiode array (1) as the longitudinal direction, and is configured to straddle the two blocks at both ends of the photodiode array (1). The part corresponding to the pixel used is covered with Aa film (
9-1), it is possible to accurately monitor the average output level of the portion corresponding to the used pixel. A part of the circuit for output processing of the brightness monitoring photodiode (9) is inserted in the center of the photodiode array (1) from which the photodiode (PD) has been removed, as shown in FIG.

As mentioned above, the brightness monitoring photodiode (9) has an elongated shape, and when its length is g and the output is taken out from one end, generally the length e and the response time τ
The relationship τoc(1' holds true between them, and the length g
The longer the period, the faster the responsiveness deteriorates. therefore,
In order to prevent responsiveness from deteriorating, the output is taken out from an extraction electrode near the center of the brightness monitoring photodiode (9). Therefore, the response time is 1/4 compared to the case where a contact is provided at the end of the photodiode (9), as shown in the following equation.

In this way, since the extraction electrode is provided near the center and the response of the brightness monitoring photodiode (9) is fast, even if the integration time is determined based on the output of the brightness monitoring photodiode (9), it will not be excessive. Appropriate integration can be performed without performing excessive integration that stores charges in the storage section (ST).

A capacitor (10-1) serving as storage means is connected to the brightness monitoring photodiode (9), and prior to integration of the image sensor (13), an FET (I0-
When the AGCRS signal is applied to the gate of 3), the capacitor (to-1) is charged to the power supply voltage VDD.

After the AGCRS signal is removed, the potential at the capacitor (IQ-1) drops due to charges generated in response to light irradiation. This potential is applied to a buffer (10-2
) is output as the AGCO8 signal.

The compensation diode (11) is provided to remove the dark output of the brightness monitor photodiode (9), and a light-shielding Aa film (11-ri) is provided on top of the compensation diode (11). The compensation diode (11) is designed to provide the same amount of output as the dark output of the brightness monitor photodiode (9), but if it has the same structure as the brightness monitor photodiode (9), requires the same area as the brightness monitoring photodiode (9), which leads to an increase in chip size.For this reason, the compensation diode (11) is designed as shown in FIG. 7(a). By making the N-type part consist of a number of parts separated from each other and aligned at regular intervals, and embedding these parts in the P-type part, the length of the PN junction at the surface where the dark output is generated can be reduced. (Perimeter length) La is increased so that the same amount of dark output can be obtained with a smaller size than the brightness monitoring photodiode (9).

The compensation diode (11) is connected to the capacitor (12-1
). This capacitor (+2-1) is connected to the FET (12-3) prior to integration of the image sensor (13).
) is charged to the power supply voltage VDD by the AGCR3 signal applied to the gate. However, after the AGCRS signal is removed, the potential of the capacitor (12-1) gradually decreases due to the dark output charge of the compensation diode (11). This potential is output as a DOS signal via a buffer (12-3). This concludes the description of the configuration of the image sensor (13).

Next, the overall hardware configuration will be explained along with the block diagram shown in FIG. 2 showing an image sensor, a microcomputer, and an interface circuit between them. Second
The cloth (14) in the figure is a microcomputer (14) which is arithmetic control means for controlling the drive of the image sensor (13).
μCon). This microcomputer (14)
The image sensor control unit (16) of the image sensor (
13) Outputs two signals MD, , MDt for switching between the four modes described below and two signals NBI, NBt for giving operation timing to the bus, and also outputs them from the I10 buffer (22). , TINT signal indicating whether integration is completed or not, and A/D of image sensor output
The ADT signal which is the logical sum with the ADS signal indicating the start of conversion is input, and the gain information Gl and G3 signals are input to the NB,
, NBt signal bus.

The circuit on the left side of the microcomputer (14) is
It is constructed on a 1-deep IC (integrator circuit). Among these, the I10 buffer (22) has the following functions.

That is, the above T [NT multiplied signal ADS signal is ORed and outputted as an ADT signal to the microcomputer (14). , NB, the signal is manually input from the microcomputer (I4), and when outputting it, Gl,
The function of outputting the G3 signal to the microcomputer (14), the signal level of the microcomputer (14), the frequency dividing circuit (19), the integral time control section (20), the signal processing timing generation section (21), and the transfer It has an interface function with a signal level in a circuit such as a lock generating section (30).

On the other hand, the mode selection circuit (23) is a circuit that decodes the MD, , MD2 signals and selects one of the following four modes. MDI-“L”.

When M D t = “L”, the mode selection circuit (23)
■ Sets only the Nl signal to "I-1" and selects the INI mode. The INI mode is a mode for initializing the image sensor (13). MD, -“L”.

When MD2="H", the mode selection circuit (23) is
Set only the T signal to "I4" and select the INT mode.

The INT mode is a mode in which the image sensor (13) performs integration. When MD I=“■(”, MD=“H”, the mode selection circuit (23) selects only the DDI signal as “I2
I” and select the DD+ mode. The DDI mode is a mode that starts reading out the image sensor (13), and is also a mode that performs sample and hold of the black reference pixel, which will be described later, using signals N B + and N B. MD = = "H", Ml) When t = "L", the mode selection circuit (23) sets only the DD2 signal to "I-1" and selects the DD2 mode. This is a mode in which the image sensor (13) is read and the read and processed output of the image sensor (I3) is sent to the A/D converter (15) of the microcomputer (14).Each mode The operation and functions of will be described later.

The above frequency dividing circuit (19) is a microcomputer (!4)
The basic clock CP generated by the clock generator (18) of
The image sensor (13) transfer lock φ1. The clock φ that is the source of φ. At the same time,
Integral time control section (20) and signal processing timing generation section (
21), a timing clock φ for synchronizing with the clock φ0 is generated.

The above clock φ. is sent to the transfer lock generation section (30), where the 8 signal sent from the integral time control section (20)
1.1 signal, RGICG signal and clock φ.

As a result, the clock φ8. φ, and serves as a transfer lock for the image sensor (13). The integral time control section (20) receives a timing signal N transmitted from the microcomputer (14) when in INI mode or INT mode.
Based on B, , NB, the AGCR9 signal, I3G signal, 91 (signal, RG [CG times signal) is generated in synchronization with the clock φ sent from the frequency dividing circuit (19), and the integration start operation is performed. Each signal is given to each part of the image sensor (!3) shown in Fig. 1.In addition, the integral time control part (!
20) is the integration completion signal VFLG from the brightness determination circuit (24), which is a subtraction means that changes from "L" to "H" when the integration of the image sensor (13) becomes appropriate, or the mode selection circuit (23) A BG multiplied signal is generated by the timing signals NB, NB, which are transmitted when the DDI signal from the DDI signal is "1", and the integration is completed.

Furthermore, this integration time control section (20) is configured so that the DDI signal is “
When the timing signal NB,

NI3. The signal SH multiplied by this is generated, and the operation to start reading the output from the storage section (ST) is performed. At this time, a signal for obtaining luminance information, which will be described later, an SH multiplied signal, and φa, φb, and φC1φd signals are transmitted to the luminance determination circuit (24). The brightness determination circuit (24) monitors the AGCOS signal and DO9G9 signal sent from the image sensor (13) and the light m irradiated to the image sensor (13), and when it is determined that the integration has reached an appropriate level. ni, V
A function to invert the FLG signal and convert the integration to VFL at low brightness.
If the G signal is an inverse signal inverter, determine the level of integration,
It has a function of outputting Gl and G3 signals for switching the gain of the image sensor (13) according to the level.

AGC differential amplifier circuit (25) is an image sensor (13)
This circuit amplifies the output signal O8 sent from.

In this AGC differential amplifier circuit (25), the PET (8) of the image sensor (13) is turned on by the 08R8 signal.
-3), the potential O8 immediately after the capacitor (8-1) is charged is sampled and held by the R8S/H signal sent from the signal processing timing generator (21), and then this potential O8 is transferred to the capacitor according to the lock. (8
-1) The difference between the potential O8 of the capacitor (8-1) which has dropped due to the generated charge of each pixel and transferred to the OB subtraction AGC difference which is the subtraction means is taken and amplified as a signal V os'. It is output to the dynamic amplifier circuit (26).

The gain of this OB subtraction AGC differential amplifier circuit (26) during amplification is switched by the G3 signal output from the brightness determination circuit (24). The above OB subtraction AGC amplifier circuit (2
6), differential amplification between the output of the black reference pixel and the output of the normal pixel without light shielding A12, that is, the effective pixel, and the output Vos
' Sample hold is being carried out. Since the photodiode (PD) always has an output in the dark, the pixel detected by the photodiode (PD) with AQ light shielding is used as the black reference pixel and the reference pixel for the dark output, and the output of the normal pixel is used as the reference pixel for the dark output. The value obtained by subtracting the black reference pixel component is the output of the image sensor (13). The OB subtraction AGC amplifier circuit (26) is an AGC differential amplifier circuit (26).
Since the output Vos' from 5) is repeatedly input in synchronization with the transfer lock, the signal processing timing generator (
21) Sample and hold the level of the signal output Vos' of the effective pixel using the OSS/I-1 signal sent from the
Also, the 0 signal sent from the signal processing timing generator (21)
According to the I3S/H signal, the output Vos' is sampled and bolded while the black reference pixel is being output. Above OB subtraction 8C
The amplifier circuit (26) calculates the sampled and held black base pixel output level Vos' from the sampled and held effective pixel output level Vos', and also switches according to the G3 signal output from the brightness determination circuit (24). The signal is multiplied by a gain, and outputted as a signal Vos below the analog reference voltage V rer.

The temperature detection section (27), which is a fixed range voltage output means,
Temperature is detected by the resistance divider circuit shown in Figure 3. This resistor divider circuit (27) includes a diffused resistor (32) formed by diffusion and a resistor (33) made of polynolylic resin (Poly-8i), which are designed to have equal resistance values at room temperature. There is. Each resistor (32), (
33) have different temperature coefficients, the output V TMP output from their connection point via the buffer (34) is:
It depends on the temperature around Vref/2. In addition, the analog switch (31) is "
"L" and turns off the analog switch (3I) to reduce current consumption.On the other hand, the second
The analog switch (28) shown in the figure is turned on in the DD2 mode, that is, in the case of DD2-"I-1", and conversely, the analog switch (29) is turned on in the case of DD2-"L". As a result, in the DD2 mode, the output Vou
The signal Vos is output as output t, and the signal VTMP is output as output V out in modes other than DD2 mode. The signal Vout is input to the A/D converter (15) in the microcomputer (14), where the analog reference voltage V
A/D conversion of analog output on the lower voltage side than rer
It starts with a T signal and converts it to digital data.

In this way, when the analog switches (28, 29) are switched and the OB subtraction AGC differential amplifier circuit (26) is outputting the signal Vos corresponding to the used pixel, the signal is transferred to the A/D converter ( I5), while in other cases, the voltage V T within a certain range from the temperature detection part (27)
Since MP is manually input to the A/D converter (15), OB
The negative output generated by subtracting the output corresponding to the black base pixel from the output corresponding to the unused pixel from the subtraction AGC differential amplifier circuit (26), or the output of the used pixel after the pixel readout is completed, produces black 2! Even if negative outputs are generated due to subtraction of the outputs of the pixels, they are not input to the A/D converter (15) and are output from the temperature detector (27) to a voltage V TMPh (A / ) within a certain range. The D converter (I5) is manually powered.Therefore, the A/D converter (15) does not exceed the human dynamic range and there is no risk of damage.

This concludes the explanation of the hardware configuration.

Next, the operation of the image sensor (13) described above in each mode will be explained in detail.

First, the initialization mode will be explained.

The microcomputer (14) is MDI-“L”.

When MD2="L" is output, the mode selection circuit (23)
In this case, only the INr signal is set to “T”, and the integral time control section (2
0) to notify that it is in initialization mode (INI mode). INr mode is image sensor (13)
This mode is for discharging unnecessary charges from the image sensor (!3) immediately after the power supply 5 is turned on. Image sensor (
13), after the power is turned on, the photodiode (PD), which is a potential well, the storage section (ST), and the transfer register (
Unnecessary charge is accumulated in each of the image sensors (RG), and it is necessary to quickly discharge this charge and start up the image sensor (I3) so that it can be used. Therefore, in order to quickly discharge unnecessary charges, we set the INN mode and
The bottom structure of the image sensor (13) is shown in FIG.

The following will explain the potential diagram in FIG. 3 and the time chart in FIG. 4. In FIG. 3(a), the left side includes an overflow drain (OD2), a barflow gate (OG), and a photodiode (PD).

Barrier gate (I3G), storage section (ST), transfer gate (SH), transfer register (RG), integral clear gate 1-
(RG I CG), Over ICl-Druin (oD
l). Barrier Gate (r3G)! Multi-feed gate (SI-1), integral clear gate (RGICG)
When voltage is applied to each gate and transfer register (RG) (φ1 is applied to transfer register (RG))
, as shown in Figure 3(b), the potential of 1 is designed so that PD>BG>ST>Ssummer1>RG>nG I CG>OD 1, and the photodiode (PD)
, the storage section (ST), and the transfer register (RG) are discharged to the overflow drain (ODl) at this time. This operation will be explained along the time chart.

The state in FIG. 4(a) corresponds to FIG. 3(a).

At this time, N13. = “L”, N B x = “L”
In the state of , barrier gate (BG), transfer gate C3fl
), no voltage is applied to each gate of the integral clear gate (RGICG), and no voltage is applied to each gate of the photodiode (P D
).

Unnecessary charges are accumulated in each section of the storage section (ST) and transfer register (NC). When both N B r and N B x are "L", the integral time control section (20) that controls the image sensor (13)
It does nothing for .

The microcomputer (14) is N13. = “I-1”
.

When outputting NB, -“L”, the integral time control section (20)
is the clock φ sent from the frequency dividing circuit (19). As shown in FIG. 4(b), S H="I-I
”.

BG="H" and RG I CG="H" are output to the image sensor (13). Furthermore, the S I-1 signal, 11
01 CG signal is also sent to the transfer lock generation unit (30), and the transfer lock generation unit (30) transfers the OR output of the SI (signal and clock φ) and sets it as lock φ1, and also the RGICG signal and φ. Transfers the Noah output of and locks φ.

In the case of S H = "H" and RG I CG = "14", the transfer lock to the image sensor (13) is stopped in the state of φ, = "H", φ, - "L". ing.

And the image sensor (13) is 5l-1, BG, R
GI CG, φ1. By each signal of φ, Fig. 3(b)
As shown in the figure, unnecessary charges are discharged from the photodiode (PD), storage section (ST), and transfer register (RG).

The microcomputer (14) then NB, = “H”
, NB, after outputting ="H", N13. = “shi”.

N [Output 3-“H”. In response to this, the integral time control section (20) sets the clock φ. and returns the SH double signal and BG double signal to "L" (FIG. 3(C), FIG. 4(C)). On the other hand, in the transfer lock generation section (30), Sl
When the l signal returns to "L", transfer lock φ1 starts to move, and transfer lock φ is at "L".

At this time, the potential difference between the transfer register (rtG) and the overflow drain (ODI) increases, promoting the discharge of unnecessary charges from the transfer register (RG), and completely discharging them to the overflow drain (ODI) (third
Figure (d), Figure 4 (d)). Also, at this time, since the transfer lock φ remains stopped at "L", another transfer register (RG) adjacent to the above transfer register (RG) to which the transfer lock φ is applied is connected to the above register. (RG)
There is no such thing as 27 where unnecessary charges flow into.

After the timer measures that a predetermined period of time has elapsed, the microcomputer (14) controls NB, , N13 . Together “
The integral time control section (20) thereby returns φ
The RGICG signal is set to "L" in synchronization with G. Then, the voltage applied to the rtG [CG voltage] of the image sensor (I3) becomes zero, and this integral clear gate (RGI
CG) closes. At the same time, the transfer lock generation section (
30), as the RG I CG double signal becomes “L”, the transfer lock φ also starts moving (Fig. 3 (e), 4
Figure (e)). With this, one cycle of unnecessary charge discharging operation is completed.

Normally, when initializing the image sensor (13), the above-described unnecessary charge discharge operation is repeated several cycles, and then the initialization mode is ended.

In the present invention, the structure in which an integral clear gate (RGICG) is connected to each register (RG) eliminates the need to discharge unnecessary charge from each register (RG) by transferring it from the register (RG). It is possible to shorten the time required for one cycle of the unnecessary charge discharging operation, and to shorten the time allocated to the initialization mode.

Next, the second mode, the integral mode, will be explained.

The microcomputer (14) is MD, = “L”.

When MD = “H” is output, the mode selection circuit (23)
In this case, only the INT signal is set to “11”, and the integral time control section (2
0) to notify that it is in integral mode (INT mode). In the INT mode, the image sensor (13) starts integrating and ends the integration during high brightness.

The operation will be explained along with FIGS. 5 and 6. The start operation of integration is the discharge operation of unnecessary charges at the time of initialization, and the I3G
Exactly the same except for the signal. BG double signal NB, -“1
■", NB2-"L" is the microcomputer (14)
After outputting φ, the integral time control section (20) outputs φ. (In the figure, this is the rising time of φ).
t”. This is the same as in the lNl mode. However, the microcomputer (!4) is
When outputting B, -“L”, N B t-“H”,
In lNl mode, φ. BG double signal again in synchronization with “
However, in INT mode, the BG double signal “■
1".The BG multiplication signal remains "1" at the end of the integration, which will be described later.
It becomes “L”.

At the time of FIG. 5(C) and FIG. 6(c), the transfer gate (St
When the gate voltage of the transfer gate (SLI) becomes zero, the transfer gate (SLI
) returns to a higher potential than the photodiode (PD), storage section (ST), and overflow gate (OG), and from this point on, the charge generated in the photodiode (PD) flows into the storage section (ST) and is accumulated. (ST), and the image sensor (!3) starts to integrate.

On the other hand, the time point at which the integration ends is monitored by the output of the brightness monitoring photodiode (9). The operation of the brightness determination circuit (24) will be explained below, and the operation of completing the integration will be explained.

The integration time control unit (20) transmits the AGCR9 signal to the image sensor (13) at the same timing as the SH multiplication signal at the start of integration.
). As shown in FIG.
The signal is transmitted through an FET (10-1) connected to a capacitor (10-1) connected to a photodiode (9) for brightness monitoring.
-3) and the gate of the FET (12) connected to the capacitor (+2-1) connected to the compensation diode (11).
-3) is applied to the gate. By applying the AGCR3 signal, the capacitor (10-1), (
+2-1) is charged to approximately the power supply voltage VDD. When the AGCrtS signal becomes "L" at the same timing as the SH double signal, the power supply is cut off, and from then on, the brightness monitoring photodiode (9) generates a charge according to the amount of light irradiated and is connected to it. The potential of the capacitor (10-I) begins to drop in accordance with the generated charge. On the other hand, the compensating diode (11) generates a charge due to its dark output, and the potential of the capacitor (12-1) connected thereto also begins to drop in accordance with the generated charge. Each potential is passed through each buffer (IO-2), (+2-2),
The brightness determination circuit (24) in FIG. 2 is outputted to the analog circuit shown in FIG. 8. In Figure 8, the AGCO8 signal is input to the positive input of the operational amplifier (43), and DO5
The signal is input manually to the negative input of the operational amplifier (43),
The differential output is output from the operational amplifier (43). The output V43 of the operational amplifier (43) is expressed by the following formula. 'V,=Vrer-(DOS-AGCOS) This output V4
3 is a luminance determining means, which is manually operated by the minus human power of the comparator (45).

On the other hand, the positive input of the comparator (45) is connected to the FET (46°47.
A constant voltage generated by resistance division according to 48.49) is supplied. During integration, only φd is "11", the FET (49) is turned on, and the supplied constant voltage is V49-(VrefVth). The output of the comparator (45) is “I” when V 43 < V 48.
-1". In other words, Vre"-(DOS-AGCOS)<Vref-Vth
When DOS-AGCOS>Vth, "■]" is displayed.

(DOS-AGCOS) indicates a voltage dropped by light irradiation from the brightness monitoring photodiode (9) (the dark output component is compensated by the output of the compensation diode (II)). Immediately after the start of integration, the amount of light irradiated to the brightness monitor photodiode (9) is insufficient, and DOS-
AGCO8 and O, and the output of the comparator (45) (
VFLG) becomes “I,”. During the integration (DOS
-AGCOS) becomes larger than the voltage v th, the integration for the image sensor (13) becomes appropriate,
The output (VFLG) of the comparator (45) is inverted from "L" to "■(". As shown in the time chart of FIG. 6, the integral time control section (20) controls the output of the comparator (45). When VFLG is inverted, the BG double signal is set to "L". When the BG double signal becomes "L", the signal shown in Fig. 5 (e
), the potential of the barrier gate (BG) becomes larger than the potential of the photodiode (PD), which prevents the charge generated in the photodiode (PD) from flowing into the storage section (ST). (ST)
The charges accumulated in the VFLG signal are “H”, that is, the BG
When the double signal becomes "L", it is held and the integration ends. The charge generated after the completion of integration is transferred to the photodiode (r'D
), and even if the accumulation progresses, it crosses the overflow gate (OG), which has a lower potential than the barrier gate (BG), and is discharged to the overflow drain (OD2), as shown in Figure 5 (e). , storage section (
ST).

Further, the integration time control unit (20) sets the BG multiplied signal to "L" and simultaneously sets the TINT signal to "off", and notifies the microcomputer (14) of the inversion of the TINT signal via the ADT voltage. This concludes the explanation of the integration start operation in the integration mode and the integration end operation during high brightness.

Next, the third mode, data read mode 1 (DDI
mode).

The microcomputer (14) is MD, = “11”.

When M D t = "I-1" is output, the mode selection circuit (23) sets only the DD+ signal to "■1" and notifies the integration time control section (20) that it is the DDI mode.

DD! The mode performs integration end operation at low brightness, and
This is a mode in which the readout operation of each pixel data of the image sensor (13) is performed.

First, the integration termination operation at low luminance will be explained based on the time chart of FIG. 22. When the subject brightness is low, it may take a long time until the brightness determination circuit (24) determines that the appropriate integration time has been reached. If integration is performed for a long time, the dark output increases, leading to deterioration of the S/N ratio. Furthermore, an extremely long integration time is inconvenient from a system perspective.

For example, when used in a focus detection device for a camera, the focus detection cycle becomes long, resulting in the inconvenience that the focus detection cannot follow the movement of the subject. Therefore, the longest integration time allowable within the microcomputer (14) is set in advance, and if the TINT signal output to the ADT voltage has not been inverted even after this time, the MD
, ="[l"3MD, -"g" are output, the mode shifts to the DDI mode, and the operation of terminating the integration is performed in the DDI mode.

In the DDI mode, the integral time control section (20) controls NB, -
H''.

NBt-“L” signal to microcomputer (!4)
When the signal is received from the BG signal, the BG multiplied signal is immediately set to "L". As a result, as in the previous case, the barrier gate (B
The potential of 'G) becomes higher than that of the photodiode (PD), the charge generated in the photodiode (PD) stops flowing into the storage section (ST), and the integration ends (FIG. 22).

Next, the operation to start reading out each pixel data of the image sensor (I3) will be explained. Regardless of whether the brightness is low or high, the microcomputer (14
) is NB, = “■4”, NF2. ="L", the integral time control section (20) locks the transfer φ. Synchronize and transfer lock φ. SH at the timing of “I-1”
Generate a signal pulse (Figure 6 or Figure 22). As a result, a pulse voltage is applied to the S I-1 gate of the image sensor (13), and each pixel stored in each storage section (ST) is The signal charge is transferred to the transfer register (RG).Then, the signal charge of each pixel is transferred and read out by the transfer lock φ1.φ.Transfer of the signal charge accumulated in each storage section (ST) To transfer to the register (RG), the microcomputer (!4) sets NB, -“H” in CDI mode.
, NBI-"L" is output. At this time, it is necessary that the transfer register (RG) returns from the unsteady state after the start of integration and becomes a steady state.

In a steady state, each transfer register (RG) has a dark charge of 23
It is accumulated as shown in the figure. This dark charge is the sum of the dark charge generated in the potential well of each transfer register (RG) and the dark charge of the intermediate registers that are sequentially transferred. At the start of integration, the integral clear gate (IIGI
A voltage is applied to the gate voltage of the transfer register (R
The integral clear gate (RGICG) between G) and overflow drain (OD+) is turned on, and the transfer register (
RG) are all cleared. After the integral clear gate (rtGrcG) is turned off, the transfer lock φ.

Every time one period passes, the dark charge in the transfer register (RG) reaches a steady state starting from the left side of FIG.

It takes a time equal to the number of pixels (N) x one transfer lock cycle ('r) until all transfer registers (rtG) return to a steady state.

When an sti pulse is generated in an unsteady state, the dark charge component of the transfer register (RG) in the charge taken out as an output is shifted by the pixel in the unsteady state, so that a correct signal cannot be taken out. Therefore, the SII pulse must be generated at least after the I'tGICG signal changes from "I" to "L" and after the number of pixels x one transfer lock period (NXT) has elapsed. It won't happen.

At high brightness, integration is often completed within one period (NXT), but since the integration is terminated by closing the barrier gate (I3G), It is possible to make the occurrence wait.

Next, regarding the processing of the read pixel output, FIG.
This will be explained below with reference to FIG.

The signal charge of each pixel of the image sensor (I3) is φ, −
At the timing of "L", φ, -"I-1", it is transferred to the capacitor (8-1) shown in FIG. In the signal processing timing generation section (21), prior to the transfer of this signal charge, as shown in FIG.
08RS signal pulse is generated at the timing of 2"L", and this pulse is applied to the gate of FET (8-3) shown in Fig. 1 to charge the capacitor (8-1) to approximately the power supply voltage and reset it. . φ1-“L”.

When the signal charge is transferred at the time when φ becomes -“H”, the voltage of this capacitor (8-1) decreases due to the signal charge, and the output O8 of the image sensor (13) becomes the 12th
The output is as shown in the figure. AGC differential amplifier circuit (
25), the RSS/HSS/up and reset voltage levels sent from the signal processing timing generator (21) are measured by the sample and hold circuit consisting of the FET (52), capacitor (53), and buffer (51) shown in Figure 11. According to
It is stored and input to the plus input of the operational amplifier (54).

On the other hand, the O8 signal is input to the negative input of the operational amplifier (54) via the buffer (50), and is input to the negative input of the operational amplifier (54).
5, 56, 57, 58).

The output differentially amplified with the gain determined by the G2 signal (see FIG. 1t) is output from the operational amplifier (54) as Vas' (see FIG. 12).

Next, the determination of the integral level will be explained.

If the integration is forcibly terminated when the brightness is low, the level of the pixel output of the image sensor (13) will naturally be lower than when it is appropriate. Therefore, in this case, the level of integration is detected using the brightness determination circuit (24) described in 071, and a gain is applied to the output of the image sensor (13) according to the result, so that the output is always at an appropriate level. I'm trying to get it.

The following will explain the brightness determination analog circuit of FIG. 8, the pulse timing chart of FIG. 9, the brightness determination logic circuit of FIG. 10, and the truth table of FIG. 24. Note that the brightness determination circuit (23) is constituted by this brightness determination analog circuit and the brightness determination logic circuit. As shown in FIG. 8, the operational amplifier (43) outputs an output (43=Vref-(DOS-AGCOS) corresponding to the intensity of light emitted), and a comparator (45) serving as a brightness determination means outputs
is input to the negative input of When determining the integral time, φd is applied as shown in FIG.
-V th) is manually operated. Now, when the SH pulse occurs, latch 1 (73) and latch 2 (
74) and latch 3 (75) are all set. After that, as shown in FIG. 9, when the φC pulse is generated,
The FET (43) in Figure 8 turns on, and the comparator (
The positive input of 45) is (Vref-Vth/2)
is done manually. Here, Rashi (DOS-AGCOS)>
If Vth/2, the output VFLG of the comparator (45) is “■
1'', and the AND gate shown in Figure 1O (
The output of FET (47) 7!l (on Therefore, the positive human power of the comparator (45) is (V
rer-V Lh/4) is input. Here, if DOS-AGCOS)>Vth/4, the output VFLG of the comparator (45) is “H”.
”, and in FIG. 10, the output of the AND gate (7I) becomes “11”, and the latch 2 (74) is set.Furthermore, as shown in FIG. FET (46) in diagram S turns on,
The positive force of the comparator (45) is (Vref-V
th/8) is input. Here, (DOS-AGCO
S)>Vth/8, the output VFLG of the comparator (45) is “■
1", the output of the AND gate (72) shown in FIG. 1O becomes "H", and the latch 3 (75) is set.

For each of the above cases, Gl
, G3 signal is generated. Based on this signal, the gains are selected as shown in the table below, each with approximately the appropriate level of Vos.
is obtained.

In this way, by sequentially turning on PET (49, 48, 47, 46), the reference voltage generation circuit (RVC)
generates multiple reference voltages, one comparator (45) can judge the brightness at multiple stages, and the image sensor (
I3) The number of comparators formed on the same chip can be reduced.

The FET (44) shown in Figure 8 is in INT mode and DD mode.
This is a switch for supplying power to the resistance divider circuit, that is, the reference voltage generation circuit (RVC) only in the I mode.

This FET (44) allows the reference voltage generation circuit (Rv
C) is energized only when brightness determination is necessary, reducing current consumption. This saving effect on current consumption becomes greater at high brightness because the integration time becomes shorter than the readout time.

As shown in FIG. 11, the signal Vos' is connected to the FET (60)
, a capacitor (62), and a buffer (64).
65) is input to the negative input. This signal Vos'
Holding is the signal processing timing generation section (2I)
This is performed by the O9S/If pulse signal generated at the timing of signal charge transfer from φ1=“L” to φ2−“H”. The signal os' is also input to a sample and hold circuit consisting of a PET (59), a capacitor (61), and a buffer (63). This sample hold circuit performs sample bolding of the output of the black reference pixel subjected to AI2 light shielding as shown in FIG. The pulse providing timing for sample and hold is the OBS/II signal shown in FIG. 12, which is generated in the sequence shown below.

As shown in FIG. 2.12, after shifting from the INT mode to the DDl mode, an ADS signal that provides the timing to start A/D conversion appears in the ADT signal. The microcomputer (14) measures the timing of sampling and holding the black reference pixel output while monitoring this signal. The microcomputer (14) outputs NB while outputting the black reference pixel.

= "[I", NBt"'"■4", and the signal processing timing generating section (21) thereby sets the OBS/H signal to "Hl". Continued development of microcomputers (
14) is NB until the next ADS signal rises.

= “L”, NB! = “H”, and the signal processing timing generation unit (21) thereby outputs the OBS/H signal “L”.
”.As a result of the above, the FET (59) shown in FIG.
, a capacitor (61), and a buffer (63) holds the input black reference pixel output and inputs it to the negative input of operational amplifier 2 (65). After sampling and holding the black reference pixel output, the output of operational amplifier 2 (65) is subtracted by an amount corresponding to the held black reference pixel output, and FE'r (66) to (6
g) (1) G3 connected to the gate. The signal V is amplified by the gain determined by the G4 signal (see the attached table in Figure 11)
It is output as os (Fig. 12).

As shown in "2" below, the output signal O8 of the image sensor (B3)
is double sampled in the AGC differential amplifier circuit (25) and the OB subtraction AGC differential amplifier circuit (26), the reset level is subtracted from the signal level, a signal not affected by reset noise is extracted, and further, The black reference level is subtracted from the signal that is not affected by reset noise, and the dark output is removed from the output of each pixel Vo.
s is obtained. Furthermore, this output Vos is determined according to the average level of each pixel output in the AGC differential amplifier circuit (25) and the OB subtraction AGC differential amplifier circuit (26) with respect to the output O8 of the image sensor (B3). It is created by applying a gain of x8 to x64 so that In this way, since the two amplifier circuits (25, 26) amplify in two stages, the range of resistance values connected to the operational amplifier (54, 6/l) is smaller than when amplifying with one amplifier circuit. This reduces the area occupied by the resistor.

Next, the gain of the operational amplifier (54) of the AGC differential amplifier circuit (25) and the gain of the operational amplifier (65) of the OB subtraction AGC differential amplifier circuit (26) shown in FIG. 11 will be described. Here, for the output O8 of the image sensor (13), X8. I16. In order to switch the gain of I32゜I64, operational amplifier 1 (54) has two stages, operational amplifier 2
(65) performs two-stage gain switching. In this case, the operational amplifiers (54) and (65) always have an offset problem. When applying gain in two stages, the first stage gain is GNI, the second stage gain is GN2,
Assuming that the offset of each operational amplifier is ΔV, the individual horn is Vi, and the output is Vo, the output is expressed by the following formula.

Vo=((Vi+△V)xGNl+△V) X GN2
=VixGNlxGN2+△V * (GN1xGN2
+0N2)= (Vi +△Y) x GNI x G
N2+ΔVXGN If the total gain GNIXGN2 of the 22-stage operational amplifier does not change, an offset due to GN2 appears in the second term (Δ■XGN2) in the above equation.

That is, the smaller GN2 is, the smaller the offset of 1.-tal becomes.

Therefore, the first stage gain GNI is the second stage gain GN2.
Although the offset can be suppressed by choosing a value higher than , the offset remains even with this measure. For this reason,
As shown in FIG. 11, the operational amplifier 2 (65) in the latter stage softens the level based on the voltage that is lowered by the potential of the diode (99) lffW, which is the bias means, from the reference voltage V ref, so A/D conversion is always possible. In this way, the offset is made to appear on the lower voltage side than the reference voltage V ref.

After the OB subtraction AGC differential amplifier circuit (26) samples the signal representing the black base pixel and before outputting the signal representing the effective pixel, the OB subtraction AGC differential amplifier circuit (26) receives a sample representing the second black base pixel subjected to A12 light shielding before outputting the signal representing the effective pixel. It is outputting a signal. Since the previously held black reference pixel is subtracted from the output representing the second black reference pixel, an output matching the reference voltage Vrer is obtained if there is no offset of the operational amplifier. However, since the output of the operational amplifier 2 (65) always has an offset VofTset on the lower voltage side than the reference voltage V ref, the output becomes (V rer - Vofrset). This is A/
When D-converted, a signal corresponding to VofTset is obtained as digital data. Thereafter, the output of the effective pixel is subtracted by this VofTset by the calculation of the microcomputer (14).
The data input in step 4) is substantially the same as the data with the offset component removed.

Next, the DD2 mode will be explained.

In the DD2 mode, the image sensor (13) is not caused to perform any active operation.

Therefore, the NB connected to the I10 buffer (22),
, NB2 is switched, a Gl signal is output to NB, a G3 signal is output to NB2, and gain information of the output of the image sensor (B3) is notified to the microcomputer (14). This I10 switching is performed by the DD2 signal.

Only in the DD2 mode, the signal output as Vout is the output Vos of the image sensor (B3).

The pixels used in this system are image sensors (13)
are pixels detected in two separate regions of
No photodiode (PD) is provided between the two regions. When outputting the output of these pixels to the A/D converter (15) as Vout, there is a problem that will be described later, so by switching between DD2 mode and DDI mode,
Vos is output as Vout only when valid pixels are output. The output Vos' of the AGC differential amplifier circuit (25) is the output component Vo corresponding to the optical signal when the effective pixel is output.
s' (sig) and dark output component V 6g' (dark
) expressed as the sum of (V os' = V os'
(sig) tenVos' (dark)). OB
V os' (d
ark) is subtracted, and Vos= V rer −G N 2 X (Vos'
-Vos' (dark)) as the A/D converter (1
5) is output.

At this time, the output of the pixel from which the photodiode (PD) has been removed has neither an output corresponding to an optical signal nor a dark output component, so Vos'=0. Here, when Vos' (dark) is subtracted by the OB subtraction AGC differential amplification (26), Vos=Vref-GN2 x(0-Vos'(dark)
k))>Vref, and the reference voltage V that can be A/D converted
Contrary to the voltage side lower than rer, Vos is the reference voltage Vre
"The voltage will become higher, exceeding the dynamic range of the A/D conversion, and may cause damage to the A/D conversion device, that is, the A/D conversion unit (15). Now, analog switches (28), (2
9) to constantly output an A/D convertible temperature detection output VTMP. In this way, the dynamic range of A/D conversion is always maintained by outputting Vos by setting DD2 to "H" only when outputting a valid pixel, and outputting VTMP by setting DD2 to "L" when outputting an invalid pixel. A/D conversion is performed within the unit.

This concludes the explanation of the DD2 mode and the explanation of the first embodiment.

Next, a second embodiment will be described in which the means for removing the dark output component in the first embodiment is modified. here,
Only the differences from the first embodiment will be explained with reference to the block diagram in FIG. 14 and the circuit diagram of the AGC differential amplifier circuit in FIG. 15.

First, the block diagram of FIG. 14 showing the second embodiment and the block diagram of FIG.
As shown by the differences in the block diagram of FIG. 2 illustrating an embodiment of the analog reference voltage V re
The difference from the first embodiment is that "f" is output from the AGC differential amplifier circuit (125). Also, in FIG. 14, the OB subtraction AGC differential amplifier circuit in the first embodiment is removed. There is.

The operation of the second embodiment will be explained with reference to FIG. As in the first embodiment, the image sensor (13) outputs the dark output, that is, the output of the black reference pixel, before outputting the effective pixel. Here, FE in the AGC differential amplifier circuit (125)
T (159), capacitor (161) and buffer (
163) samples and holds the output of the black reference pixel using the OBS/I-1 pulse. In the first embodiment, the held output was connected to the negative input of operational amplifier 2 (65) and subtraction was performed by operational amplifier 2 (65), but the second
In the embodiment, the held output is output as V rer'. This Vrer' is the A/D converter (
115) as an analog reference voltage, and the A/D converter (115) A/D converts the input voltage using this voltage as a reference. That is, since the difference between the input Vout and the reference voltage Vrer' is taken and converted into a digital value, this is equivalent to subtracting the black reference pixel output within the A/D converter (+15).

Therefore, the problem of operational amplifier offset that occurs when the operational amplifier subtracts the black reference pixel output from the effective pixel output, shifts the level, and uses this as a reference voltage for the A/D conversion section does not occur in this embodiment.

In addition, the output of the black reference pixel, which is sampled and held by the sample-and-hold circuit consisting of the FET (160), the capacitor (162), and the buffer (164), and the output of each effective pixel are the outputs of the operational amplifier 2 (165). Since these differentials are taken within the A/D converter (115), the offset of operational amplifier 2 (165) is completely removed. Therefore, in the second embodiment, the dark output of the image sensor (13) is removed and the operational amplifier 2 (16) is removed simultaneously.
5) Offset removal is performed.

Next, a third embodiment will be described with reference to FIGS. 16, 17, and 18. This third embodiment differs from the first and second embodiments in the dark output removal means.

First, let us look at the block diagram of the third embodiment (Fig. 16) and the block diagram of the first embodiment.
Differences from the block diagram of the embodiment (FIG. 2) will be described.

In the third embodiment, the sample bold pulse 0I3S/l[ of the black reference pixel is input to the A/D converter, that is, the A/D converter (215), and the OB subtraction AGC differential amplifier circuit is removed. There is. In this third embodiment, subtraction of the black reference pixel is performed within the A/D converter (215).

FIG. 18 shows the A/D converter (215), and this A/D converter (215)
The conversion section (215) includes an A/D conversion circuit (206) and an internal circuit provided on the same chip. In FIG. 18, the output of the image sensor manually inputted as Vin consists of the output of a black base pixel and the output of the effective pixel following this. The output of the black reference pixel is F'ET (20I) using OBS/H pulse.
), a capacitor (202) and a buffer (203). Then, the effective pixel output input thereafter is inputted to the A/D conversion circuit (206) after subtracting the sampled and held black reference pixel output by an operational amplifier (205) which is a subtracting means.

In this way, the operational amplifier (205) calculates the difference between the effective pixel output and the black reference pixel output and converts it into A/D, reducing the processing on the image sensor (13) side and simplifying the circuit configuration. .

FIG. 17 shows an AGC differential amplifier circuit (225).

In the first embodiment, there was a sample and hold circuit for the output of the black reference pixel, but in the third embodiment, this is removed. Further, as in the second embodiment, since the black reference pixel output and the effective pixel output are output from the same operational amplifier (+65), the offset of this operational amplifier (165) is completely canceled.

Next, a fourth example in which the dark time output removing means is different from the above-mentioned embodiment.
An example will be explained. FIG. 19 is a hardware block diagram according to the fourth embodiment. This is different from FIG. 16, which is a block diagram of the third embodiment, when the reference voltage V re
The difference is that f is not manually input to the A/D converter (315), and the AGC differential amplifier circuit (225) has exactly the same configuration as the third embodiment.

FIG. 20 shows the A/D converter (315), and this A/D converter (315)
The conversion section (315) includes an A/D conversion circuit (405) and an internal circuit provided on the same chip. While the image sensor (13) is outputting the black reference pixel,
The OBS/I-1 pulse is given to the /D converter (315), and the output of the black reference pixel input to the voltage Vin is sent to the FET (401), the capacitor (402), and the buffer (
403) is sampled and held by a sample bold circuit. The held black reference pixel output is input to the A/D conversion circuit (405) as an analog reference voltage (V ref' ). From then on, the effective pixel output of the image sensor (13) manually applied to the voltage Vin is:
As in the second embodiment, the bolded black reference pixel output (Vref') is subtracted and then A/D converted.

This removes the dark output component.

As described above, in this fourth embodiment, the black reference pixel output is sampled and held, and the black reference pixel output is used as the analog reference voltage (V ref') to be applied to the A/D conversion circuit (405).
) performs A/D conversion, an operational amplifier for level-shifting the black reference pixel output to the reference voltage is not required, and furthermore, the level shift offset becomes zero.

<Effects of the Invention> As is clear from the above, the A/D converter of the present invention has a sample-hold means for sampling and holding an input voltage, and a voltage sample-and-hold between another input voltage and the sample-and-hold means. Since the subtraction means that performs subtraction and the A/D conversion circuit that A/D converts the output of the subtraction means are provided on the same chip, the dip area on the image sensor side can be reduced and the processing on the image sensor side can be reduced. It can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the image sensor in the solid-state imaging device of the present invention, FIG. 2 is a block diagram of the fixed imaging device of the first embodiment of the invention, and FIG. 3 shows the potential structure of the image sensor at the time of initialization. 4 is a time chart of signals in the initialization mode of the first embodiment, and FIG. 5 is a time chart of the signals in the initialization mode of the first embodiment.
Fig. 6 is a time chart of signals in integral mode, Fig. 7 is a structural diagram of an n-use diode, Fig. 8 is a circuit diagram of a luminance judgment analog circuit, and Fig. 9 is a diagram of the luminance determination analog circuit. A time chart of signals at the time of judgment, Fig. 10 is a circuit diagram of the brightness judgment logic circuit, Fig. 11 is a circuit diagram of the AGC operational amplifier circuit and OB subtraction AGC operational amplifier circuit in the first embodiment, and Fig. 12 is the pixel output. 13 is a circuit diagram of the temperature detection section, FIG. 14 is a block diagram of the solid-state imaging device of the second embodiment, and FIG. 15 is a circuit diagram of the AGC-operated amplifier circuit of the second embodiment. FIG. 16 is a block diagram of the solid-state imaging device of the third embodiment, FIG. 17 is a circuit diagram of the AGC operational amplifier circuit of the third embodiment, FIG. 18 is a circuit diagram of the A/D conversion section, and FIG. Fourth
A block diagram of the solid-state imaging device of the embodiment, FIG. 20 is a circuit diagram of the A/D converter of the fourth embodiment, FIG. 21 is a structural diagram of the image sensor, and FIG. 22 is a diagram of the integration mode of the fourth embodiment. A signal time chart, FIG. 23 is a diagram explaining the transfer of dark charges, and FIG. 24 is a diagram showing the truth table of the brightness determination logic circuit. PD...Photodiode, BG...Barrier gate, ST...Storage section, SH...Shift gate, RG...
...Transfer register, RG I CG... Integral clear gate, 14... Microcomputer, 20... Integral time control section, 23... Mode selection circuit, 24...
Brightness determination circuit, 30... transfer lock generation section. Patent applicant: Minolta Camera Co., Ltd. Agent Patent attorney: Aohaku Ao and 2 others Peripheral length Lt) Figure 7 Ff1 & La LO's 7.7Ll) Figure 921 GICG

Claims (1)

[Claims] (1) A sample and hold means for sampling and holding an input voltage, a subtraction means for subtracting another input voltage and the voltage sampled and held by the sample and hold means, and A/D converting the output of the subtraction means. An A/D conversion device that includes a /D conversion circuit and a D conversion circuit on the same chip.