JPH01205685A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent the cutting down of the picture element output of an image sensor by including a bias means to level-shift offset the output of an amplifying circuit in one direction in which the output can be A/D converted more than the analog reference voltage of an A/D converting part. CONSTITUTION:An amplifying circuit 26 amplifies the output of the image sensor and outputs the amplified output, and the output is made into the one level-shift-offset hy a bias means 99 in one direction in which the output can be A/D converted more than analog reference voltage Vref of the A/D converting part. Consequently, at the A/D converting part, since a signal inputted from the amplifier 26 is outputted in the direction in which a level shift offset can be A/D converted all the time, a clip block, etc., for the picture element output of the image sensor never occurs. Thus, since the signal is outputted in the direction in which the level shift offset can be A/D-converted all the time, the so called cutting down never occurs for the picture element output outputted from the image sensor.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a solid-state imaging device used in an automatic focus detection device of a camera or the like.

<Prior art> It is conventionally known that the output of a differential amplifier is A/D converted by an A/D converter, and the output of this A/D converter is taken into a microcomputer to perform arithmetic processing. (Japanese Unexamined Patent Publication No. 62-83627).

By the way, in an automatic focus detection device using a CDD (charge coupled device) type image sensor, the output of this image sensor is A/D converted by an A/D converter, and the output after this A/D conversion is The output is taken into a microcomputer to perform calculations. And normally, the output of such a CDD type image sensor is 1
After being amplified by an amplifier circuit at ~2 volts, A/D conversion is performed. In order to perform this A/D conversion, A
It is necessary to match the output level of the image sensor to the analog reference voltage input to the /D converter.

In this way, when level shifting is performed to match the zero output level of the image sensor with the analog reference voltage of the A/D converter, there is an offset, and this offset makes A/D conversion impossible. If this occurs in a certain direction, part of the output of the image sensor will be clipped and A/D converted.

Therefore, an object of the present invention is to provide a solid-state imaging device having an image sensor, an amplifier circuit, and an A/D converter, in which a level shift offset generated on the output side of the amplifier circuit is always caused by an A/D converter.
The purpose is to prevent part of the output of the image sensor from being clipped by allowing D conversion to occur in one direction.

Means for Solving the Problems> In order to achieve the above object, the present invention provides the following features:
As illustrated in the figure, there is a photoelectric conversion section (PD) that generates charges corresponding to each pixel, a storage section (ST) that accumulates the charges generated in the photoelectric conversion section (PD), and a storage section (ST) that generates charges corresponding to each pixel.
An image sensor (13) having a sequential transfer register (RG) for sequentially transferring charges of T), and an image sensor (13) having
an amplifier circuit (26) for amplifying the output of the amplifier circuit (13); and an arithmetic control means (1) that converts the output of the amplifier circuit (26) into a
4), the amplifier circuit (26) outputs an analog reference voltage (V r ) of the A/D converter (15).
The present invention is characterized in that it includes bias means (99) for performing a level shift offset in one direction from which Δ/D conversion is possible.

Effect> When the photoelectric conversion part (PD) of the image sensor (13) is irradiated with light, a charge is generated in this photoelectric conversion part (PD),
This charge is stored in the storage section (ST).

The transfer register (RG) sequentially transfers and outputs the charges in the storage section (ST). The amplifier circuit (26) is an image sensor (
13) is amplified and output, and the output is level-shifted in one direction by the bias means (99) to enable A/D conversion compared to the analog reference voltage (V ref) of the A/D converter (15). It will be offset. Therefore, in the A/D converter (15), the amplifier (26)
The signal input from the image sensor (1
3) No clipping or the like occurs in the pixel output. In this way, the level soft offset is always A/
Image sensor (13) in order to exit in the direction where D conversion is possible.
There is no occurrence of so-called "fullness" in the pixel output output from the pixel output. In this way, after the output of the amplifier circuit (26) is A/D converted by the A/D converter (15), the arithmetic control means (14) removes the influence of the level shift offset.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

First, a first example will be described. FIG. 1 shows the configuration of an image sensor (13) manufactured as a CCD.

(1) is a photodiode array consisting of a plurality of photodiodes (PD) as photoelectric conversion means that generate charges according to the amount of incident light, and (ST) is an accumulation section that accumulates charges generated by the photodiodes (PD). , (B.G.
) is a field-effect transistor (hereinafter referred to as a field-effect transistor), which is a gate provided between a photodiode (PD) and a storage section (ST).
It's called PET. ), and this barrier gate (BG) connects the photodiode (PD) and the storage section (ST) when voltage is applied, and transfers the charge generated in the photodiode (PD) to the storage section (ST). On the other hand, when no voltage is applied, the photodiode (P
D) and the storage section (ST) are separated, and the photodiode (P
Stop the charge generated in step D) from flowing into the storage section (ST). In addition, (RG) is a transfer register that transfers charge from the left to the right in the drawing by two-phase drive, and (SH) is a storage unit (S
This is a transfer gate made of PET, which is a gate provided between the transfer register (RG) and the transfer register (RG). This transfer gate (SH) connects the storage section (ST) and transfer register (RG) when voltage is applied, and transfers the charge accumulated in the storage section (ST) to the transfer register (RG), while also transferring the voltage. When no voltage is applied, the storage section (ST) and transfer register (RG
) to prevent charges accumulated in the storage section (ST) from flowing into the transfer register (RG). Also, (RG
ICG) is an integral clear gate consisting of a FET as a gate. This integral clear gate (RGTCG) connects the transfer renostator (RG) and overflow drain (ODI) when voltage is applied, and removes unnecessary charges from the photodiode (FD) and storage section (ST) of each pixel prior to integration. Drain from the transfer renoster (RG) to the overflow drain (ODI). The overflow drain (ODI) is connected to the power supply voltage VDD and has the lowest potential.

On the other hand, an overflow gate 1 is connected between the photodiode (PD) and the overflow drain (OD2).
- (OG) is provided, and this overflow gate (
No voltage is applied to OG), and the potential is always fixed to be lower than the potential of the parier game-1-(BG) when no voltage is applied. The charge of each pixel transferred to the transfer register (RG) is transferred to the transfer lock φ1. φ is sequentially transferred to the capacitor (8-1) from the right side in the drawing. Before the charge is transferred to the capacitor (8-1),
Charging is reset to the power supply voltage by the 0SRS signal applied to the gate of the FET (8-3). Thereafter, the potential of the capacitor (8-1) decreases from the charging voltage by the transferred charge. The voltage between the terminals of this capacitor (L-1) is taken out as an O8 signal by a buffer (8-2). Although (8-1) has been described here as a capacitor for convenience of explanation, it can be replaced with a Gouioto PN junction, and when the circuit is integrated, this capacitor is manufactured as a diode. Hereinafter, the same applies when referring to a capacitor.

A light-shielding AC film (1-1) is provided on the plurality of photodiodes (PDs) at the ends of the photodiode array (1) in order to take out a black reference pixel output, which will be described later.

The photodiode array (1) detects pixels necessary for the automatic focus detection system using blocks on both sides except for the central area.
) corresponds to unused pixels that are unnecessary for the automatic focus detection system. For this reason, the central photodiode (PD) of the photodiode array (1) corresponding to the unused pixel is removed, and a photodiode (9) for brightness monitoring (to be described later) is installed in this removed portion for output processing. A part of the circuit is inserted (see Figure 21).

Further, in order to control the integration time of the image sensor (13), a brightness monitoring photodiode (9) is provided as brightness monitoring means for monitoring the amount of light incident on the photodiode (PD).

The brightness monitor photodiode (9) has an elongated shape because it is formed across two blocks on both sides of the photodiode array (1) that detects pixels necessary for the automatic focus detection system. In addition, this brightness monitoring photodiode (9) is configured so as not to monitor the amount of light irradiated to the area corresponding to the unused pixel.
The portions corresponding to the unused pixels are shielded from light by the A& film (9-1). In this way, the brightness monitoring photodiode (9) is arranged with the alignment direction of the photodiode array (1) in the elongated direction, and is configured to straddle the two blocks at both ends of the photodiode array (1). AQ film (9
-1), it is possible to accurately monitor the average output level of the portion corresponding to the pixel used. A part of the circuit for output processing of the brightness monitoring photodiode (9) is inserted in the center of the photodiode array (1) from which the photodiode (PD) has been removed, as shown in FIG.

As mentioned above, the luminance monitoring photodiode (9) has an elongated shape, and when its length is ρ and the output is taken out from one end, the length Q and the response time τ are generally
A relationship τoCρ2 holds true, and the longer the length Q, the more rapidly the responsiveness deteriorates. Therefore, in order to prevent the responsiveness from deteriorating, the output is extracted from the extraction electrode near the center of the brightness monitoring photodiode (9). Therefore, compared to the case where a contact is provided at the end of the photodiode (9), the response time is as shown in the following equation:
It is 1/4.

In this way, since the extraction electrode is provided near the center and the response of the brightness monitoring photodiode (9) is fast, even if the integration time is determined based on the output of the brightness monitoring photodiode (9), it will not be excessive. Appropriate integration can be performed without performing excessive integration that stores charges in the storage section (ST).

A capacitor (IO-1), which is a storage means, is connected to the brightness monitoring photodiode (9), and prior to integration of the image sensor (13), an FET (I O
When the AGCR3 signal is applied to the gate of the capacitor (10-1), the capacitor (10-1) is charged to the power supply voltage VDD. After the AGCR8 signal is removed, the potential at the capacitor (10-1) drops due to charges generated in response to light irradiation. This potential is applied to a buffer (10-2
) is output as the AGCO8 signal.

The compensation diode (I) is provided to remove the dark output of the brightness monitor photodiode (9), and a light-shielding A12 film (11-1) is provided on top of this. . This compensation diode (11) is designed to obtain the same amount of output as the dark output of the brightness monitor photodiode (9), but if it has the same structure as the brightness monitor photodiode (9). requires the same area as the brightness monitoring photodiode (9), leading to an increase in chip size. Therefore, this compensating diode (11), as shown in FIG. 7(a),
By making the N-type part consist of a number of parts separated from each other and aligned at regular intervals, and embedding these parts in the P-type part, the P on the surface that is the source of dark output can be reduced.
By increasing the length (peripheral length) La of the N-junction, it is designed so that the same amount of dark output can be obtained with a smaller size than the brightness monitoring photodiode (9).

The compensation diode (11) is connected to the capacitor (12-1
). This capacitor (Il-1) is connected to FE'r (+2-
3) is charged to the power supply voltage VDD by the AGCRS signal applied to the gate. However, after the AGCR8 signal is removed, the potential of the capacitor (12-1) gradually decreases due to the dark output charge of the compensation diode (I). This potential is output as the DO5 signal via the buffer (12-3). This concludes the description of the configuration of the image sensor (13).

Next, the overall hardware configuration will be explained along the block diagram of FIG. (14) in the middle of FIG. 2 is a microcomputer (μCom) which is an arithmetic control means for controlling the drive of the image sensor (13). Image sensor control section (16) of this microcomputer (14)
are two signals M D 1. for switching the four modes of the image sensor (13), which will be described later. M D t
In addition to outputting two signals N B + and N B t for providing the output and operation timing of I1
0 buffer (22), TIN indicating whether integration is completed or not
A indicating the start of A/D conversion of T signal and image sensor output
The ADT signal, which is the logical sum with the DS signal, is manually input, and gain information Gl is also input.

The G3 signal is NB, , NI3. The signal is input using the signal line.

The circuit on the left side of the microcomputer (14) is
It is constructed on a single-chip IC. Among these, the above I
The 10 buffer (22) has the following functions: That is,
A function of ORing the above TINT signal and ADS signal and outputting it to the microcomputer (14) as an ADT signal, and switching the output of the signal line of the signal N B l + N B to NB when inputting.

The NB2 signal is input from the microcomputer (14), and at the time of output, the Gl and G3 signals are input to the microcomputer (14).
14), the signal level of the microcomputer (14), the frequency dividing circuit (19), the integration time control section (20), the signal processing timing generation section (21), and the transfer lock generation section (30). ), etc., has an interface function with the signal level in the circuit.

On the other hand, the mode selection circuit (23) selects M D + , M
This circuit decodes the D2 signal and selects one of the following four modes. MD, -“L”.

In the case of MDt-“Yes”, the mode selection circuit (23)
[Set only the signal as “■]” and select INI mode.

IN [mode is a mode in which the image sensor (13) is initialized. MD, -“L”5MD2-
In the case of "H", the mode selection circuit (23) sets only the INT signal to "I4" and selects the INT mode. The INT mode is a mode for performing integration of the image sensor (I3). In the case of MD, - "T-(", MD2 - "H", the mode selection circuit (23) binds only the DD+ signal to "I-1" and selects the DD! mode. In the DDI mode, the image sensor (13) This is also the mode in which sample and hold of the black reference pixel, which will be described later, is performed using the NB, , NB2 signals.MD, -“H”,
In the case of MDt-“L”, the mote selection circuit (23)
2 signal only as "F(") and select DD'2 mode. In DD2 mode, the image sensor (13) is read out, and the image sensor (13) that has been read out and processed is
13) output to the A/D of the microcomputer (I4)
This is the mode for transmitting to the converter (I5). The operation and functions of each mode will be described later.

” The two-leg frequency divider circuit (19) is connected to the microcomputer (1.
The reference clock CP generated by the clock generator (I8) of 1) is divided, and the image sensor (13) transfer lock φ1. The clock φ that is the source of φ. At the same time, the integral time control section (20) and the signal processing timing generation section (2) generate a clock φ. A timing clock φ is generated for synchronization with the

The above clock φ. is sent to the transfer lock generation section (30), where S sent from the integral time control section (20)
H times signal RG I CG times signal clock φ.

Accordingly, the clock φ1. φ2 is created and used as a transfer lock for the image sensor (13). The integral time control section (20) receives a timing signal N transmitted from the microcomputer (14) when in INI mode or INT mode.
Based on the signals B, , NB, the ACCR8 signal, the BG multiplied signal S)I signal, and the nGTcG signal are generated in synchronization with the clock φ sent from the frequency divider circuit (19), and the integration start operation is performed. Each of the above signals is transmitted by the image sensor (
13). In addition, the integral time control section (2
0) is the integration completion signal VPLG from the brightness determination circuit (24), which is a subtraction means, which becomes "L" - "II" when the integration of the image sensor (13) becomes appropriate, or the mode selection circuit. A BG multiplied signal is generated by the timing signals NB, , NB2 transmitted when the DDI signal from (23) is at "H", and the operation of terminating the integration is performed.

Furthermore, this integral time control section (20) is controlled by the DDI signal.
I-1'', the timing signal NB.

The NB2 generates the SH signal and starts reading the output from the storage section (ST). At this time, a signal for obtaining luminance information, which will be described later, an SH multiplied signal, and φa, φb, and φC1φd signals are transmitted to the luminance determination circuit (24). The brightness determination circuit (24) monitors the AGCOS signal and DO9G9 signal sent from the image sensor (I3) and the light intensity irradiated to the image sensor (13), and when it is determined that the integration has reached an appropriate level. ni, V
l';'Gl function for inverting the LG signal, and determining the level of the integral when using the VFLG signal inverter for integration at low brightness and switching the gain of the image sensor (13) according to that level. , and has a function of outputting G3 signals.

AGC differential amplifier circuit (25) is an image sensor (13)
This circuit amplifies the output signal O8 sent from.

In this AGC differential amplifier circuit (25), the FET (8) of the image sensor (13) is turned on by the 09R9 signal.
After sampling and holding the potential O8 immediately after the capacitor (8-1) is charged by -3) using the r(SS/H signal sent from the signal processing timing generation unit (21)), this potential O8 is transferred and locked. According to the capacitor (
8-1) is transferred to the capacitor (s-H) which has dropped due to the electric charge generated in each pixel, and the difference with the potential O8 is taken, amplified, and output as a signal Vos' to the OB subtraction AGC differential which is the subtraction means. It is output to the amplifier circuit (26).

The gain of this OB subtraction AGC differential amplifier circuit (26) during amplification is switched by the G3 signal output from the brightness determination circuit (24). The above OB subtraction AGC amplifier circuit (2
6), differential amplification between the output of the black reference pixel and the output of the normal pixel without Aa light shielding, that is, the effective pixel, and the output Vos'
Sample hold is being carried out. Photodiode(
PD) always involves dark output, so the pixel detected by the AQ-shielded photodiode (PD) is used as the black reference pixel and the dark output reference pixel, and the black reference pixel is calculated from the output of the normal pixel. The value obtained by subtracting the components is the output of the image sensor (13). The OB subtraction AGC amplifier circuit (26) includes an AGC differential amplifier circuit (25).
Since the output V os' from ) is repeatedly input in synchronization with the transfer lock, the signal processing timing generator (
21) The level of the signal output V as' of the effective pixel is sampled and held by the O6S/H signal sent from the signal processing timing generator (21), and the OB signal sent from the signal processing timing generator (21)
Due to the S/H signal, during the black reference pixel output, the output Vo
Sample and hold s'.

The OB subtraction AGC amplifier circuit (26) subtracts the sampled and held black reference pixel output level Vos' from the sampled and held valid pixel signal output level Vos', and also G3 output from the brightness determination circuit (24). It is multiplied by a gain that is switched by the signal and output as a signal Vos below the analog reference voltage V rer.

The temperature detection section (27), which is a fixed range voltage output means,
Temperature is detected by the resistance divider circuit shown in Figure 3. This resistor divider circuit (27) includes a diffused resistor (32) formed by diffusion and a resistor (33) made of polynolylic resin (Po1y-5i), which are designed to have equal resistance values at room temperature. There is. Each resistor (32), (
33) have different temperature coefficients, the output V TMP output from their connection point via the buffer (34) is:
It depends on the temperature around Vref/2. Note that the analog switch (31) is set to D in the DD2 mode.
D = "L" and the analog switch (31) is turned off to reduce the current. On the other hand, the analog switch (28) shown in Fig. 2 is in DD2 mode.
That is, when DD2 is "H", it is turned on, and conversely, when DD2 is "I7", the analog switch (29) is turned on. As a result, in the DD2 mode, the output Vou
The signal Vos is output as the output t, and the signal VTMP is output as the output Vout in modes other than DD2 mode. The signal Vout is input to the A/D converter (15) in the microcomputer (I4), where the analog reference voltage V
A/D conversion of analog output on the lower voltage side than ref
It starts with a T signal and converts it to digital data.

In this way, when the analog switches (28, 29) are switched and the OB subtraction AGC differential amplifier circuit (26) is outputting the signal Vos corresponding to the used pixel, the signal is transferred to the A/D converter ( 15), while in other cases, the voltage VTM within a certain range is input from the temperature detection section (27).
Since P is input to the A/D converter (15), the negative output generated by subtracting the output corresponding to the black reference pixel from the output corresponding to the unused pixel from the OB subtraction AGC differential amplifier circuit (26), Even if a negative output is generated by subtracting the output of the black reference pixel from the output of the used pixel after pixel reading is completed, these will not be input to the A/D converter (15) and will not be input to the temperature detector. From (27), a voltage V TMP within a certain range is input to the A/D converter (15). Therefore, the A/D converter (15) does not exceed the input dynamic range and there is no risk of damage.

This concludes the explanation of the hardware configuration.

Next, the operation of the image sensor (13) described above in each mode will be explained in detail.

First, the initialization mode will be explained.

The microcomputer (14) is MDI-“L”.

When MD2="L" is output, the mode selection circuit (23)
is set to IN [only the signal is “■]”, and the integral time control section (2
0) to notify that it is in initialization mode (INI mode). INI mode is image sensor (I3)
This mode is for discharging unnecessary charges from the image sensor (13) immediately after the power is turned on. Image sensor (1
3), after the power is turned on, the photodiode (PD), which is a potential well, the storage section (ST), and the transfer register (RG
) has accumulated unnecessary charge, and it is necessary to quickly discharge this charge and start up the image sensor (13) so that it can be used. Therefore, in order to quickly discharge unnecessary charges, an INI mote was set, and the potential structure of the image sensor (13) was changed to the structure shown in FIG. 3.

Hereinafter, explanation will be given along with the potential diagram of FIG. 3 and the time chart of FIG. 4. In Fig. 3(a), the left side force is the overflow drain (OD2), the overflow gate (
OG), photodiode (PD).

Barrier gate (BG), storage section (ST), transfer gate (
S H), transfer register (RG), integral clear gate (
RG I CG), overflow train (ODl)
It becomes. Barrier gate (BG), transfer gate (S
H), when a voltage is applied to each gate of the integral clear gate (RGICG) and the transfer register (RG) (φ1 is applied to the transfer register (RG)), Fig. 3 (b
), PD>BG>ST>SH>RG>RG
The potential is designed so that I CG > OD l, and the photodiode (PD) and storage section (ST)
At this time, unnecessary charges in the transfer register (RG) are discharged to the overflow drain (ODl). This operation will be explained along the time chart.

The state in FIG. 4(a) corresponds to FIG. 3(a).

At this time, in the state of N B l = "I7", NB2 - "L', barrier gate (BG), transfer gate (S H),
No voltage is applied to each gate of the integral clear gate (RGICG) and the photodiode (PD).

Unnecessary charges are accumulated in each section of the storage section (ST) and transfer register (RG). When both NB, NBt are "L", the integral time control section (20) that controls the image sensor (13) does not perform any operation on the image sensor (13).

The microcomputer (14) is NB, -"I(".

When NB = “L” is output, the integral time control section (20)
is the clock φ sent from the frequency dividing circuit (19). In synchronization with , as shown in FIG. 4(b), SH-"I(".

BG="H" and RG I CG="H" are output to the image sensor (13). Furthermore, S H signal, RG I
The CG double signal is also sent to the transfer lock generation section (30), and the transfer lock generation section (30) receives the SH signal and the clock φ. The OR output of is transferred to lock φ, and RGI
CG signal and φ. Transfer the Noah output of and use it as lock φ2,
In the case of SH-“■]”, RGICG-“H゛, φ,
- When the image sensor (13
) has been stopped. The image sensor (13) is SH, BG, RGICG, φ1. φ
, the unnecessary charges from the photodiode (PD), the storage section (ST), and the transfer register (r(G)) are discharged as shown in FIG. 3(b).

The microcomputer (14) continues with NB, -“H”
, NBt="H", and then NB,="L".

NB! ="H" is output. In response to this, the integral time control section (20) sets the clock φ. and returns the SH double signal and BG double signal to “L” (Fig. 3 (C), Fig. 4 (C)
)). On the other hand, in the transfer lock generation unit (30), the transfer lock φ starts to move due to the SH multiplied signal returning to “L”, and the transfer lock φ is “L”.

At this time, the potential difference between the transfer register (RG) and the overflow drain (ODI) increases, promoting the discharge of unnecessary charges from the transfer register (RG), and completely discharging them to the overflow drain (ODI) (see Figure 3). d), Figure 4(d)). Also, at this time, since the transfer lock φ2 remains stopped at "L", another transfer register (RG) adjacent to the above transfer register (RG) to which the transfer lock φ is applied is connected to the above register (RG). RG) will not flow in.

After the timer measures that the predetermined time has elapsed, the microcomputer (14) sets both NB and NBt to "L".
”.The integral time control section (20) thereby returns φQ
The RG I CG double signal is set to "L" in synchronization with. Then, the voltage applied to the RGICG terminal of the image sensor (13) becomes zero, and the integral clear gate (RGICG) becomes zero.
CG) closes. At the same time, the transfer lock generation section (
30), the RG I CG double signal becomes “L”, and the transfer lock φ starts to move (Fig. 3 (e), 4
Figure (e)). With this, one cycle of unnecessary charge discharging operation is completed.

Normally, when initializing the image sensor (13), the above-described unnecessary charge discharge operation is repeated several cycles, and then the initialization mode is ended.

In the present invention, the structure in which an integral clear gate (RGICG) is connected to each register (RG) eliminates the need to discharge unnecessary charge from each register (RG) by transferring it from the register (RG). It is possible to shorten the time for one cycle of the unnecessary charge discharge operation, and to shorten the time allocated to the initialization mode.

Next, the second mode, the integral mode, will be explained.

The microcomputer (14) is MD, -“L”.

When MD outputs −“H”, the mode selection circuit (23)
In this case, only the INT signal is set to “H”, and the integral time control section (20
) to notify that it is in integration mode (INT mode). In the INT mode, the image sensor (13) starts integrating and ends the integration during high brightness.

The operation will be explained along with FIGS. 5 and 6. The integration starting operation is exactly the same as the unnecessary charge discharge operation during initialization, except for the BG multiplication signal. BG double signal NB, -“H”
, NB, - After the microcomputer (14) outputs "L", the integral time control section (20) outputs φ. (In the figure, this is the rising time of φ1.) “I-(”)
will be launched on. This is the same as in IN1 mode. However, the microcomputer (14) is NB,
- “L”, NB x - “H” output, IN
φ in I mode. BG double signal “L” again in synchronization with
However, in IN′r mode, the BG double signal “H”
It remains as it is. BG double signal “L” at the end of integration (described later)
becomes.

At the time of Fig. 5 (C) and Fig. 6 (C), the transfer gate (SH
) becomes zero, the transfer gate (SH) returns to a higher potential than the photodiode (PD), storage section (ST), and overflow gate (OG), and from this point on, The generated charges flow into the storage section (ST) and begin to be accumulated in the storage section (ST), and integration is started in the image sensor (13).

On the other hand, the time point at which the integration ends is monitored by the output of the brightness monitoring photodiode (9). The operation of the brightness determination circuit (24) will be explained below, and the operation of completing the integration will be explained.

The integration time control section (20) transmits the AGCR9 signal to the image sensor (+3
). As shown in FIG. 1, the AGCR8 signal is transmitted to the FET (1 (1)
-3) and the gate of the FET (+2-1) connected to the capacitor (+2-1) connected to the compensation diode (11).
2-3) is applied to the gate. By applying the above AC; CRS signal, the above capacitor (10-1)
, (12-1) are charged to approximately the power supply voltage VDD. S.H.
When the AGCR9 signal becomes "L" at the same timing as the double signal, the power supply is cut off, and from then on, the brightness monitoring photodiode (9) generates a charge according to the amount of light irradiated, and the photodiode (9) connected to this The potential of the capacitor (10-1) begins to drop in accordance with the generated charge. On the other hand, the compensating diode (11) generates a charge due to its dark output, and the potential of the capacitor (12-1) connected thereto also begins to drop in accordance with the generated charge. Each potential is outputted to the analog circuit shown in FIG. 8 of the brightness determination circuit (24) in FIG. 2 via each buffer (IO-2) and (12-2). In Fig. 8, the AGCO9 signal is input to the positive input of an operational amplifier (hereinafter referred to as an operational amplifier (X43)), the DO8 signal is input to the negative input of an operational amplifier (43), and the differential output is the operational amplifier (X43). 43). The output V 43 of the operational amplifier (43) is expressed by the following formula.

V+3=Vref (DOS AGCOS) This output V43 is connected to one comparator (45
)'s negative human power.

On the other hand, the positive input of the comparator (45) is connected to the FET (46°47.
A constant voltage generated by resistance division according to 48.49) is supplied. During integration, only φd is “H”, FET (49) is turned on, and the supplied constant voltage is V.
4°=(V rer −V th). The output of the comparator (45) is “ when V 43 < V 49”
In other words, Vref-(DOS-AGCOS)<Vref-Vth
It becomes "H" when DO9-AGCOS>Vth.

(DO9-AGCOS) indicates a voltage dropped due to light irradiation from the brightness monitoring photodiode (9) (the dark output component is compensated by the output of the compensation diode (11)). Immediately after the start of integration, the amount of light irradiated to the brightness monitoring photodiode (9) is insufficient, and DO9-
AGCOS is 0, and the output of the comparator (45) (
VF'LG) is at "L". During the integration (DO8
-AGCOS) becomes greater than the voltage of vth,
The integration for the image sensor (13) is appropriate, and the output (V F L G) of the comparator (45) is “L”
to "I4". As shown in the time chart of FIG. 6, the integral time control section (20) sets the BG multiplied signal to "L" when the output VFLG of the comparator (45) is inverted. When the BG multiplied signal becomes "L", the potential of the barrier gate (BG) becomes greater than the potential of the photodiode (PD), as shown in Figure 5(e), and the charge generated in the photodiode (PD) increases. It prevents the water from flowing into the storage part (ST).
The charge accumulated in T) is generated when the VFLG signal is “I-1”,
That is, when the BG multiplied signal becomes "L", it is held and the integration ends. The charge generated after the completion of integration is accumulated in the photodiode (PD), and even if the accumulation progresses, the charge generated in Fig. 5 (e
), it crosses the overflow gate (OG), which has a lower potential than the barrier gate (BG), and is discharged to the overflow drain (OD2), so it does not flow into the storage section (ST).

Further, the integration time control unit (20) sets the BG multiplied signal to "L" and at the same time sets the TINT signal to "L", and notifies the microcomputer (14) of the inversion of the TINT signal via the ADT terminal. This concludes the explanation of the integration start operation in the integration mode and the integration end operation during high brightness.

Next, the third mode, f-event read mode 1 (DDI
mode).

The microcomputer (14) is MD, = “H”.

When MD, -“)-1” is output, the mode selection circuit (2
3), only the DD+ signal is set to “H”, and the integration time control section (
20) to notify that it is in DDI mode. The DDI mode is a mode in which the integration is completed at low brightness and the reading of each pixel data of the image sensor (13) is started.

First, the integration termination operation at low luminance will be explained based on the time chart of FIG. 22. When the subject brightness is low, it may take a long time until the brightness determination circuit (24) determines that the appropriate integration time has been reached. If integration is performed for a long time, the dark output increases, leading to deterioration of the S/N ratio. Furthermore, an extremely long integration time is inconvenient from a system perspective.

For example, when used in a focus detection device for a camera, the focus detection cycle becomes long and the focus detection cannot keep up with the movement of the subject. Therefore, the longest integration time allowable within the microcomputer (I4) is set in advance, and if the TINT signal output to the ADT terminal has not been inverted even after this time, the M
D, -"I]"1MD2-"■(" is output, the transition is made to the DDI mode, and the operation of completing the integration is performed in the DDi mode.The integration time control section (20) in the DD+ mode outputs NB,
-“l(″.

NB, - “L” signal is sent to the microcomputer (14)
When the signal is received from the BG signal, the BG multiplied signal is immediately set to "L". As a result, as in the previous case, the barrier gate (B
The potential of G) becomes higher than that of the photodiode (PD), the charge generated in the photodiode (PD) stops flowing into the storage section (ST), and the integration ends (FIG. 22).

Next, the operation to start reading out each pixel data of the image sensor (I3) will be explained. Regardless of whether the brightness is low or high, the microcomputer (14
) outputs NB,=“H”, NB,−“L”, the integral time control unit (20) locks the transfer φ. Synchronize and transfer lock φ. The SH signal pulse is generated at the timing of "H" (FIG. 6 or FIG. 22). As a result, as shown in FIGS. 5(J) and (g), a pulse voltage is applied to the Sr gate of the image sensor (I3), and the signal charge of each pixel is accumulated in each accumulation section (ST). is transferred to the transfer register (RG). After that, transfer lock φ8
．． The signal charge of each pixel is transferred and read out by φ2. Transfer of the signal charges accumulated in each accumulation section (ST) to the transfer register (RG) is carried out by a microcomputer (1
4) is in DDI mode, NB, -“H”, NBt="L"
This is performed when " is output. At this time, it is necessary that the transfer register (RG) returns from the unsteady state after the start of integration and becomes a steady state.

In a steady state, each transfer register (RG) has a dark charge of 23
It is accumulated as shown in the figure. This dark charge is the sum of the dark charge generated in the potential well of each transfer register (RG) and the dark charge of the previous stage register that is sequentially transferred. At the start of integration, the integral clear gate (flGI
A voltage is applied to the gate terminal of the transfer register (R
The integral clear gate (RGICG) between G) and overflow drain (ODI) is turned on, and the transfer register (
RG) are all cleared. After the integral clear gate (RGICG) turns off, transfer lock φ
.

Every time one period passes, the dark charge of the transfer register (r(G)) reaches a steady state starting from the left side of FIG.

It takes a time equal to the number of pixels (N) x one transfer lock cycle (T) until all transfer registers (r(G) return to a steady state).

When the S H pulse is generated in an unsteady state, the dark charge component of the transfer register (RG) in the charge taken out as an output may be in an unsteady state depending on the pixel, so a correct signal cannot be taken out. Therefore, the SH pulse is generated when at least the RGICG signal is from "I-1" to "L".
”, then the number of pixels x one transfer lock period (N
XT).

At high brightness, the integration is often completed within one cycle (NXT), but since the integration is terminated by closing the barrier gate (BG), the integration is completed after one cycle (NxT) has elapsed.
It is possible to make the generation of the S H pulse wait.

Next, regarding the processing of the read pixel output, Figure 1+,
This will be explained below with reference to FIG.

The signal charge of each pixel of the image sensor (13) is φ, −
At the timing of "L", φ, -"I("), the signal charge is transferred to the capacitor (8-1) shown in FIG.
As shown in FIG. 12, φ1−“■]”, φ,=“
The 0SR8 signal pulse is generated at the timing of "L", and this pulse is applied to the gate of the FET (8-3) shown in Fig. 1 to charge the capacitor (8-1) to approximately the power supply voltage and reset it.φ1 = “L”.

When the signal charge is transferred at the time when φ2 becomes “H”, the voltage of this capacitor (8-1) decreases due to the signal charge, and the output O8 of the image sensor (13) becomes the 12th
The output is as shown in the figure. AGC differential amplifier circuit (
25), the RSS/HSS/up and reset voltage levels sent from the signal processing timing generator (21) are measured by the sample and hold circuit consisting of the PET (52), capacitor (53), and buffer (51) shown in Figure 11. According to
Store it and manually input it to the positive input of the operational amplifier (54).

On the other hand, the O8 signal is input to the negative input of the operational amplifier (54) via the buffer (50), and
5゜56.57.58) Gl manually applied to the gate, 0
The output differentially amplified with a gain determined by the two signals (see FIG. 11) is output from the operational amplifier (54) as V os' (see FIG. 12).

Next, the determination of the integral level will be explained.

If the integration is forcibly terminated when the brightness is low, the level of the pixel output of the image sensor (13) will naturally be lower than when it is appropriate. Therefore, in this case, the above-mentioned brightness determination circuit (24) is used to detect one novel of integration, and a gain is applied to the output of the image sensor (13) according to the result, so that the output is always at an appropriate level. I'm trying to get it.

The following will explain the brightness determination analog circuit of FIG. 8, the pulse timing chart of FIG. 9, the brightness determination logic circuit of FIG. 1O, and the truth table of FIG. 24. Note that the brightness determination circuit (23) is constituted by this brightness determination analog circuit and the brightness determination logic circuit. As shown in Fig. 8, the operational amplifier (43) outputs an output (43=Vrer-(DOS-AGCOS)) corresponding to the amount of light, and a comparator (45), which is a luminance determination means, outputs an output corresponding to the amount of light.
is input to the negative input of When determining the integration time, φd is applied as shown in FIG.
Vth) is input. Now, when the SH pulse occurs, latch I (73) and latch 2 (74) in Figure 1O are activated.
), latch 3 (75) are all reset.

Thereafter, as shown in FIG. 9, when the φC pulse is generated, the FET (48) in FIG. 8 is turned on, and the positive input of the comparator (45) is
2) is done manually. Here, if DO9-AGCOS)>Vth/2, the output ■FLG of the comparator (45) is “I
4”, and the AND gate shown in Figure 10 (
70) becomes "H", and latch 1 (73) is set. After that, as shown in FIG. 9, when the φb pulse is generated, the FET (47) in FIG. 8 is turned on.
The positive input of the comparator (45) has (V re "-
Vth/4) is input. Here, if DO
3-AGCOS)>Vth/4, the output VFLG of the comparator (45) is “1”.
-1", and in FIG. 10, the AND gate (71
) output becomes "■(", and latch 2 (74) is set.Furthermore, as shown in FIG. 9, when the φa pulse is generated, the FET (46) in FIG. 8 is turned on, The positive input of the comparator (45) has (V re
"-V th/ 8 ) is input. Here, (DO
3-AGCOS)>Vth/8, the output VFLG of the comparator (45) is “H”.
”, the output of the AND gate (72) shown in FIG. 10 becomes “H”, and the latch 3 (75) is set. In each of the above cases, as shown in the truth table of FIG. 24, Gl,
G3 signal is generated. Based on this signal, the gains are selected as shown in the table below, and a substantially appropriate level of Vos is obtained for each gain.

-Left below- In this way, by sequentially turning on PET (49, 48, 47, 46), the reference voltage generation circuit (RVC)
generates multiple reference voltages, one comparator (45) can judge the brightness at multiple stages, and the image sensor (
13) The number of comparators formed on the same chip can be reduced.

The FET (44) shown in FIG.
This is a switch for supplying power to the resistance divider circuit, that is, the reference voltage generation circuit (RVC) only in the I mode.

This FET (44) allows the reference voltage generation circuit (RV
C) is energized only when necessary for brightness determination, reducing current consumption. This saving effect on current consumption becomes greater at high brightness because the integration time becomes shorter than the readout time.

As shown in FIG. 11, the signal Vos' is connected to the FET (60)
, a capacitor (62), and a buffer (64).
65) is input to the negative input. This signal V os
' is held by the signal processing timing generator (21
) to φ, -“L”, φ2=“■]” This is performed by an OSS/H pulse signal generated at the timing of signal charge transfer. The signal Vos' is also input to a sample and hold circuit consisting of an FET (59), a capacitor (61), and a buffer (63). This sample and hold circuit samples and holds the output of the black reference pixel subjected to the A12 light shielding shown in FIG. The pulse that provides sample and hold timing is the OBS/H signal shown in FIG. 12, which is generated in the sequence shown below.

As shown in FIGS. 2 and 12, after shifting from the INT mode to the DD+ mode, an ADS signal that provides timing for starting A/D conversion appears in the ADT signal. The microcomputer (14) measures the timing of sampling and holding the black reference pixel output while monitoring this signal. The microcomputer (14) outputs NB while outputting the black reference pixel.

= "H", NB, - "H", and the signal processing timing generating section (21) thereby sets the OBS/I-I signal to "H". Next, the microcomputer (1
4) is NB until the next ADS signal rises.

= “L”, NB, = “H”, and the signal processing timing generation unit (21) thereby outputs the OBS/H signal “L”.
”.As a result of the above, the FET (59) shown in FIG.
, a capacitor (61), and a buffer (63) holds the inputted black reference pixel output and inputs it to the negative input of operational amplifier 2 (65). After sampling and holding the black reference pixel, the output of the operational amplifier 2 (65) is subtracted by the amount corresponding to the held black reference pixel output, and the output of the operational amplifier 2 (65) is subtracted by the amount corresponding to the held black reference pixel output, and the output of the G3. It is amplified by the gain determined by the G4 signal (No. 11 Interest Table) and output as the signal Vos (FIG. 12).

As described above, the output signal O8 of the image sensor (13) is double sampled in the AGC differential amplifier circuit (25) and the OB subtraction AGC differential amplifier circuit (26), the reset level is subtracted from the signal level, and the reset level is subtracted from the signal level. A signal unaffected by noise is extracted, and the black base level is further subtracted from the signal unaffected by reset noise, resulting in an output Vos in which the dark output is removed from the output of each pixel.
is obtained. Furthermore, this output Vos is applied to the AGC differential amplifier circuit (
25) and the OB subtraction AGC differential amplifier circuit (26), a gain of x8 to x64 is applied, as described later, according to the average level of each pixel output. In this way, since the two amplifier circuits (25, 26) perform two-stage amplification, the range of resistance values connected to the operational amplifier (54, 64) can be smaller than when amplifying with one amplifier circuit. , the area occupied by the resistor becomes smaller.

Next, the gain of the operational amplifier (54) of the AGC differential amplifier circuit (25) and the gain of the operational amplifier (65) of the OB subtraction AGC differential amplifier circuit (26) shown in FIG. 11 will be described. Here, for the output OS of the image sensor (13), x8. X16. In order to switch the gain of
(65) performs two-stage gain switching. In this case, the operational amplifiers (54) and (65) always have an offset problem. When applying gain in two stages, the first stage gain is GNI, the second stage gain is GN2,
If the offset of each operational amplifier is ΔV1, the manual power is vi1, and the output is Vo, then the output is expressed by the following formula.

Vo-((Vi+△V) x GNI+△v)xGN2
= Vi X GNI X GN2+△V −(GNI
X GN2 + GN2)-(Vi+△V)xGNl
xGN2+ΔVXGN If the total gain GNIXGN2 of the 22-stage operational amplifier does not change, an offset due to GN2 appears in the second term (Δ■xGN2) of the above equation.

That is, the smaller GN2 is, the smaller the total offset will be.

Therefore, the first stage gain GNI is the second stage gain GN2.
The offset can be suppressed by choosing higher than , but even with this measure the offset remains. For this reason,
As shown in FIG. 11, the downstream operational amplifier 2 (65) performs a level shift based on a voltage that is one diode (99) serving as a bias means from the reference voltage V ref, so it always performs A/D conversion. As much as possible, the offset is made to be output on the lower voltage side than the reference voltage Vref.

After sampling and holding the signal representing the black reference pixel, the OB subtraction AGC differential amplifier circuit (26) outputs a signal representing the second black reference pixel subjected to A12 light shielding before outputting the signal representing the effective pixel. are doing. Since the previously held black reference pixel is subtracted from the output representing this second black reference pixel, if there is no offset of the operational amplifier, an output that matches the reference voltage Vre' can be obtained.However, Since the output of the operational amplifier 2 (65) always has an offset VoffseL on the lower voltage side than the reference voltage Vrer, the output becomes (Vref-VofTset).
When /D conversion is performed, a signal corresponding to Voffset can be obtained as digital data. Thereafter, the output of the effective pixel is subtracted by this Vo[Tset by the calculation of the microcomputer (I4), so the output of the effective pixel is subtracted by the microcomputer (I4).
The data input to step 14) is substantially the same as the data with the offset component removed.

Next, the DD2 mode will be explained.

In the DD2 mode, the image sensor (13) is not caused to perform any active operation.

Therefore, NB1 connected to I10 buffer (22)
．． It switches the input/output of the NBt signal, outputs the G1 signal to NB, the G3 signal to Nl3t, and notifies the microcomputer (14) of the gain information of the output of the image sensor (13). This +10 switching is performed by the DD2 signal.

Only in the DD2 mode, the signal output as Vout is the output Vos of the image sensor (13).

The pixels used in this system are image sensors (13)
are pixels detected in two separate regions of
No photodiode (PD) is provided between the two regions. A/D with the output of these pixels as V out
Since there is a problem described later when outputting to the converter (15), Vos is output as Vout only when an effective pixel is output by switching between DD2 mode and DD1 mode. Output Vos' of AGC differential amplifier circuit (25)
is the output component V corresponding to the optical signal when outputting from an effective pixel.
□s' (s ig) and dark output component V os' (
(V os' = V
os' (sig) + V os' (dark)
). V os in the OB subtraction AGC differential amplifier circuit (26)
' (dark) is subtracted, and Vos= V ref - G N 2 X (Vos'
-Vos' (dark)) as the A/D converter (1
5) is output.

At this time, the output of the pixel from which the photodiode (PD) has been removed does not have an output corresponding to an optical signal or a dark output component, so Vos'=O. Here, when Vos' (dark) is subtracted in the OB subtraction AGC differential amplification (26), Vos=Vref-GN2X (0-Vos'
(dark))> V ref, and Vos becomes higher voltage than the reference voltage V er, contrary to the lower voltage side than the reference voltage V ref that can be converted into A/D.
Exceeding the dynamic range of conversion, the A/D converter (15
) may result in destruction. For this purpose, except for the output of effective pixels, the analog switches (28) and (29) are switched, and the temperature detection output VTM, which can be converted into A/D, is always output.
Outputs P. In this way, by outputting Vos with DD2-“H” only when outputting a valid pixel, and outputting VTIAP with DD2-“L” when outputting an invalid pixel, the dynamic range of A/D conversion is always maintained. A/D conversion is performed within the unit.

This concludes the explanation of I)D2 mode and the explanation of the first embodiment.

Next, a second embodiment will be described in which the means for removing the dark output component in the first embodiment is modified. here,
Only the differences from the first embodiment will be explained with reference to the block diagram in FIG. 14 and the circuit diagram of the AGC differential amplifier circuit in FIG. 15.

First, the block diagram of FIG. 14 showing the second embodiment and the block diagram of FIG.
As shown by the differences in the block diagram of FIG. 2 illustrating an embodiment of the analog reference voltage V re
This embodiment differs from the first embodiment in that f' is output from the AGC differential amplifier circuit (125). Furthermore, in FIG. 14, the OB subtraction AGC differential amplifier circuit in the first embodiment is removed.

The operation of the second embodiment will be explained with reference to FIG. As in the first embodiment, the image sensor (13) outputs the output of the black reference pixel before outputting the effective pixel. Here, A
A sample and hold circuit consisting of a PET (159), a capacitor (161) and a buffer (163) in the GC differential amplifier circuit (+25) samples and holds the output of the black reference pixel using the OBS/H pulse. In the first embodiment, the held output was connected to the negative input of operational amplifier 2 (65) and subtraction was performed by operational amplifier 2 (65), but in the second embodiment, the bolded output was connected to the negative input of operational amplifier 2 (65). It is output as ref'. This Vref' is A
The voltage is supplied to the /D converter (115) as an analog reference voltage, and the A/D converter (115) performs A/D conversion of the manually input voltage using this voltage as a reference.

That is, since the difference between the human power V out and the reference voltage V ref is taken and converted into a dinotal value, this is equivalent to subtracting the black reference pixel output in the A/D converter (+15).

In addition, the output of the black reference pixel, which is sampled and held by the sample-and-hold circuit consisting of the FET (160), the capacitor (162), and the buffer (164), and the output of each effective pixel are the outputs of the operational amplifier 2 (165). Since these differentials are taken within the A/D converter (115), the offset of operational amplifier 2 (165) is completely removed. Therefore, in the second embodiment, the image sensor (13).

At the same time as removing the dark output, the offset of operational amplifier 2 (165) is removed.

Next, a third embodiment will be described with reference to FIGS. 16, 17, and 18. This third embodiment differs from the first and second embodiments in the dark output removal means.

First, let us look at the block diagram of the third embodiment (Fig. 16) and the block diagram of the first embodiment.
Differences from the block diagram of the embodiment (FIG. 2) will be described.

In the third embodiment, the sample and hold pulse OBS/H of the black reference pixel is input to the A/D converter (215), and the OB subtraction AGC differential amplifier circuit is removed. In this third embodiment, subtraction of the black reference pixel is performed within the A/D converter (215).

FIG. 18 shows the A/D converter (215), and this A/D converter (215)
The conversion section (215) includes an A/D conversion circuit (206) and an internal circuit provided on the same chip. In FIG. 18, the output of the image sensor, which is manually inputted as Vin, consists of the output of a black reference pixel and the output of the effective pixel following this pixel. The output of the black reference pixel is OBS/H pulse, PET (201),
A sample and hold circuit consisting of a capacitor (202) and a buffer (203) performs sample bolding. The effective pixel output that is input from then on is the operational amplifier (
205), the sampled and held black reference pixel output is subtracted therefrom, and then input to the A/D conversion circuit (206).

FIG. 17 shows an AGC differential amplifier circuit (225).

In the first embodiment, there was a sample and hold circuit for the output of the black reference pixel, but in the third embodiment, this is removed. Further, as in the second embodiment, since the black reference pixel output and the effective pixel output are output from the same operational amplifier (165), the offset of this operational amplifier (165) is completely canceled.

Next, a fourth example in which the dark time output removing means is different from the above-mentioned embodiment.
An example will be explained. FIG. 19 is a hardware block diagram according to the fourth embodiment. This is different from FIG. 16, which is a block diagram of the third embodiment, when the reference voltage V re
The difference is that f is not manually input to the A/D converter (315), and the AGC differential amplifier circuit (225) has exactly the same configuration as the third embodiment.

FIG. 20 shows the A/D converter (315), and this A/D converter (315)
The conversion section (315) includes an A/D conversion circuit (405) and an internal circuit provided on the same chip. While the image sensor (13) is outputting the black reference pixel,
The OBS/H pulse is given to the /D converter (315), and the output of the black reference pixel input to the terminal Vin becomes PE.
T (401), capacitor (402), buffer (40
3) is sampled and held by the sample bold circuit. The held black reference pixel output is input to the A/D conversion circuit (405) as an analog reference voltage (V rer' ). After that, the effective pixel output of the image sensor (13) inputted to the terminal Vin is the second
As in the embodiment, the output of the held black reference pixel (V
ref') is subtracted and then A/D converted. This removes the dark output component.

<Effects of the Invention> As is clear from the above, the solid-state imaging device of the present invention has the following effects:
An image sensor having a photoelectric conversion section, a storage section, and a transfer register, an amplifier circuit that amplifies the output of this image sensor, and an A/D conversion that converts the output of this amplifier circuit into a digital signal and outputs it to an arithmetic control means. The amplifier circuit further includes bias means for level-shifting the output of the amplifier circuit in one direction capable of A/D conversion with respect to the analog reference voltage of the A/D conversion section. A/D
The level shift offset of the signal input to the converter always occurs in the direction in which A/D conversion is possible, so that a part of the pixel output of the image sensor is never cut off.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the image sensor in the solid-state imaging device of the present invention, FIG. 2 is a block diagram of the fixed imaging device of the first embodiment of the invention, and FIG. 3 shows the potential structure of the image sensor at the time of initialization. 4 is a time chart of the signal in the initialization mode of the first embodiment, FIG. 5 is a diagram showing the potential structure of the image sensor in the integral mode, and FIG. 6 is the time chart of the signal in the integral mode. Chart, Fig. 7 is a structural diagram of a compensation diode, Fig. 8 is a circuit diagram of a brightness judgment analog circuit, Fig. 9 is a time chart of signals during brightness judgment,
FIG. 10 is a circuit diagram of the brightness determination Ronok circuit, FIG. 11 is a circuit diagram of the AGC differential amplifier circuit and the OB subtraction AGC differential amplifier circuit in the first embodiment, FIG. 12 is a time chart regarding pixel output processing, and FIG. The figure is a circuit diagram of the temperature detection section, Figure 14 is a block diagram of the solid-state imaging device of the second embodiment, Figure 15 is a circuit diagram of the AGC operational amplifier circuit of the second embodiment, and Figure 16 is the third embodiment. 17 is a circuit diagram of the AGC operational amplifier circuit of the third embodiment, FIG. 18 is a circuit diagram of the A/D conversion section, and FIG. 19 is a block diagram of the solid-state imaging device of the fourth embodiment. 20 is a circuit diagram of the A/D conversion section of the fourth embodiment, FIG. 21 is a structural diagram of the image sensor, and FIG. 22 is a time chart of signals in the integration mode of the fourth embodiment. FIG. 23 is a diagram illustrating the transfer of dark charges, and FIG. 24 is a diagram showing the truth table of the luminance judgment Ronok circuit. PD, BG, ST...Storage means, SH...Shift gate, RG...Transfer register,
RG [CG... Integral clear gate, 14 - Microcomputer, 20... Integral time control section, 23... Mode selection circuit, 2
4... Brightness determination circuit, 30... Transfer resistance generating section. Patent applicant: Minolta Camera Co., Ltd. Representative: Patent attorney: Mr. Yu and 2 others (G) Shuun-ro Lb 7 Figures around Hi-cho La LaM7.71-b

Claims (1)

[Claims] (1) A photoelectric conversion unit that generates a charge corresponding to each pixel;
An image sensor having an accumulation section that accumulates charges generated in the photoelectric conversion section, a transfer register that sequentially transfers the charges of this accumulation section, an amplifier circuit that amplifies the output of the image sensor, and an output of the amplifier circuit. In the solid-state imaging device, the amplifier circuit has an A/D converter whose output is higher than the analog reference voltage of the A/D converter. A solid-state imaging device including bias means for providing a convertible unidirectional level shift offset.