JPH0120537B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master slice semiconductor device, and particularly to a master slice semiconductor device of a multilayer wiring type using polysilicon for the first layer wiring.

Conventional master slice semiconductor devices perform transistor base diffusion from the surface of a single crystal silicon wafer, form a polysilicon layer on the surface of the single crystal silicon wafer, and then perform graft base and emitter diffusion from the surface of the polysilicon layer. is being carried out. The polysilicon thus formed is used as a polysilicon wiring and a polysilicon resistor after undergoing a predetermined process. As a result, each electrode of the transistor and the wiring can be connected to each other without requiring a connection hole, especially by using the polysilicon on each electrode which also serves as a wiring. Now, based on the premise of a manufacturing method that allows formation of such polysilicon wiring as a first wiring layer and further formation of second and third wiring layers, gate circuits, EXOR circuits,
When designing a logic LSI using the master slice method, which configures the entire logic circuit by interconnecting various basic logic circuits such as flip-flops,
In order to mount more logic functions per unit area on a chip, it is preferable to give the polysilicon wiring the most suitable shape according to each of the above-mentioned basic logic circuits and their relative arrangement on the chip. Therefore, it is preferable that the process of defining the polysilicon wiring shape in the master slicing method be handled individually for each product type.

However, with this method, the two processes of graft base diffusion and emitter diffusion, which do not require a unique shape to each product, can be applied to wafers that have already been differentiated into individual products by the polysilicon wiring shape. This results in the disadvantage that the manufacturing period for individual products becomes longer than necessary. In this manufacturing method, a second layer is further added,
This drawback requires more effort in manufacturing management compared to conventional master slice semiconductor devices, as the third layer wiring must be formed, and furthermore, it is difficult for the user of the product. On the other hand, it is difficult to supply products within a certain period of time. In order to eliminate this drawback, it is sufficient to make the shape of the polysilicon wiring common to all products, and by doing so, the process of determining the shape of the polysilicon wiring, and the two processes of graft base diffusion and emitter diffusion. The diffusion process is omitted from the time required to manufacture individual products, making it possible to achieve a significant time reduction. However, in this case, on the other hand, it becomes impossible to change the shape of the polysilicon wiring according to various connection relationships of the circuit, and the function of the polysilicon wiring as a wiring is significantly impaired. In other words, it is theoretically prohibited to connect device terminals using only polysilicon wiring on the first layer (if the wires are connected, a specific circuit will be created there), and the connection between device terminals must be made using a second layer. Layer wiring or second layer wiring and third layer wiring become necessary.

As a result, in order to shorten the manufacturing time required for individual products, how can we compensate for the decline in the wiring function of poly-silicon wiring, or how can we improve the second layer, which will increase to compensate for the decline in the functionality of poly-silicon wiring? A new problem arises as to how to reduce the load on the wiring or the third layer wiring.

That is, the conventional master slice semiconductor device has disadvantages in that it places a heavy burden on the second layer wiring and the third layer wiring and prolongs the manufacturing period.

An object of the present invention is to provide a master slice semiconductor device that can reduce the burden on second-layer wiring and third-layer wiring and shorten the manufacturing period.

That is, the present invention was made against this background, and aims to shorten the manufacturing period for individual products, and for this purpose, the shape of the first layer polysilicon wiring is made common to all products. To provide a means for suppressing an increase in load on second-layer wiring and third-layer wiring by effectively defining a poly-silicon wiring shape that is a common shape in order to compensate for the functional deterioration of poly-silicon wiring as wiring that occurs at that time. .

The master slice semiconductor device of the present invention includes a plurality of transistors and a first layer formed of polysilicon and connected to the transistors. a plurality of transistor electrodes, at least one first connecting hole-able position, and a first polysilicon resistor-formable region formed between the transistor electrode and the first connecting hole-able position; a first type of polysilicon wiring; and at least two second connection hole-permissible positions formed of polysilicon in the first layer, at least one of which is disposed relative to the first connection hole-performable position. and a plurality of second type polysilicon wirings each having a second polysilicon resistor formation region formed between two second connection opening possible positions.

That is, in the master slice semiconductor device of the present invention, a master slice substrate is formed by a plurality of transistors having electrodes made of polysilicon and a first layer wiring made of polysilicon and in the same layer as the polysilicon. a master slice having means for forming a polysilicon resistor at a desired position of the polysilicon wiring on the master slice substrate; and means for connecting the polysilicon to each other by means of second and third layer wirings. In a semiconductor device, at least one part thereof has a part constituting a transistor electrode and a position where a hole for connection with a second layer wiring can be formed, and a polysilicon resistor is formed as necessary. The first type polysilicon wiring, which has a width and length that corresponds to the resistance value range as much as possible, can be opened for connection with the second layer wiring without including any transistor electrodes. Type 2 polysilicon wiring, which has at least two positions in a part thereof and has a width and length corresponding to the resistance value range in order to form a polysilicon resistor as necessary. and at least one of the positions where a connection hole can be formed in the second type polysilicon wiring with the second layer wiring is adjacent to a position where a connection hole can be formed in at least one of the first type polysilicon wiring. They are arranged relative to each other.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a part of a master slice board that is an embodiment of the present invention, 1 and 2 are transistors, B is a base electrode, E is an emitter electrode,
C is a collector electrode, 3 and 6 are each a polysilicon wiring including a base electrode, 4 and 7 are each a polysilicon wiring including an emitter electrode, 5 and 8 are each a polysilicon wiring including a collector electrode, and 9 is a transistor electrode. The polysilicon wirings 10 to 21, which are not present, respectively indicate positions where holes for connection between each polysilicon wiring and the second layer wiring can be formed. Here, in the polysilicon wiring 9, each of the connection hole opening positions 17 to 20 on the wiring is
Possible opening positions 10-12, 14-1 for connection of polysilicon wirings 3-8 including transistor electrodes, respectively
6 and are relatively arranged adjacent to each other.

Now, a case will be described below by way of example in which wiring work is performed to connect the emitter of transistor 1 and the emitter of transistor 2 on such a master slice board.

First, holes 11 and 17 are opened for connection holes, and the polysilicon wirings 4 and 9 are connected with the second layer wiring through these two holes. Next, holes 15 and 20 are opened for connections. hole position, and those 2
The process is completed by connecting the polysilicon wirings 7 and 9 with the second layer wiring through the two openings.

Now, in this wiring result, the wiring of the second layer wiring is similar to that of the master shown in FIG. On the slice base, the shortest length in the left-right direction in FIG. 1 can be taken. Furthermore, in the same way as the wiring work using the polysilicon wiring 9 described above, for all combinations in which any one electrode of the transistor 1 is connected to any one electrode of the transistor 2, the second layer wiring is Connection can be realized while keeping the wiring length to the shortest distance in the left and right directions of FIG. 1, respectively.

Regarding these connection methods, if the polysilicon wiring shape can be changed according to various connection relationships, there is no need for the second layer wiring, and in fact, the above second layer wiring can be used as a polysilicon wiring. It is sufficient if the two polysilicon wirings connected by the second layer wiring are connected by the replaced polysilicon wiring.

However, as explained in the background of the present invention, the polysilicon wiring shape needs to have a common shape for all possible connections, and at least a second layer wiring is required to realize each connection. Therefore, as shown in the connection side above, when the second layer wiring fulfills its function, it is necessary to specify the placement and wiring shape of the polysilicon wiring so that the wiring length or wiring area is kept to the minimum necessary. This has the meaning of the present invention.

Now, in order to explain in more detail that the above-mentioned effect is the best for all combinations of connections between the respective terminals of transistors 1 and 2, the polysilicon wiring 9 in FIG. Assuming that the master slice board shown in FIG. 2 is connected to the poly-silicon wiring 7 by the poly-silicon wiring itself on the line connecting the possible positions 15 and 20, the master slice board shown in FIG. 2 is different from that shown in FIG. 1. I'll try it.

In Figure 2, for example, when connecting the emitter terminal of transistor 2' and one of the terminals of transistor 1', the shortest length
Wiring can be completed by using the layer wiring at one location between 11' and 17' where connection holes can be opened, and the wiring length is half that of the case shown in Figure 1 where it is used at two locations. . However, in the case of a connection relationship other than this, for example, when connecting the base terminal of transistor 2' and the base terminal of transistor 1', the second layer is The wiring must be laid quite long in the vertical direction of Figure 2, and passing another second layer wiring in the left and right direction of Figure 2 at least in the section of dimension L' will prevent wiring crossover. Because it occurs, it becomes impossible. Alternatively, if wiring in the left and right directions is absolutely required at the same time, it is possible to open a hole for connection between the second layer wiring and the third layer wiring in one of the crossing wirings, at least in the vicinity of the crossing. The third layer wiring must be used after providing openings at the positions. Alternatively, in order to prevent the need for third-layer wiring as described above, as shown in FIG.
The polysilicon wiring corresponding to the polysilicon wiring 6' shown in the figure is extended from the left side of the transistors 2'' and 1'' downward in the vertical direction of FIG. 3 to the left side of the polysilicon wiring 3'' to form the polysilicon wiring 6'', and Possible connection hole position 14'' and connection hole possible position 1
0'' by the second layer wiring, but this generally increases the layout area of the polysilicon wiring itself and reduces the number of transistors per unit area. Even if the wiring area of the second-layer wiring and the third-layer wiring is reduced, overall, this is undesirable because it will reduce the amount of logic functions per unit area. A polysilicon wiring shape that allows the second layer wiring to be wired to the shortest length for connection between the collector of transistor 2'' and any one terminal of transistor 1'' cannot be achieved.

As is clear from the above explanation, the master slice board shown in Fig. 2 or 3 is more effective in reducing wiring area for specific connection relationships than that shown in Fig. 1. However, with regard to other connection relationships, this will lead to significantly disadvantageous results. Originally,
When designing a master slice board, regarding the circuits placed on the master slice board,
For example, even if there is a selection in advance based on the general classification of TTL-type circuits or CML-type circuits, once one of the circuit types has been decided upon, it is possible to select as many types of circuits as possible that occur in that type of circuit. Since the base plate is configured in a pattern that allows the configuration of the master slice base, among the examples shown in FIGS. 1 to 3, the one shown in FIG. 1 is particularly versatile as a master slice base. The reason for this is that the poly-silicon wiring 9 shown in FIG. This is because the positions where holes can be opened for connection are arranged adjacent to positions where holes can be opened for connection of each of the polysilicon wirings 3 to 8.

If it is sufficient that only a very small number of circuit types can be configured at a specific location on the master slice board, for example, the connection between FIG. 1 and FIG. It goes without saying that it is sufficient to have a master slice board shape that is optimal for only a few types of circuits, as in the example shown in the comparison, and in fact, as will be explained later in another embodiment of the present invention. In this way, it may be more effective to configure a part of the master slice base shape for the purpose of specific connection relationships only.

Next, according to the present invention, in order to form a polysilicon resistor in a portion where a resistor element is required due to the circuit configuration, a part of the polysilicon wiring arranged as described above is set according to a resistance value range expected in advance. One of its features is ensuring the wiring dimensions. Polysilicon resistors are formed by forming a combination of platinum and silicon, so-called platinum silicide, on the surface of polysilicon into which impurities have been implanted, and when forming the final polysilicon wiring, a portion of the wiring is selectively injected with platinum. This is done by leaving it unsilicided,
The resistance value is proportional to the layer resistance value of the polysilicon portion into which impurities have been implanted, the length of the resistance portion in the direction of current flow, i.e., the resistance length, and the width of the resistance portion perpendicular to the resistance length, i.e. It is inversely proportional to the resistance width.

In FIG. 1, there is a resistance width w in the polysilicon wiring 5.
1. The region where a polysilicon resistor can be formed with a resistor length l1 is
Resistance width w2 and resistance length l2 in the polysilicon wiring 8 part
The area where polysilicon resistance can be formed is secured.
For example, in the polysilicon wiring 5, if the polysilicon resistor forming area with the resistance width w1 and the resistance length l1 is not made into platinum silicide and a hole is opened at the connection hole possible position 13, the connection hole can be formed at the position 13. 13
A connection having a resistor element in series is completed between the transistor 1 and the collector electrode of the transistor 1. At this time,
The resistance length l1 corresponds to the maximum resistance value that can be formed in the polysilicon wiring 5. If a smaller resistance value is required, the resistance width w1 remains the same and a distance shorter than the resistance length l1 is formed using platinum silicide. It is better to leave it without turning it into something.

Now, the effect of using such a polysilicon resistor is that, like the conventional technology, the resistance element is formed in a part of the polysilicon wiring, so the element integration degree can be greatly improved. The present invention proposes to set the shape and dimensions of polysilicon wiring in advance, including the possibility of forming a resistor, so as not to impair the effect of using polysilicon resistors when standardizing the shape of polysilicon wiring. It is something to do.

Note that here, the shape and dimensions are first set.
In order to keep fluctuations in the absolute value of resistance caused by fluctuations in manufacturing conditions and fluctuations in the ratio of resistance values between multiple resistors within the permissible range, the minimum resistance width and minimum resistance length are determined, and the second In order not to exceed the minimum resistance width and minimum resistance length limits, a part of the polysilicon wiring is secured as an area where polysilicon resistance can be formed, so that the resistance width and resistance length correspond to the resistance value range as a circuit constant. It is done by twisting.

Next, on the master slice board shown in FIG. 4, which is another embodiment of the present invention, an exclusive OR circuit using the current switching type logic circuit shown in FIG. 5 is configured,
This is shown in Figure 6.

In Fig. 4, 1 to 10 are transistors, C
is a collector electrode, E is an emitter electrode, B is a base electrode, and 11 to 48 are polysilicon wirings, of which 11, 13, 15, 17, 26 to 29, 38,
44 does not include a transistor electrode. on the other hand,
Reference numerals 49 to 84 and 117 to 123 respectively indicate portions of positions where holes for connection between the first layer polysilicon wiring and the second layer wiring can be formed. That is, in FIG. 4, the positions where the connection holes can be formed are omitted on the polysilicon wirings that are congruent with each other. It has connection hole opening possible positions at the same positions as the connection hole opening possible positions 49 to 55 in .

On the other hand, 85 to 106 indicate the second layer wiring grid, respectively.
107 to 114 indicate third layer wiring grids.
In addition, in the polysilicon wiring 24, a polysilicon resistor forming area is secured having dimensions of a resistance width w1 and a maximum resistance length l1 corresponding to the resistance value range in order to form a polysilicon resistor. Although not shown, polysilicon resistor formation areas having dimensions of resistance width w1 and resistance length l1 are also secured in polysilicon wirings 22, 23, 25, 30 to 33 having a congruent shape with polysilicon wiring 24. Similarly, the polysilicon wiring 38 and the polysilicon wiring 44 having a shape congruent with it include the polysilicon wiring 44.
Resistance width w2, maximum resistance length l as written in
The area where polysilicon resistor can be formed has a dimension of 2.
The polysilicon wiring 40 and the polysilicon wiring 42 having a shape congruent with the polysilicon wiring 40 have a region where a polysilicon resistor can be formed with a resistance width w3 and a resistance length l3, and the polysilicon wiring 47 has a resistance width w4 and a resistance length l.
4, a resistor width w5, and a resistor length l5, a polysilicon resistor formation area is secured. Here, polysilicon wiring 1 that does not include transistor electrodes
1, 13, 15, 17, 26-29, 38, 44
are arranged relative to each other so as to be adjacent to the polysilicon wiring including the transistor electrode at least at one location where each connection hole can be formed, for example, the connection hole possible position 60 on the polysilicon wiring 29.
is the position 6 where the connection hole for the polysilicon wiring 21 can be opened.
0, a connection hole possible position 57 on the polysilicon wiring 25, and a connection hole possible position 57 corresponding to the connection hole possible position 57 on the polysilicon wiring 25 and the congruent shape polysilicon wiring 24. Adjacent. In addition, transistors 1 to 10 shown in FIG.
A plurality of the polysilicon wirings 11 to 48 are repeatedly arranged in parallel movement in the left-right direction in FIG. 4, and some adjacent portions are shown by broken lines. Moreover, in the vertical direction of FIG. 4, there is a mirror symmetry axis 11.
5, 116, and according to the rule, a plurality of pieces are also arranged repeatedly in the vertical direction.

In particular, at this time, polysilicon wiring 12, 14, 16,
18, 46, and 48 are removed from the rules for mirror surface symmetry so that the parts before folding and the parts after folding do not connect, as shown by broken lines in FIG. 4, so that they interlock. On the contrary, polysilicon wirings 11, 13, 15, 17 are mirror symmetry axis 1
The polysilicon wirings 11, 13, 15, and 17 are connected to the downwardly folded line 16 and extend to the side of the base terminals of the downwardly folded transistors 1 to 4, respectively.

Incidentally, the end portion of the repeating arrangement in the vertical direction is arranged so that the upper part in FIG. 4 is the outermost shell, and therefore, the number of repeating in the vertical direction is an even number. Now, on such a master slice base, the fifth
FIG. 6 shows a configuration of the current switching type exclusive OR circuit shown in the figure. FIG. 6 is depicted as having interconnections between many other circuits on the semiconductor substrate. Figure 6 completely corresponds to the master slice base part shown in Figure 4, and the fourth
Transistors 1 to 10 and polysilicon wiring 1 shown in the figure
1 to 48 are shown as transistors 1' to 10' and polysilicon wirings 11' to 48', respectively, in FIG. The entry has been omitted. Next, to show the correspondence between FIG. 5 and FIG. 6, the transistor Q1 shown in FIG. 5 is replaced with the transistor 3' in FIG.
Q4 to 2', Q5 to 6', Q6 to 5', Q7 to 9', Q8 to 7', Q9 to 8'
, the resistors R1 to R4 shown in FIG.
correspond to polysilicon resistors R1' to R4' in FIG. 6, respectively, and these positions are regions where polysilicon resistors can be formed with dimensions of resistance width w1 and resistance length l1 on polysilicon wiring 25 shown in FIG. 4, respectively. , polysilicon wiring 47
A region where a polysilicon resistor can be formed with a resistance width w5 and a resistance length l5 above the polysilicon wiring 42, a region where a polysilicon resistor can be formed with the dimensions of a resistance width w3 and a resistance length l3 above the polysilicon wiring 42, and a resistance width w2 above the polysilicon wiring 44. , a polysilicon resistor formed in a polysilicon resistor-formable region having a resistance length l2. In addition, power supply to terminals GND and V _EE and terminals V _ref 1 and V _CCV shown in Fig. 5
The constant voltage supply is provided by the second layer wiring terminal shown in Figure 6.
This is done by second layer wiring from each of GND, V _EE V _ref 1, and V _CCV , and these are respectively assigned to second layer wiring grids 95, 105, 85, and 106 shown in FIG. It should be noted that these four types of power supply wiring occupy the above-mentioned wiring grid and are used in common with other circuits lined up in the left and right direction in FIG. Here, if we follow an example of the connection relationship of the circuit shown in Fig. 5 with reference to Fig. 6, we will find that from the terminal GND shown in Fig.
In Figure 6, the connection series connects to the collectors of transistors Q2 and Q3 and the base of transistor Q9 through the connection hole A and the output of the third layer wiring terminal O1. Passing through resistor R1', polysilicon resistor R
The polysilicon wiring 25' including 1' is connected to the collector of the transistor 4' (corresponding to Q2 in FIG. 5) as it is, and is also connected to the second layer wiring M1 through the connection hole 6, and a part of the polysilicon wiring 25' including , in order to supply the output of the third layer wiring terminal O1 to another circuit located below in FIG.
It is connected to the polysilicon wiring 17' through the connection hole C. Further, a part of the wire is connected to the polysilicon wiring 29' through the connection hole d, and is also connected to the polysilicon wiring 22' through the connection hole e, and is connected to the collector of the transistor 1' (corresponding to Q2 in FIG. 5). .
On the other hand, the polysilicon wiring 29' reaches the second layer wiring M2 through the connection hole f, and is further connected to the polysilicon wiring 45' through the connection hole g, and is then directly connected to the transistor 8' (see FIG. Connect to the base of Q9 (compatible with Q9). Now, in this embodiment, the polysilicon wirings 26 to 29 shown in FIG. 4 have a great effect in suppressing the increase in load on the second and third layer wirings. That is, in FIG. 6, polysilicon wirings 27' to 2
9' plays the role of interconnecting the areas vertically separated by the second layer wiring terminal GND, and if these polysilicon wirings were not present, there would be no intersection with the second layer wiring terminal GND. To avoid this, third layer wiring must be used. If the third layer wiring is used in this way, the third layer wiring N1 is connected from the second layer wiring M3 in FIG. , and similarly passes through the connection hole B to reach the second layer wiring M4. Wiring for connection between other circuits that passes through the circuit part in the same diagram is impossible, at least as it is in Figure 6, and in fact, wiring on the third layer must be routed within the range shown in Figure 6. Moving onto the third layer wiring grid means extending the second layer wiring M3 to the left for the second layer wiring M1, and extending the second layer wiring M4 to the right for the second layer wiring terminal I2. It is impossible because it cannot be done. Such polysilicon wiring 27'-2
The effect of 9' is caused by the same reason as described for polysilicon wiring 9 in FIG. Among these, in particular, the effect of suppressing the increase in the burden on the third layer wiring is that the polysilicon wiring 14',
18' eliminates the wiring intersection with the second layer wiring M5, and the polysilicon wirings 15' and 17'
The wiring intersection between the second layer wiring M5 and the second layer wiring terminal V _ref 1 is connected to the first layer polysilicon wiring 23', 24', 32',
33' eliminates wiring crossover with the second layer wiring M1, M3, I2 when connecting the second layer wiring terminal GND and each collector of the transistors 2', 3', 7', 8'. Therefore, there is no need to use third-layer wiring, and the effect is fully demonstrated.

On the other hand, in this embodiment, the effect of arranging the connection holes adjacent to each other is not obvious at first glance in FIG. 6 due to various connection relationships such as connections between transistors separated by one or more transistors. is at least the second layer wiring M
6, M7, M8, and M1, M9, M10, M1
1. In some parts of O2, the wiring length between the openings is the shortest distance, which creates extra space in the second layer wiring grid, making it possible to connect long distances between other circuits. At the same time, on the one hand, the second layer wiring density is correspondingly relaxed, and it becomes possible to correspond all of the transistors 1' to 8' to the eight transistors in the circuit diagram. That is, there are no usable and abandoned transistors among 1' to 8'. Next, when we compare the polysilicon wirings 40' and 42', which have congruent shapes, we find that although they are placed under equal conditions on the master slice substrate shown in FIG. Wiring 40' serves to connect the emitters of transistors 5' and 6' (corresponding to Q6 and Q5 in Figure 5) to the collector of current source transistor 9' (corresponding to Q7 in Figure 5). On the other hand, the polysilicon wiring 42' is connected to the emitter follower transistor 7' (corresponding to Q8 in Fig. 5).
It is used as an emitter follower resistor and polysilicon wiring for continuous connection to it. The same thing is true for polysilicon wiring 2 that has congruent shapes with each other.
5' and polysilicon wiring 23', 24', 32', 3
The same can be said for the area between 3' and 3', which shows that the fact that one polysilicon wiring can be used as a wiring in some cases, and in some cases as a wiring that includes a resistive element, facilitates design and improves device integration. On the other hand, in order to form a resistance element at a desired position, the effect is only possible because the shape and dimensions of the polysilicon wiring are secured in advance on the master slice substrate to match the resistance range. It shows.

Note that the transistors 9 and 10 in FIG. 5 are arranged for exclusive use as current source transistors in a current switching type logic circuit, and therefore, the polysilicon wirings 46 and 48 are ,
For the sole purpose of supplying a constant voltage for the current source to the base of the transistor, the polysilicon wiring 47 includes each of the emitter resistors for these two current sources in a part thereof, and the polysilicon wiring 47 is placed at a position where a connecting hole can be formed. 8
4 is arranged for the purpose of connecting to the second layer wiring on the second layer wiring grid 105. As mentioned in a part of the explanation of Figure 1, for a limited type of circuit called a current source, the transistors for that purpose are replaced by a group of transistors that handle normal signal input (transistors 1 to 8 in Figure 4). group)
Polysilicon wiring is placed at a distance from the current source, and for such limited uses, it is important to note that the polysilicon wiring does not have a configuration that can be used for multiple purposes, but its shape is specified only for the exclusive purpose of the current source. In particular, by isolating such a part from the above transistor group, it becomes easier to design the part of transistors 1 to 8 shown in FIG. By arranging elements necessary for the circuit configuration in a part of the wiring-only area, which is often reserved for wiring, so as not to affect the wiring at all, this also has the effect of improving the element integration. moreover,
A method similar to the above is applied to polysilicon wiring 2 shown in FIG.
1 is also taken. That is, the polysilicon wiring 21 includes the emitter electrodes of each of the transistors 3 and 4, and the emitter-to-emitter connection of the transistors has already been completed on the master slice substrate. This is a so-called phenomenon that always appears in current-switching logic circuits.
This means that the CML common emitter has been connected in advance, and in fact, as shown in FIG. 6, transistors Q1 and Q2 shown in FIG.
By associating them with and 4', it is possible to automatically connect the emitters of the two transistors, and as a result, the polysilicon wiring including the emitter of transistor 3 shown in FIG.
and 3, and the polysilicon wiring 28 can be extended to that part to a position where it is sandwiched between the emitter terminals of the transistors 2 and 3, as shown in the same position in FIG. As a result, the second layer wiring M12 is not wired in the vertical direction shown in FIG.
The layer wiring M10 has wiring portions in the vertical direction. )
Therefore, the second layer wiring M1 can be arranged to allow the presence of the second layer wiring M3, and as a result of the above, it is possible to arrange the third layer wiring N1. The effect here is also due in part to the fact that the polysilicon wiring shape, which is limited to a specific application, is constructed on the master slice substrate.

As explained above, the present invention aims to shorten the manufacturing period required for each product type in the master slice method by making the polysilicon wiring have a common shape for all products, and by using the second layer wiring and the third layer wiring. This paper presents an effective method for defining polysilicon wiring shapes to reduce the burden on second-layer wiring and third-layer wiring when configuring various circuits on a chip.

In the master slice semiconductor device of the present invention, by adding a second type of polysilicon wiring that does not include transistor electrodes, the commonality of the first layer polysilicon wiring can be increased and the degree of freedom can be increased, so that it can be manufactured into individual products. This has the effect that the burden on the second layer wiring and third layer wiring can be reduced, and the manufacturing period can be shortened.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a configuration pattern of one embodiment of the present invention, FIGS. 2 and 3 are diagrams showing a modification to explain the effect of FIG. 1, and FIG. 4 is a diagram showing another embodiment of the present invention. FIG. 5 is a circuit diagram of an exclusive OR circuit configured using a current switching type logic circuit placed on the configuration pattern of the embodiment shown in FIG. 4, and FIG. 6 is a diagram showing an example configuration pattern. , is a diagram showing a configuration pattern in which the circuit shown in FIG. 5 is realized on the configuration pattern of the embodiment shown in FIG. 4; In Figures 1 to 3, 1, 2, 1', 2',
1″, 2″……transistor, 3 to 8, 6′, 3″,
6''...First type polysilicon wiring, 9...First type polysilicon wiring, 10 to 21, 10', 11', 1
4', 17', 10'', 14''...Positions where connection holes can be formed, w1, l1 and w2, l2...Dimensions of areas where polysilicon resistors can be formed, L...Transistor spacing,
C...Collector electrode, B...Base electrode, E...
Emitter electrode, 1 to 1 in Figures 4 to 6
0,1'-10'...transistor, 11-48,
11'-48'...First layer polysilicon wiring, 49-8
4,49' to 84'... Connection hole possible position, 85
~106...Second layer wiring grid, 107-114...
...Third layer wiring grid, 115, 116...Mirror symmetry axis, w1, l1; w2, l2; w3, l3; w
4, l4; w5, l5... Dimensions of area where polysilicon resistor can be formed, Q1 to Q9... Transistor, R1
~R4...Resistance, C...Collector electrode, B...Base electrode, E...Emitter electrode, R1'~R4'...
...Polysilicon resistor, a to g... Connection hole, A, B
... Connection holes, M1 to M12 ... second layer wiring,
N1...3rd layer wiring, V _ref 1, GND, I2, O
2, V _ref 2, V _EE , V _CCV ... 2nd layer wiring terminal, I
1, O1...First layer wiring terminal.

Claims (1)

[Claims] 1 A first transistor region having a collector electrode region, an emitter electrode region, and a base electrode region in this order; a first transistor region having a base electrode region, an emitter electrode region, and a collector electrode region in this order; a second transistor region in which the regions face each other and the electrode regions are arranged in a straight line; and a portion adjacent to each emitter electrode region of the first and second transistor regions in parallel with the straight line; A first polycrystalline silicon layer formed on a plane different from that of the first and second transistor regions, and connected to each base electrode region of the first and second transistor regions and connected to the straight line. second and third polycrystalline silicon layers extending close to the first polycrystalline silicon layer and formed on the different planes at right angles to the first polycrystalline silicon layer; and emitters of the first and second transistor regions. fourth and fifth polycrystalline silicon layers formed on the respective emitter electrode regions connected to the electrode regions; and fourth and fifth polycrystalline silicon layers respectively connected to the respective collector electrode regions of the first and second transistor regions. A plurality of sets of the first and second transistor regions and the sixth and seventh polycrystalline silicon layers extending between the first and second transistor regions on the straight line on the plane are one set. A master slice semiconductor device characterized in that first to seventh polycrystalline silicon layers are formed on a single semiconductor substrate.