JPH01200811A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

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Publication number
JPH01200811A
JPH01200811A JP2602388A JP2602388A JPH01200811A JP H01200811 A JPH01200811 A JP H01200811A JP 2602388 A JP2602388 A JP 2602388A JP 2602388 A JP2602388 A JP 2602388A JP H01200811 A JPH01200811 A JP H01200811A
Authority
JP
Japan
Prior art keywords
current
transistor
input signal
circuit
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2602388A
Other languages
Japanese (ja)
Inventor
Yutaka Hayashi
豊 林
Naoyuki Kato
直之 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2602388A priority Critical patent/JPH01200811A/en
Publication of JPH01200811A publication Critical patent/JPH01200811A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To clearly remove the noise of an input signal by adding a resistance to the emitter of a second transistor(TR) in an AGC circuit to have a current mirror circuit. CONSTITUTION:The input signal from an input terminal VIN is inputted through an amplitude/voltage converting circuit A/V to the base of a TR Q1. A current i1 to be approximately equal to a collector current to flow according to the base current of the TR Q1 is made to flow to the collector of a TR Q2. At the same time, a collector current i2 of a TR Q3 of a current mirror circuit 1 is also made to flow according to the base voltage of the TR Q1. At such a time, since the collector voltage of the TR Q2 is lowered by a resistance RE, the current i2 is made into a value larger than the current i1. By inputting the current i2 to the bases of TRs Q4 and Q5, even with the input signal VIN to be small, the current i2 of the current mirror circuit 1 is made into the large current, and it is inputted to a non-inverting amplifier circuit A. Consequently, since a gain is made large, simultaneously, quick and constant, the noise of the input signal can be clearly removed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、自動利得別画回路(以下AGC回・烙)K
関し、特にその利得特性の向上に関するものである。
[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to automatic gain dividing circuit (hereinafter referred to as AGC circuit) K.
In particular, it relates to improving its gain characteristics.

〔従来の技術〕[Conventional technology]

第3図は従来の一般的なカレントミラー回路?有すAG
C回路である。図において、(OP)は−万の入力端子
(VIN) VC入力信号が印加される演算項@器、(
A/V)は前記入力信号(VrN)の振11111を電
圧を変換する振幅電圧変換101賂、(R1)は振幅電
圧変換+1=ll路(A/V)によって変換された電圧
がベースに印加されるnpn )ランジスタ、(R2)
μpnp)ランジスタでnpn)ランジスタ(R1)の
コレクタに接続される、(R3)はpnpトランジスタ
(R2)とカレントミラー回路を構成するpnp )ラ
ンジスタ、(R4)はトランジスタ(R3)のコレクタ
電流がベースに印加されるnpnのトランジスタ、(R
5)はそのベースICp n p )ランジスタ(R3
)のコレクタ電流が印加されると共に、npn)ランジ
スタ1o4)と逆接続されるnpn )ランジスタ、(
R1)は抵抗であり、npnトランジスタ(θ4)、(
θ5)の共通の出力が前記演算増幅器(OP l(/J
能万の端子にこの抵抗(R1)を通して入力される。(
R21、(Rs )は抵抗であり、この演其増@器(O
P)は抵抗(+(11,(R2)を前記抵抗(R1]、
npn )ランジスタ(θ4)、(θ5)ニよシ非反転
項幅回路IAlを構成している。(Vout)は演算増
幅器N)P)t/>出力端子、(tマaa)はカレント
ミラー回路(21に印加される電源端子である。
Is Figure 3 a conventional general current mirror circuit? AG with
It is a C circuit. In the figure, (OP) is the -1000 input terminal (VIN), the operand to which the VC input signal is applied, (
A/V) is the amplitude voltage conversion 101 voltage that converts the amplitude 11111 of the input signal (VrN) into a voltage, and (R1) is the voltage converted by the amplitude voltage conversion +1=ll path (A/V) applied to the base. npn) transistor, (R2)
μpnp) transistor connected to the collector of npn) transistor (R1), (R3) forming a current mirror circuit with pnp transistor (R2) pnp) transistor, (R4) based on the collector current of transistor (R3) npn transistor, (R
5) is its base IC p n p ) transistor (R3
) is applied, and the npn) transistor is reversely connected to the npn) transistor 1o4).
R1) is a resistor, and npn transistor (θ4), (
The common output of the operational amplifier (OP l(/J
It is input to the power terminal through this resistor (R1). (
R21, (Rs) is a resistance, and this
P) is a resistance (+(11, (R2)) is the resistance (R1],
npn) transistors (θ4) and (θ5) constitute a non-inverting term width circuit IAl. (Vout) is the output terminal of the operational amplifier N)P)t/>, and (tmaaa) is the power supply terminal applied to the current mirror circuit (21).

次に動作について説明する。演算増幅5(OP)の−万
の入力端子に入力信号が印加されると同時に入力信号が
、入力端子(7I N )から入力され掘・郵嵐圧変換
[開路(A/V )を通して入力信号の損幅が電圧に変
換され、トランジスタ(θ1)のベースに入力される。
Next, the operation will be explained. At the same time, the input signal is applied to the -1000 input terminal of the operational amplifier 5 (OP), and the input signal is input from the input terminal (7I N ) and is converted to the input signal through the open circuit (A/V). The loss width is converted into a voltage and input to the base of the transistor (θ1).

そのベースに応じてトランシタ(θ1)のコレクタ電流
が流れこのコレクタ電流とほぼ同じ位の電流がトランジ
スタ(θ2)のコレクタに流れる。トランジスタ(θ2
)、(θ3)はカレントミラー回路(21を構成してい
るのでトランジスタCθ3)のコレクタ電流はトランジ
スタ(θ2)り垣しクタ電流と同一にトランジスタ(θ
2)のベース電圧ニ応じ流れる。そしてそのトランジス
タ(θ3)のコレクタ電流がトランジスタC夕4)(θ
5)の共通ベースに入力され、トランジスタ(θ4)(
θ5)の共通の出力電流が流れる。この出力電流はトラ
ンジスタ(θ+ 1(’75 )のベース電流が太きく
なると大さくなり、ある値で一定となる。そしてトラン
ジスタ(θ4)(θ5)の出力は抵抗(R1)i通して
前記の演算増幅器(oP)の他の端子に入力さnる。ま
たこの演算増幅器(OP)は抵抗IRQ 1(R3)(
R1)、トランジスタ(θ4)C84)により非反転増
幅回路囚?購取しておltl力端子(vout)7/:
より出力される。
A collector current of the transistor (θ1) flows in accordance with the base, and a current approximately equal to this collector current flows to the collector of the transistor (θ2). Transistor (θ2
) and (θ3) constitute a current mirror circuit (21), so the collector current of transistor Cθ3 is the same as the collector current of transistor (θ2).
2) flows depending on the base voltage. Then, the collector current of the transistor (θ3) is the transistor C4)(θ
5) is input to the common base of the transistor (θ4) (
A common output current of θ5) flows. This output current increases as the base current of the transistor (θ+1('75) becomes thicker, and becomes constant at a certain value.Then, the output of the transistor (θ4) (θ5) is passed through the resistor (R1) i to the above-mentioned It is input to the other terminal of the operational amplifier (oP).This operational amplifier (OP) is also connected to the resistor IRQ1 (R3) (
R1), transistor (θ4) C84) creates a non-inverting amplifier circuit? Purchase LTL power terminal (vout) 7/:
It is output from

その時の入力信号電圧(VIN )−出力信号低圧(V
o ut )特性を第4図に示す。この図において振幅
電圧変換lo]路(A/VJ ct)出力電圧を(VA
/V)とする。(vrNl)はトランジスタ(θ4)(
θ5)が作u3し始める入力信号電圧であり、(VIN
2)はトランジスタ(θ4)(θ5)の出力電流が一定
となる入力信号電圧である。(vzul)−(Vxu2
)間はトランジスタ(θ4)(θ5)の出力電流が変化
している。その結果前記のような動作で第4図のような
特性曲線となる。この図の示す利得特性曲裸の特性は入
力信号電圧が(vrN)以下の時げ入力イg号がクリア
に除去され、又(VIN2)以上の時はクリアに増幅さ
れる。(vxnx )−(vxpt2)間は入力信号電
圧に応じてm幅されるということである。
At that time, input signal voltage (VIN) - output signal low voltage (V
Out) characteristics are shown in FIG. In this figure, the amplitude voltage conversion lo] path (A/VJ ct) output voltage is (VA
/V). (vrNl) is the transistor (θ4) (
θ5) is the input signal voltage that u3 starts to generate, and (VIN
2) is an input signal voltage at which the output current of the transistors (θ4) (θ5) becomes constant. (vzul)-(Vxu2
), the output currents of the transistors (θ4) and (θ5) are changing. As a result, the operation as described above results in a characteristic curve as shown in FIG. The gain characteristic curve shown in this figure shows that when the input signal voltage is below (vrN), the input signal voltage is clearly removed, and when it is above (VIN2), it is clearly amplified. This means that the width between (vxnx) and (vxpt2) is changed by m depending on the input signal voltage.

〔発明が解決しようとする課I〕[Problem I that the invention seeks to solve]

従来の一般面なカレントミラー回路を有するAGC回g
11は以上のように構成されているため第4図における
(vrsx )−(vnr2)間の特性に頃き)は一定
となってし甘う。すなわち、入力信号のノイズがクリア
に除去されないという課頭があった。
AGC circuit with conventional general current mirror circuit
11 is configured as described above, the characteristic between (vrsx) and (vnr2) in FIG. 4 remains constant. In other words, there was a problem that noise in the input signal was not clearly removed.

この発明は上記のような課印金解消するためになされた
もので、入力信号のノイズをクリアに除去できるAGC
回路を得ることを目的とする。
This invention was made in order to eliminate the above-mentioned royalties, and it is an AGC that can clearly remove noise from input signals.
The purpose is to obtain a circuit.

〔課題?解決するための手段〕〔assignment? Means to solve]

この発明に係る、カレントミラー回路を有する、AGC
回路け、第2のトランジスタのエミッタに抵抗をy3え
たものである。
AGC having a current mirror circuit according to the present invention
The circuit has a resistor of y3 added to the emitter of the second transistor.

〔作用〕[Effect]

この発明におけるAGC回路は第2のトランジスタのエ
ミッタにつけた抵抗によって丼反転項幅回酪を利砒する
電流2大きくすることができ、その結果利得特性が向上
する。
In the AGC circuit according to the present invention, the current 2 for increasing the width of the inversion term can be increased by the resistor attached to the emitter of the second transistor, and as a result, the gain characteristics are improved.

〔発明の実施例〕[Embodiments of the invention]

第1図ハコノ発明’7) −実* $I VCなるAG
C回路である。
Figure 1 Hakono Invention'7) -Real* $I VC becoming AG
It is a C circuit.

なお図中第3図と同一符号は相当部分?なすものであり
説明は省略する。以下この発明の一実羅列Vこついて説
明する。図において(RE lにカレントミラー回路I
ll ’i 構成しているPNP)ランジスタ(θ1)
のエミッタに接続された抵抗である。
In the figure, are the same symbols as in Figure 3 corresponding parts? The explanation will be omitted. Hereinafter, a specific enumeration of this invention will be explained. In the figure (RE l is the current mirror circuit I)
ll 'i Constituting PNP) transistor (θ1)
is a resistor connected to the emitter of .

以下この発明の一害施例になるAGC回路の動作につい
て説明する入力端子(VIN)から入力信号を入力し振
;鴫電Iff換[司路(A/V )を通して入力旧号の
振I固が低圧に変換されたトランジスタ(θ1)のベー
スに入力される。そのベース磁圧VC心Uてトランジス
タ(θ1)のコレクター流が流れそのコレクタ4(流と
ほぼ同じトランジスタlθ2)のコレクタ電光(以下電
流11)が流れる。
The following describes the operation of the AGC circuit which is an example of the present invention.An input signal is input from the input terminal (VIN), and the input signal is input through the Iff circuit (A/V). is input to the base of the transistor (θ1), which is converted to a low voltage. A collector current of the transistor (θ1) flows through the base magnetic pressure VC, and a collector current (hereinafter referred to as current 11) of the collector 4 (transistor lθ2, which is substantially the same as the current) flows.

また同時にカレントミラー回路111 金?j★成して
いるトランジスタ(θ3)のコレクタ回流(以下電流1
2)もトランジスタ(θ1)のペース電圧に心して流れ
る。この時抵抗(RF、)7C:よってトランジスタ(
θ2)のコレクタ電圧が下がるので電流12が電流すよ
りも大へな1直となる。その電流i2がトラン・ジスタ
(ua l(G lのベースに入力される。その結果小
さな入力信号でもカレントミラー回路12)の電流i2
は大きな電流となり非反転増幅回路・Alに入力きれる
わけでおるから四部か犬をくなりかつ早く一定となる。
At the same time, current mirror circuit 111 Gold? The collector circulation current (hereinafter referred to as current 1) of the transistor (θ3)
2) also flows based on the pace voltage of the transistor (θ1). At this time, the resistor (RF, ) 7C: Therefore, the transistor (
Since the collector voltage of θ2) decreases, the current 12 becomes a current larger than the current I. The current i2 is input to the base of the transistor (ua l (G l). As a result, even if the input signal is small, the current i2 of the current mirror circuit 12
Since the current becomes a large current and can be input to the non-inverting amplifier circuit/Al, the current becomes constant and quickly becomes constant.

その時の入力信号電圧(VII−出力信号電圧(V□)
ua)特性を第2図に示す。図中第4図と同−符号i−
を相当部分をなすものであり説明は省略する。(VII
3)は上記のAC3回:晶において(θ4)(θ5)の
出力電流が一定となりAGC回路の利得が一定となる入
力信号電圧である。この図の示す利得特性曲線の特性は
、従来のAGCLgJ路の特性に比べ、入力信号が(V
II2)より低い値の(V+s3)より利得が一定とな
る。そして(VII1)−(Vxs3)間の傾きが大き
くなっていの0このことにより(VI N )以下入力
信号かクリアに除去できていることがわかる。
Input signal voltage at that time (VII - output signal voltage (V□)
ua) characteristics are shown in FIG. In the figure, the same symbol as in Fig. 4 is i.
The explanation is omitted since it constitutes a considerable part. (VII
3) is the input signal voltage at which the output currents (θ4) and (θ5) in the above AC three-time crystal are constant and the gain of the AGC circuit is constant. The characteristics of the gain characteristic curve shown in this figure are different from those of the conventional AGCLgJ path when the input signal is (V
II2) The gain becomes constant at a lower value (V+s3). Then, the slope between (VII1) and (Vxs3) becomes large and becomes zero. This shows that input signals below (VIN) can be clearly removed.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、カレントミラー回路を
有するAGC回路全第2のトランジスタのエミッタVC
抵抗を接続した臂成としたので入力信号のノイズがクリ
アに除去されるという幼果がある。
As described above, according to the present invention, the emitter VC of all second transistors in the AGC circuit having a current mirror circuit
The advantage of this method is that the noise in the input signal can be clearly removed because the resistor is connected to the arm.

【図面の簡単な説明】[Brief explanation of the drawing]

41図はこの発明によるAGC回路全示す回路図、第2
図はこの発明によるAGC回路の利得特性(入力信号電
圧(VI N )K対する出力電圧(vout)の特性
)曲線を示すグラフ、第3図は従来のAGC回路を示す
回路図、第4図は従来のAGCLgJ路の利得特性を示
すグラフである。 図において(θ1)、lθ4)(θ5)はNPN トラ
ンジスタ、(θ2)、fθ3)はPNP トランジスタ
、 (REI。 fRl)、(R21,1R31は抵抗、(OP社演算増
幅回路、(tVcc)は重連端子、(Vuq)は入力端
子である。
Figure 41 is a circuit diagram showing the entire AGC circuit according to the present invention.
The figure is a graph showing the gain characteristic (characteristic of output voltage (vout) versus input signal voltage (VIN)K) curve of the AGC circuit according to the present invention, FIG. 3 is a circuit diagram showing a conventional AGC circuit, and FIG. 3 is a graph showing gain characteristics of a conventional AGCLgJ path. In the figure, (θ1), lθ4) (θ5) are NPN transistors, (θ2), fθ3) are PNP transistors, (REI. fRl), (R21, 1R31 are resistors, (OP company operational amplifier circuit, (tVcc) is a The continuous terminal (Vuq) is an input terminal.

Claims (1)

【特許請求の範囲】[Claims] 一方の入力端子に入力信号が印加される演算増幅器と前
記入力信号の振幅を電圧に変換する回路と、この変換回
路によつて変換された電圧がベースに印加される一方の
極性の第1トランジスタと、この第1のトランジスタの
コレクタに接線されると共にこの第1のトランジスタと
は逆極性の第2トランジスタとこの第2のトランジスタ
とカレントミラー回路を構成する第3のトランジスタの
コレクタ電流がその共通のベースに印加されると共に、
互に逆接続の第4第5のトランジスタを備えこの第4第
5のトランジスタの共通の出力が前記演算増幅器の他方
の入力端子に加えられるようにしたものにおいて前記第
2のトランジスタのエミッタに接続した抵抗を特徴とす
る自動利得制御回路。
an operational amplifier to which an input signal is applied to one input terminal; a circuit for converting the amplitude of the input signal into a voltage; and a first transistor of one polarity to which the voltage converted by the conversion circuit is applied to the base. A second transistor which is tangential to the collector of the first transistor and has a polarity opposite to that of the first transistor, and a third transistor that forms a current mirror circuit with the second transistor have their collector currents in common. is applied to the base of
The fourth and fifth transistors are connected in reverse to each other, and the common output of the fourth and fifth transistors is applied to the other input terminal of the operational amplifier, and the fourth and fifth transistors are connected to the emitter of the second transistor. Automatic gain control circuit featuring a resistor.
JP2602388A 1988-02-05 1988-02-05 Automatic gain control circuit Pending JPH01200811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2602388A JPH01200811A (en) 1988-02-05 1988-02-05 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2602388A JPH01200811A (en) 1988-02-05 1988-02-05 Automatic gain control circuit

Publications (1)

Publication Number Publication Date
JPH01200811A true JPH01200811A (en) 1989-08-14

Family

ID=12182105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2602388A Pending JPH01200811A (en) 1988-02-05 1988-02-05 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPH01200811A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100946735B1 (en) * 2008-04-10 2010-03-12 한국전기연구원 Pulse realization apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6038903A (en) * 1983-08-11 1985-02-28 Matsushita Electric Ind Co Ltd Local oscillating circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6038903A (en) * 1983-08-11 1985-02-28 Matsushita Electric Ind Co Ltd Local oscillating circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100946735B1 (en) * 2008-04-10 2010-03-12 한국전기연구원 Pulse realization apparatus

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