JPH01192147A - Substrate for semiconductor device - Google Patents
Substrate for semiconductor deviceInfo
- Publication number
- JPH01192147A JPH01192147A JP1779888A JP1779888A JPH01192147A JP H01192147 A JPH01192147 A JP H01192147A JP 1779888 A JP1779888 A JP 1779888A JP 1779888 A JP1779888 A JP 1779888A JP H01192147 A JPH01192147 A JP H01192147A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- dam part
- sealing
- resin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims description 7
- 239000004593 Epoxy Substances 0.000 claims 1
- 229910000831 Steel Inorganic materials 0.000 claims 1
- 239000000919 ceramic Substances 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 claims 1
- 239000010959 steel Substances 0.000 claims 1
- 238000007789 sealing Methods 0.000 abstract description 27
- 239000011347 resin Substances 0.000 abstract description 18
- 229920005989 resin Polymers 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 15
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ICカード、ノ為イブリツドエCなどを製
造する際に用する半導体装置用基板に関するものである
0
〔従来の技術〕
以下、従来の半導体装置用基板として工0カードモジュ
ール用基板について図を用匹て説明する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a substrate for a semiconductor device used in manufacturing IC cards, hybrid electronic devices, etc. [Prior Art] The following describes the conventional technology. A substrate for an industrial card module as a substrate for a semiconductor device will be explained with reference to the drawings.
第3図(a) 、 (b) 、 (Q)は、封止前のI
Cカードモジュールの、それぞれ上面図(表側:半導体
素子側)。Figures 3 (a), (b), and (Q) show I before sealing.
FIG. 4 is a top view (front side: semiconductor element side) of each C card module.
下面図(裏側:を極側)、側面図である。They are a bottom view (back side: pole side) and a side view.
第4図(−) 、 (b) 、 (c)は、封止後の工
Cカードモジュールのそれぞれ上面図、下面図、断面図
マある。FIGS. 4(-), (b), and (c) are a top view, a bottom view, and a sectional view, respectively, of the C-card module after sealing.
第5図(a) 、 (b)は、第3図におけるそれぞれ
(d)。Figures 5(a) and 5(b) are respectively (d) in Figure 3.
(e)部の拡大図である。It is an enlarged view of part (e).
第6図(a) 、 (b) 、 (c) Tri 、工
Cカードモジュール用基板を用いて封止する際のプロセ
スの説明図で、そハぞrL、金型を型締めする前、型締
め後及び封止後における第3図f −f’の断面図であ
る。Figure 6 (a), (b), (c) is an explanatory diagram of the process of sealing using a Tri-C card module substrate; FIG. 3 is a cross-sectional view of FIG. 3 f-f' after tightening and sealing;
第7図(a) 、 (b) 、 (c) Vi、工Cカ
ードモジュール用基板を用いて封止する際のプロセスの
説明図で、第6図(a) 、 (t)) 、 (c)の
紙面に垂直、かつ、第3図のg−glにおける断面図で
ある。Fig. 7 (a), (b), (c) is an explanatory diagram of the process of sealing using the Vi, Engineering C card module substrate; Fig. 6 (a), (t)), (c ) is a sectional view perpendicular to the plane of paper and taken along g-gl in FIG. 3.
図にお−で、(1)は基材、(2)は導体、(3)は半
導体素子、(4)は導体(2)と半導体素子(3)を電
気的に接続すみ金属細線、(5)は基板の裏面にあるI
Cカードモジュールと外部を電気的に接続する外部電弧
、(6)け導体〔2)と外部電極を電気的に接続する貫
通孔であるスルーホール、(71半導体素子(3)と基
材(1)又は導体(2)の一部を接続するD/B材0(
8)は封止樹脂、(9)は金型で(9−a)h上金!、
(9−’b)tf下金型、αOは金型内に設けであ
る封止樹脂が注入される部分でキャビティ、(2)は基
板裏面の外部電極の間、基板周囲に発生した樹脂バリ、
(2)は金型(9)に設けた溝で、封止樹脂(8)が外
部からキャビティα0へ注入される際の通路でゲートと
呼ばれる部分であるOa3は基板の裏面にある外部電極
(5)間及び基板と金型(9)間のすき間、α4Vi従
来のICカードモジュール基板のGNI)!極、(至)
は組立てられた基板である。In the figure, (1) is the base material, (2) is the conductor, (3) is the semiconductor element, (4) is the thin metal wire that electrically connects the conductor (2) and the semiconductor element (3), ( 5) is the I on the back side of the board.
An external arc that electrically connects the C card module to the outside, (6) a through hole that electrically connects the conductor [2] and the external electrode, (71 semiconductor element (3) and the base material (1) ) or D/B material 0 (
8) is the sealing resin, (9) is the mold, and (9-a) h upper metal! ,
(9-'b) tf lower mold, αO is the cavity where the sealing resin is injected inside the mold, (2) is the resin burr generated around the substrate between the external electrodes on the back of the substrate. ,
(2) is a groove provided in the mold (9), and Oa3, which is a passage called a gate and is a passage when the sealing resin (8) is injected from the outside into the cavity α0, is an external electrode ( 5) Gaps between the board and the mold (9), GNI of α4Vi conventional IC card module board)! pole, (to)
is the assembled board.
従来の工Cカードモジュールの裏面の電極におりて、
GND電甑α41は、第3図(1))に示す様な形状に
なって^る。At the electrode on the back of the conventional C card module,
The GND electric oven α41 has a shape as shown in FIG. 3 (1)).
とのGND [hα4Jは、ICカードモジュールにお
^では図のように設けて匹るが、通常のハイブリッドI
Cにおいてはな^5
次にICカート0モジユールの製造プロセスのうち。GND [hα4J is comparable to the IC card module by installing it as shown in the figure, but it is not suitable for normal hybrid I
In C^5 Next, let's look at the manufacturing process of the IC cart 0 module.
封止プロセスを、この発明に特に関係の深層低圧トラン
スファー法を例に説明する。The sealing process will be explained using the deep low pressure transfer method, which is particularly relevant to this invention, as an example.
ICカードモジュールを製造する際、基材(1)に半導
体素子(3)をD/B材(7)を用いて接着し、その後
。When manufacturing an IC card module, a semiconductor element (3) is bonded to a base material (1) using a D/B material (7), and then.
金やアルミニウムを素材とする金属細線(4)を用いて
半導体素子(3)と基材(1)を電気的に接続する〇基
板(至)を封止樹脂(8)で封止したのが第4図に示す
ICカードモジュールであるう
封止工程を第7図を例に説明すると、第7図(a)に示
すように基板(至)を金型(9)の所定の場所(キャビ
ティα0)に置き、金製(9)を聾締めした後、外部か
らゲート@を通して封止樹脂(8)が注入され、金型(
9)内で硬化させて完成する。The semiconductor element (3) and the base material (1) are electrically connected using a thin metal wire (4) made of gold or aluminum. The substrate (to) is sealed with a sealing resin (8). To explain the sealing process for the IC card module shown in FIG. 4 using FIG. 7 as an example, as shown in FIG. α0), and after tightening the metal (9), the sealing resin (8) is injected from the outside through the gate@, and the mold (
9) Complete by curing inside.
従来の半導体装置用基板は以上のように構成されて−る
のf、外部電極(5)のすき間(至)の部分が通路とな
シ、封止樹脂(8)の注入時に、封止樹脂(8)が流れ
込み、樹脂パリIになってしまう。The conventional substrate for a semiconductor device is constructed as described above, and the gap between the external electrodes (5) is a passage. (8) flows in and becomes resin Paris I.
第6図〜第7図にパリの生成状況を示す。Figures 6 and 7 show the generation status of Paris.
この発明は上記のような問題点を解消するためになされ
たもので、封止樹脂(8)の樹脂バリαDが発生しない
、低圧トランスファー法による樹脂封止工Cカード、あ
るいけハイブリッドICを製作することができる半導体
装置用基板を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and produced a resin-encapsulated C card and a hybrid IC using a low-pressure transfer method that does not generate resin burrs αD of the sealing resin (8). The object of the present invention is to obtain a substrate for a semiconductor device that can be used for semiconductor devices.
この発明に係る半導体装置用基板は、基板の裏面、半導
体素子を搭載して^なの側の基板の周囲にダムの部分を
設けたものである〇
〔作用〕
この発明における、基板の裏面周囲に設けたダムの部分
け、上記基板を金型を用ハて樹脂封止する際に、裏面の
電極間に樹脂が流れ込み、樹脂バリができるのを防ぐ。The substrate for a semiconductor device according to the present invention is provided with a dam portion around the back side of the substrate on the ^ side on which the semiconductor element is mounted. The provided dam part prevents the resin from flowing between the electrodes on the back surface and forming resin burrs when the substrate is sealed with resin using a mold.
以下、この発明の一実施例としてICカードモジュール
基板を本とに図について説明する。第1図(a) 、
(1)) 、 (C)け封止前の工Cカードモジュール
の、それぞれ上面図C表IFI *半導体素子側)、下
面図(裏側=1!極911)、及び(1−d’における
断面図、第2図は第1図のe−e−における断面の拡大
図で(a)は基板を下金型に入れて、封止樹脂〈よる封
止を行う前、(1))H封止樹rtIVcより封止した
状況を示すう図にお^て、(1)なめしαd、(Ll、
(至)は従来技術の項の第3図ないし第7図で説明した
各部分と同一。DESCRIPTION OF THE PREFERRED EMBODIMENTS An IC card module board will be described below as an embodiment of the present invention with reference to the drawings. Figure 1(a),
(1)), (C) Top view C table IFI * semiconductor element side), bottom view (back side = 1! pole 911), and cross section at (1-d') of the C card module before sealing. Figures 2 and 2 are enlarged cross-sectional views taken along the line e-e in Figure 1. (a) shows the substrate placed in the lower mold and before sealing with sealing resin (1)) H-sealing. In the figure showing the situation sealed from the sealing tree rtIVc, (1) tanning αd, (Ll,
(to) are the same as each portion explained in FIGS. 3 to 7 in the prior art section.
又は相当部分である。また、αati基板(至)の裏面
に設けたダムの部分である。Or a considerable portion. It is also a dam part provided on the back surface of the αati substrate (towards).
この実施例において、基板(2)の裏面周囲に設けたダ
ムの部分αeVi外部電FIA(5)と同じ材質であみ
。In this embodiment, the dam part provided around the back surface of the substrate (2) is made of the same material as the αeVi external electric FIA (5).
以下、この発明の作用を図を用^て説明すb0第1図の
ように1基板(至)周囲の部分にダムの部分αet−設
ffGND(接地)電極とすることによシ%第1図(b
)に示すように、電甑厚さによる基板上の溝がダムの部
分αQで塞がれる。従って基板(至)を金型(9)にお
いて、低圧トランスファー封止した場合。Hereinafter, the operation of this invention will be explained with reference to the drawings. As shown in Fig. 1, a dam part αet-ff is set as a GND (ground) electrode on the periphery of one substrate. Figure (b
), the groove on the substrate due to the thickness of the electric kettle is closed by the dam portion αQ. Therefore, when the substrate (to) is placed in the mold (9) and sealed by low pressure transfer.
第2図(a)のように下金型(9−b)と基板(至)の
間のすき間(至)が塞がれるため、封止後のモジュール
にお^でも第2図(b)のように電極間に樹脂バリIが
できなりり、。As shown in Fig. 2(a), the gap between the lower mold (9-b) and the substrate (to) is closed, so even if the module is sealed, the gap shown in Fig. 2(b) will be closed. A resin burr I is formed between the electrodes as shown in the figure.
なお、上記実施例では、ダムの部分αGに、外部電極(
5)と同じ材質の金属を用すたが、ダムの部分α0の材
質は何でも良−0また、ダム部分αGの表面に可撓性材
料をコートしたようなダムの部分α!にしても良く、そ
の構造についても限定されない。In the above embodiment, an external electrode (
The same metal material as in 5) was used, but the material of the dam part α0 can be any material.In addition, the dam part α whose surface is coated with a flexible material! The structure is not limited either.
また1本実施例では、ダムの部分α0をGND (接地
)電属としたが、ダムの部分αGけGND [iでなく
ても良1/”k3
〔宅間の効果〕
以上のように、この発明によれば、ICカード。In addition, in this embodiment, the dam part α0 is made of GND (ground) electric, but the dam part αG is GND [does not have to be i1/”k3 [Takuma effect] As mentioned above, this According to the invention, an IC card.
ハイブリッドエCなどを製造する際に用する半導体装置
用基板の裏面周囲にダムの部分を設けたので、低圧トラ
ンスファー法による封止が行なえ、装置が安価にでき、
また信頼性の良−製品が得られる効果がある。A dam part is provided around the back side of the substrate for semiconductor devices used when manufacturing Hybrid E-C, etc., so sealing can be performed using the low-pressure transfer method, making the device inexpensive.
Moreover, there is an effect that a product with good reliability can be obtained.
第1図はこの宅間の一実施例による半導体装置用基板の
外形図、第2図は第1図に示した半導体装置用基板を、
金型を用いて低圧トランスファー法により封止するプロ
セス及び封止後の半導体装置の断面を示す図で、第1図
e−θ′における断面の拡大図、第3図は従来のICカ
ードモジュール基板の外形図、第4図は工Cカードモジ
ュールの外形図及びd −a’断面図、第5図は従来の
工Cカードモジュール基板を低圧トランスファー法で作
製する際の問題点を示す図で、第3図((1)、(e)
部の拡大図、第6図及び第7図は第3図に示した従来基
板を低圧トランスファー法を用いて封止する場合の問題
点を示す図であシ、第6図は第3図に示した半導体装置
用基板を金型を用いて低圧トランスファー法によシ封止
するプロセス、及び封止後の半導体装置を示す図、第7
図は第6図の紙面に垂直かつ第3図のg−g’における
断面図である。
図中%fl) Vi基材、〔2)は導体、(3)は半導
体素子。
(4)は金属細線、(5)は外部電甑、(6) Viミ
スルーホール(7)はD/B材、!8)V′i封止樹脂
、(9−b)titT金型、α0はキャビティ、(至)
はすき間、(2)は基板、αQViダムの部分である。
なお2図中、同一符号は同−又は相当部分を示す0FIG. 1 is an outline drawing of a semiconductor device substrate according to one embodiment of this home, and FIG. 2 is a diagram showing the semiconductor device substrate shown in FIG. 1.
These are diagrams showing a process of sealing by a low-pressure transfer method using a mold and a cross section of a semiconductor device after sealing. Fig. 1 is an enlarged view of the cross section at e-θ', and Fig. 3 is a conventional IC card module board. 4 is an outline drawing and a d-a' cross-sectional view of an engineered C card module, and FIG. 5 is a diagram showing problems when manufacturing a conventional engineered C card module board by the low-voltage transfer method. Figure 3 ((1), (e)
6 and 7 are diagrams showing problems when sealing the conventional substrate shown in FIG. 3 using the low-pressure transfer method. FIG. 7 shows a process of sealing the illustrated substrate for a semiconductor device by a low-pressure transfer method using a mold, and a semiconductor device after sealing.
The figure is a sectional view taken along line gg' in FIG. 3 and perpendicular to the plane of the paper in FIG. 6. %fl in the figure) Vi base material, [2] is a conductor, and (3) is a semiconductor element. (4) is a thin metal wire, (5) is an external electric kettle, (6) Vi miss-through hole (7) is a D/B material,! 8) V′i sealing resin, (9-b) titT mold, α0 is cavity, (to)
2 is the gap, and (2) is the substrate and αQVi dam part. In addition, the same symbols in the two figures indicate the same or equivalent parts.
Claims (1)
半導体素子を、ガラスエポキシ材やセラミックを基材と
し、金属鋼や銀−パラジウム焼成導体で回路や導体を形
成した基板上に搭載した半導体装置に用いる導体におい
て、基板の裏面、半導体素子を搭載していない側の、外
部と電気的に接続する外部電極周囲に、外部電極と同じ
材質又は他の材質により、ダム部分を設けたことを特徴
とする半導体装置用基板。Used in semiconductor devices, such as IC cards and hybrid ICs, in which one or more semiconductor elements are mounted on a substrate made of glass epoxy material or ceramic, with circuits and conductors formed of metal steel or fired silver-palladium conductors. The conductor is characterized by having a dam part made of the same material as the external electrode or another material around the external electrode that is electrically connected to the outside on the back side of the substrate, on the side where the semiconductor element is not mounted. Substrate for semiconductor devices.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1779888A JPH01192147A (en) | 1988-01-27 | 1988-01-27 | Substrate for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1779888A JPH01192147A (en) | 1988-01-27 | 1988-01-27 | Substrate for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01192147A true JPH01192147A (en) | 1989-08-02 |
Family
ID=11953731
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1779888A Pending JPH01192147A (en) | 1988-01-27 | 1988-01-27 | Substrate for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01192147A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7544246B2 (en) | 2003-04-08 | 2009-06-09 | Sumitomo Metal Mining Co., Ltd. | Lithium tantalate substrate and method of manufacturing same |
-
1988
- 1988-01-27 JP JP1779888A patent/JPH01192147A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7544246B2 (en) | 2003-04-08 | 2009-06-09 | Sumitomo Metal Mining Co., Ltd. | Lithium tantalate substrate and method of manufacturing same |
US7544248B2 (en) | 2003-04-08 | 2009-06-09 | Sumitomo Metal Mining Co., Ltd. | Lithium tantalate substrate and method of manufacturing same |
US7544247B2 (en) | 2003-04-08 | 2009-06-09 | Sumitomo Metal Mining Co., Ltd. | Lithium tantalate substrate and method of manufacturing same |
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