JPH01187933A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01187933A JPH01187933A JP1288788A JP1288788A JPH01187933A JP H01187933 A JPH01187933 A JP H01187933A JP 1288788 A JP1288788 A JP 1288788A JP 1288788 A JP1288788 A JP 1288788A JP H01187933 A JPH01187933 A JP H01187933A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- oxygen content
- dielectric
- dielectric film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000001301 oxygen Substances 0.000 claims abstract description 18
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 19
- 230000001681 protective effect Effects 0.000 claims 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 11
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、持ニＧａＡ
ｓ ＦＥＴ （Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓ
ｉｓｔｏｒ、 ｆｉｌ界効果トランジスタ）素子におけ
る各電極保護のための誘電体膜の形成方法の改良に係る
ものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and
s FET (Field Effect Trans
The present invention relates to an improvement in a method for forming a dielectric film for protecting each electrode in an (istor, fil field effect transistor) device.
従来例によるＧａＡｓＦＥＴ素子の概要構成を第３図に
示す。FIG. 3 shows a schematic configuration of a conventional GaAsFET device.
この従来例におけるＧａＡｓ ＦＥＴ素子の製造では、
まず、半絶縁性ＧａＡｓ基板（１）面に形成された活性
層（２）上の所定位置に、ソース電極（３）、ドレイン
電極（４）を形成すると共に、エツチングによりリセス
を形成した上で、同様に所定位置にゲート電極（５）を
形成し、その後、これらの各電極（３）〜（５）を外部
からの湿気、異物等から保護するため、Ｓｉ３Ｎ、、Ｓ
ｉＯＮ等の誘電体膜（６）を形成し、かつこの誘電体膜
（６）をバッファド・フッ酸等で選択的にエツチングし
て、前記各電極（３）〜（５）のワイヤボンドのための
窓部（９）を開口させる。In manufacturing the GaAs FET device in this conventional example,
First, a source electrode (3) and a drain electrode (4) are formed at predetermined positions on an active layer (2) formed on a surface of a semi-insulating GaAs substrate (1), and a recess is formed by etching. Similarly, a gate electrode (5) is formed at a predetermined position, and then, in order to protect each electrode (3) to (5) from external moisture, foreign matter, etc., Si3N, S
A dielectric film (6) such as iON is formed, and this dielectric film (6) is selectively etched with buffered hydrofluoric acid or the like for wire bonding of each of the electrodes (3) to (5). window (9) is opened.
この従来例の場合、ＧａＡｓ ＦＥＴ素子の表面への誘
電体膜（６）は通常、プラズマＣＶＤ法を用い、成膜ガ
スをグロー放電中で分解させて形成する。In the case of this conventional example, the dielectric film (6) on the surface of the GaAs FET element is usually formed by using the plasma CVD method and decomposing the film forming gas in a glow discharge.
このように形成される誘電体膜は通常の場合、その膜形
成時における成膜温度、成膜ガス比、成膜圧力等のパラ
メーターを選択することによって、膜質を任意に変化さ
せ得るもので、例えば誘電体膜として用いられるＳｉＯ
Ｎ（シリコンオキシナイトライド）膜の場合には、成膜
に用いるＳｉＨ，（シラン）とＮＨ，（アンモニア）と
Ｈ！０（亜酸化窒素）のうち、Ｎ、Ｏの比率を高くする
と膜中の酸素含有量が多くＧａＡｓ基板に対するストレ
スの小さい誘電体膜が形成できる。またＮ２０の比率を
低くすると膜中の酸素含有量が減少し、ＧａＡｓ基板に
対するストレスは大きくなるが、耐湿性の高い膜が形成
できる。このように成膜ガス中のＮ、Ｏの比率を変化さ
せることにより膜質の異った誘電体膜を形成できる。Normally, the quality of the dielectric film formed in this way can be arbitrarily changed by selecting parameters such as the film formation temperature, film formation gas ratio, and film formation pressure during film formation. For example, SiO used as a dielectric film
In the case of N (silicon oxynitride) film, SiH, (silane) and NH, (ammonia) and H! are used for film formation. When the ratio of N and O in O (nitrous oxide) is increased, a dielectric film with a high oxygen content in the film and less stress on the GaAs substrate can be formed. Furthermore, when the ratio of N20 is lowered, the oxygen content in the film decreases, and stress on the GaAs substrate increases, but a film with high moisture resistance can be formed. By changing the ratio of N and O in the film forming gas in this way, dielectric films with different film qualities can be formed.
しかしながら、前記した従来における誘電体膜の形成方
法においては、成膜ガス中のＮ、Ｏの比率を高くするこ
とにより、ＧａＡｓ基板に対するストレスの小さい膜が
形成できるが、膜中の酸素含有量が増加すると膜が水分
を通し易くなり、膜の耐湿性が低下する。また、誘電体
膜を厚く形成したり、膜の酸素含有量を減少させると耐
湿性は向上するが膜のストレスが大きくなり高周波特性
の劣化や誘電体膜にクラックが発生するなどの問題点が
あった。However, in the conventional dielectric film formation method described above, a film with low stress on the GaAs substrate can be formed by increasing the ratio of N and O in the film formation gas, but the oxygen content in the film is When it increases, the membrane becomes more permeable to moisture, and the moisture resistance of the membrane decreases. In addition, forming a thicker dielectric film or reducing the oxygen content of the film improves moisture resistance, but increases stress on the film, resulting in problems such as deterioration of high frequency characteristics and cracks in the dielectric film. there were.
この発明方法は、従来の製造方法でこのような問題点を
改善するためになされたものでＧａＡｓＦＥＴ素子での
各電極上への誘電体膜の形成において、耐湿性が高（、
ＧａＡｓ基板に対してストレスの小さい良質な誘電体膜
を得て、ＧａＡｓＦＥＴ素子の高周波特性、信頼性を向
上できるようにした、この種の半導体装置の製造方法を
提供することである。This inventive method was developed to improve these problems with conventional manufacturing methods, and is capable of achieving high moisture resistance (,
An object of the present invention is to provide a method for manufacturing a semiconductor device of this type, which can improve the high frequency characteristics and reliability of a GaAsFET element by obtaining a high-quality dielectric film with low stress on a GaAs substrate.
前記目的を達成するために、この発明に係る半導体装置
の製造方法は、ＧａＡｓＦＥＴ素子の製造に際して、各
電極の形成後に同各電極保護のための誘電体膜を形成す
る方法であって、前記各電極上に、酸素含有量の多くス
トレスの小さい第１層目の誘電体膜を形成すると共１ご
、この第１層目の誘電体膜上に、酸素含有量の少ない耐
湿性の高い２層目以降の誘電体膜を少なくともｉ層以上
順次連続的に形成する工程を含むことを特徴とするもの
である。In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention is a method of forming a dielectric film for protecting each electrode after forming each electrode when manufacturing a GaAsFET element, the method comprising: forming a dielectric film for protecting each electrode; A first dielectric film with high oxygen content and low stress is formed on the electrode, and two layers with high moisture resistance and low oxygen content are formed on this first dielectric film. This method is characterized in that it includes a step of sequentially and continuously forming at least i layers of dielectric films after the first one.
この発明においては、ＧａＡｓＦＥＴ素子での各電極上
に、酸素含有量の多いストレスの小さい第１層目の誘電
体膜上に、酸素含有量の少ない耐湿性の高い第２層目以
降の誘電体膜を、少なくとも１層以上順次連続的に形成
するようにしたので、従来の製造方法で発生しやすかっ
た、ＧａＡｓＦＥＴ素子の高周波特性の劣化させること
なしに、その耐湿性を十分に向上させ得る。In this invention, on each electrode of the GaAsFET element, a first dielectric film with a high oxygen content and low stress is coated with a second and subsequent dielectric film with a low oxygen content and high moisture resistance. Since at least one layer of the film is successively formed, the moisture resistance of the GaAsFET element can be sufficiently improved without deteriorating the high frequency characteristics of the GaAsFET element, which tends to occur with conventional manufacturing methods.
以下、この発明に係る半導体装置の製造方法の一実施例
を第１図、第２図において説明する。An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. 1 and 2.
第１図、第２図はこの実施例方法を適用したＧａＡｓＦ
ＥＴ素子での誘電体膜の形成工程を順次示した要部断面
図である。Figures 1 and 2 show GaAsF to which this embodiment method is applied.
FIG. 3 is a cross-sectional view of main parts sequentially showing the steps of forming a dielectric film in an ET element.
すなわち、この実施例方法においてもＧａＡｓＦＥＴ素
子は、前記従来例方法と同様に、第１図に示す通り、半
絶縁性基板（１）の活性層（２）上の所定位置にソース
電極（３）、ドレイン電極（４）を形成すると共に、エ
ツチングによりリセスを形成した上で、同様に所定位置
にゲート電極（５）を形成し、ついでその後、これらの
各電極（３）（４） ｐおよび（５）上に、まずストレ
スが小さく 、ＧａＡｓ基板および電極に影響を与える
ことがない、酸素含有量の小ない膜質の第１層目の誘電
体膜（６）を形成する。この場合に例えば、Ｓｉ風、
ＮＨｓ ＝ ＮｔＯを用いるＳｉＯＮ膜であれば、Ｎ２
０の流量比を高くして形成する。続いてこの第１層目の
誘電体膜（６）上に、Ｎ、Ｏの流量比を幾分か低くして
、第１層目の誘電体膜（６）に対し、ストレスは大きい
が耐湿性の高い第２層目の誘電体膜（７）を連続的に形
成し、さらに引き続きこの第２層目の誘電体膜（７）上
に、Ｎ、０の流量比をさらに低くして、第２層目誘電体
膜（７）に対し耐湿性の高い、第３層目の誘電体膜（８
）を連続的に形成する。そしてその後は、第２図に示す
通り、これらの積層された誘電体膜（６） 、 （７）
および（８）を、ＲＩＥ法などにより選択的にエツチン
グして、前記各電極（３） ｊ （４）および（５）へ
のワイヤボンドのための窓部（９）を開口させるのであ
る。That is, in this embodiment method as well, the GaAsFET element has a source electrode (3) at a predetermined position on the active layer (2) of the semi-insulating substrate (1), as shown in FIG. , a drain electrode (4) is formed, a recess is formed by etching, a gate electrode (5) is similarly formed at a predetermined position, and then each of these electrodes (3) (4) p and ( 5) First, a first layer dielectric film (6) is formed on top, which is low in stress and does not affect the GaAs substrate and electrodes, and has a low oxygen content. In this case, for example, Si wind,
If it is a SiON film using NHs = NtO, N2
It is formed by increasing the flow rate ratio of 0. Next, the flow rate ratio of N and O is slightly lowered on this first layer dielectric film (6) to make the first layer dielectric film (6) moisture resistant, although the stress is large. A second layer dielectric film (7) with high properties is continuously formed, and then on this second layer dielectric film (7), the flow rate ratio of N and 0 is further lowered. The third dielectric film (8) has higher moisture resistance than the second dielectric film (7).
) are formed continuously. After that, as shown in Figure 2, these laminated dielectric films (6), (7)
and (8) are selectively etched by RIE or the like to open windows (9) for wire bonding to each of the electrodes (3), (4) and (5).
つまり、この実施例による誘電体膜の形成方法では、例
えば、５ＩＨ４ｐ Ｉ’１）（３＊ Ｎ２０を用いたＳ
ｉＯＮ膜による、ストレスの小さい、第１層目の誘電体
膜（６）の膜形成条件に対して、そのＮ、Ｏガスの流量
比を漸次段階的に低くするだけの極めて簡単な操作によ
り、耐湿性の高い第２層目、第３層目の誘電体膜（７）
（８）を順次連続的に形成し得るのである。That is, in the method of forming a dielectric film according to this embodiment, for example, S
With respect to the film formation conditions of the first layer dielectric film (6) with low stress using the iON film, the flow rate ratio of N and O gases is gradually lowered step by step. Second and third layer dielectric film with high moisture resistance (7)
(8) can be formed one after another.
そして、このようにして形成された複数層に亘る各誘電
体膜（６） ｊ （７）および（８）の構成では、各電
極（３） ｔ （４）および（５）の上の第１層目の誘
電体膜（６）が酸素含有量が多いストレスの小さい膜で
あるため、ＧａＡｓＦＥＴ素子の高周波特性を劣化させ
ることはなく、また第２層目以降層目の誘電体膜（７）
＃ （８）が酸素含有量の少ない水分を通しにくい膜
であるため同素子の耐湿性を向上させ得る。In the structure of each dielectric film (6) j (7) and (8) formed in this way over multiple layers, the first layer on each electrode (3) t (4) and (5) Since the dielectric film (6) in the second layer is a film with a high oxygen content and low stress, it does not deteriorate the high frequency characteristics of the GaAsFET element, and the dielectric film (7) in the second and subsequent layers
# Since (8) is a film with a low oxygen content and is difficult for moisture to pass through, the moisture resistance of the element can be improved.
なお、前記実施例方法においては、３層に亘って誘電体
膜を形成する場合について述べたが、２層、または４層
以上の誘電体を形成するようにしてもよく、またそれぞ
れの膜形成時のＮ、Ｏの流量比についても、第１層目の
ものに比較して、第２層目以降のものを流量比を低くす
ればよく、同様な作用、効果を奏し得る。In addition, in the above embodiment method, a case was described in which a dielectric film was formed over three layers, but two, four or more layers of dielectric may be formed, and each film formation Regarding the flow rate ratio of N and O at the time, the flow rate ratio of the second and subsequent layers may be made lower than that of the first layer, and the same operation and effect can be achieved.
以上のように、この発明方法によれば、ＧａＡｓＦＥＴ
素子の製造に際し、各電極の形成後、同各電極保護のた
めの誘電体膜を形成する方法において、これらの各電極
上に、ＣａＡＳ基板に対しストレスの小さい第１層目の
誘電体膜を形成する°と共に、この第１層目の誘電体膜
上に、酸素含有量が少ない、耐湿性の高い第２層目以降
の誘電体膜を少な（とも１層以上連続的に順次形成する
ようにしたので、従来の製造方法で生じやすかった、Ｃ
ａＡｓ素子の高周波特性、耐圧特性を劣化させることな
しに、その耐湿性を十分に向上させ得る。しかも、これ
らの複数層からなる誘電体膜は、順次連続的に形成する
ことができるため、その製造時に新たな工程を付加する
必要がな（、容易に実施できるなど優れた特徴を有する
ものである。As described above, according to the method of this invention, GaAsFET
When manufacturing the device, after each electrode is formed, in the method of forming a dielectric film to protect each electrode, a first layer of dielectric film that has less stress on the CaAS substrate is formed on each of these electrodes. At the same time, on this first dielectric film, the second and subsequent dielectric films with low oxygen content and high moisture resistance are formed in small quantities (one or more layers are successively formed). Because of this, C
The moisture resistance of the aAs element can be sufficiently improved without deteriorating its high frequency characteristics and breakdown voltage characteristics. Moreover, since these dielectric films consisting of multiple layers can be formed one after another, there is no need to add new processes during their manufacturing (they have excellent features such as being easy to implement). be.
第１図および第２図はこの発明に係る半導体装置の製造
方法の一実施例を適用したＧａＡｓ Ｆ Ｅ Ｔ素子で
の誘電体膜の形成工程を順次示した要部断面図、また第
３図は従来例方法による同上ＧａＡｓＦＥＴ素子の構成
を示す要部断面図である。
（１）は半絶縁性ＧａＡｓ基板、（２）は活性層、（３
）はソース電極、（４）はドレイン電極、（５）はゲー
ト電極、（６）〜（８）は第１〜３層目の誘電体膜、（
９）はワイヤボンドのための窓部。
なお、図中同一符号は同−又は相当部分を示す。1 and 2 are cross-sectional views of essential parts sequentially showing the steps of forming a dielectric film in a GaAs FET element to which an embodiment of the method for manufacturing a semiconductor device according to the present invention is applied, and FIG. FIG. 2 is a sectional view of a main part showing the structure of the GaAsFET device according to the conventional method. (1) is a semi-insulating GaAs substrate, (2) is an active layer, (3
) is the source electrode, (4) is the drain electrode, (5) is the gate electrode, (6) to (8) are the first to third dielectric films, (
9) is a window for wire bonding. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
に、同各電極保護のための誘電体を形成する方法であつ
て、前記電極上に酸素含有量が多くＧａＡｓ基板に対す
るストレスの小さそＳｉＯＮ膜を第１層目の誘電体保護
膜として形成すると共に、この第１層目の誘電体膜上に
、第１層目に比べ酸素含有量が少ない、耐湿性の高いＳ
ｉＯＮ膜を、第２層目以降の誘電体保護膜として、少な
くとも１層以上順次連続的に形成する工程を含むことを
特徴とする半導体装置の製造方法。In manufacturing a GaAsFET device, after each electrode is formed, a dielectric is formed to protect each electrode. In addition to forming the dielectric protective film for the second layer, a highly moisture-resistant S film with a lower oxygen content than the first layer is formed on the first dielectric film.
A method for manufacturing a semiconductor device, comprising the step of sequentially and sequentially forming at least one iON film as a second and subsequent dielectric protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1288788A JPH01187933A (en) | 1988-01-22 | 1988-01-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1288788A JPH01187933A (en) | 1988-01-22 | 1988-01-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01187933A true JPH01187933A (en) | 1989-07-27 |
Family
ID=11817915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1288788A Pending JPH01187933A (en) | 1988-01-22 | 1988-01-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01187933A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0827199A2 (en) * | 1996-09-02 | 1998-03-04 | Murata Manufacturing Co., Ltd. | A semiconductor device with a passivation film |
| JP2012169545A (en) * | 2011-02-16 | 2012-09-06 | Fujitsu Ltd | Semiconductor device, power supply device, amplifier and semiconductor manufacturing method |
-
1988
- 1988-01-22 JP JP1288788A patent/JPH01187933A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0827199A2 (en) * | 1996-09-02 | 1998-03-04 | Murata Manufacturing Co., Ltd. | A semiconductor device with a passivation film |
| EP0827199A3 (en) * | 1996-09-02 | 2005-10-19 | Murata Manufacturing Co., Ltd. | A semiconductor device with a passivation film |
| JP2012169545A (en) * | 2011-02-16 | 2012-09-06 | Fujitsu Ltd | Semiconductor device, power supply device, amplifier and semiconductor manufacturing method |
| US9324808B2 (en) | 2011-02-16 | 2016-04-26 | Fujitsu Limited | Semiconductor device, power-supply unit, amplifier and method of manufacturing semiconductor device |
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