JPH01187854A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate a leakage malfunction of the collector of a high breakdown strength transistor, to improve probe yield and to obtain a countermeasure of damaging a high breakdown strength capacity by performing different steps of diffusing one conductivity type impurity in high concentration to lead a collector and diffusing the same conductivity type impurity in a semiconductor substrate for forming a MIS capacity by altering the concentrations. CONSTITUTION:I is a high breakdown strength bipolar n-p-n transistor forming section, II is a high breakdown strength MOS capacity forming section, and III is a C-MOSFET forming section. The n<+> type collector 12 of the transistor reduces a crystal defect (dislocation) generated from the collector by a low concentration impurity diffusion 9, the leakage malfunction of the transistor or the like is decreased, and transistor characteristics and probe yield (approx. 10%) are improved. On the other hand, the impurity layer 8 of the MOS capacity is gate-oxidized for forming a MOS gate oxide film by high concentration impurity diffusion, and necessary thickness (2500-3000Angstrom ) of the oxide film 14 of the capacity is obtained.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, particularly a method of manufacturing a high voltage bipolar C-MO8 semiconductor device, in which impurities are removed in a diffusion process for forming a transistor and an MO8 capacitor. Concerning concentration control technology.

[Conventional technology]

In the high voltage bipolar C-MOS process, np
n) Because the transistor has high output specifications, n+ type buried layer embedded in the semiconductor substrate in advance
It is common practice to perform high-concentration phosphorus diffusion for the type collector extraction layer at the same time as phosphorus diffusion to the n-type region of other elements. For example, ■Ichigo Materials 1979 published by the Industrial Research Council
It is described in August 2008, pages 44-50 that in a Bf-CMOS device, the collector and emitter n+ diffusion and the source/drain n diffusion of an n-channel MO8 are performed simultaneously with the collector extraction diffusion.

Furthermore, the same group in bipolar C-MO8 IC,
When forming an MO8 capacitor on a plate, the applicant considers n
pn) At the same time as the transistor collector extraction phosphorus diffusion, a high-destruction layer is formed by phosphorus diffusion into the semiconductor part of the high-voltage MO8 converter part.

[Problems to be solved by the invention 5] As mentioned above, in the high voltage bipolar C-MOS process, an impurity element (phosphorus) is introduced into the collector part of the transistor.
Since the diffusion and the formation of the impurity diffusion layer of the high breakdown voltage MO5 capacitance section are performed simultaneously, the impurity concentration of each semiconductor region must be the same.

However, in the case of high-voltage MOS capacitors, a high concentration impurity element is pre-existed on the surface of the semiconductor region, an oxide film is grown on this to absorb the impurities, and then this is removed to create a clean state. When the impurity concentration in the semiconductor region is low, the growth rate of the oxide film in the capacitor region is slow and the necessary oxide film cannot be obtained. On the other hand, when the impurity concentration is too high, crystal (St') defects occur on the surface of the semiconductor region in the collector part of the transistor.
This causes leakage defects in transistors, etc. In particular, in high-voltage transistors, impurity diffusion is deep into a thick epitaxial layer, resulting in a long diffusion period, which tends to promote crystal defects.

The present invention has been made to overcome the above-mentioned problems, and its purpose is to provide a high-voltage bipolar C-M OS.
The object of the present invention is to improve the breakdown voltage and yield of transistors and at the same time secure a high breakdown voltage MO8 capacity.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means to solve the problem]

A brief summary of the most important aspects of the invention disclosed in this application is as follows.

That is, in the process of forming a high breakdown voltage transistor and a high breakdown voltage MO8 capacitor on the surface of one semiconductor substrate, phosphorus diffusion for extracting the collector of the transistor and the above M
Phosphorus diffusion into the semiconductor region for forming an O8 capacitor is performed in a separate process with different concentrations.

[Effect]

According to the above-mentioned means, by diffusing the unfavorable initial concentration for semiconductor heads of different functions by changing them, it is possible to obtain a diffusion layer suitable for the functions of those regions, thereby achieving the above object.

〔Example〕

FIG. 5 shows an embodiment of the present invention, and is a schematic process chart covering all steps of a high voltage bipolar C-MOS process. The steps will be explained below in order.

(a) Perform n embedding diffusion on the surface of the P-type S1 substrate.

(bJ Perform n-type epitaxial growth.

(c) Perform P-type diffusion for element isolation.

(d) P-'' well diffusion of n-channel MO8.

(e) Phosphorus diffusion into the capacitor.

FIGS. 1 to 4 are cross-sectional views of the above-mentioned steps in a portion where a power npn transistor and a high voltage MO8 capacitor are formed.

In the same figure, ■ is a high voltage bibor 2npn) transistor forming part, ■ is a high voltage MO8 capacitor forming part, and ■ is a C-MO
This is an 8FET forming section.

1 is a pmst substrate, 2 is an n+ buried layer, 3 is an epitaxial layer 814.4 is an element isolation P layer, 5 is a P-type well, and 6 is a surface oxide film.

As shown in FIG. 1, a first phosphorus deposit or ion implantation (5×10
"cm3)" (diffusion may be performed subsequently).

(f) Form a bipolar element using a photoresist pattern (not showing flN) A part of the bulge in (I) is opened as shown in FIG. 2 to take out the collector n Low concentration diffusion layer 9
Perform m2 removal or ion implantation <2X10'' (M713) for formation, followed by diffusion.

<g) Referring to the iA3 figure km, the base 2 layer of the npn transistor formation region I of the bipolar element, and the P of the MO8 region ■
Boron, ion implantation and diffusion for source drain P layer 11 of channel MO8FET, then emitter N layer 12 of npn transistor, n channel MO8F
Perform arsenic or phosphorous implant diffusion for the source/drain n-layer 13 of the ET.

(h) Refer to Figure 4 to see if the MOSFET game
The surface of the gate portion is etched to form a gate film, thereby forming an insulating film 14 of the MO8 and an insulating film 15 of the MOSFET.

Thereafter, contact photoetching is performed, and after i-evaporation and patterning, gate electrodes 15 and 16 and All-metal other electrodes (not shown) in ohmic contact with each semiconductor region are formed on the insulating film.

The effects obtained from the above examples are as follows.

+11 The n+ collector part of a bipolar transistor is reduced in crystal defects (dislocations) generated from the collector part due to low impurity impurities, reducing leakage defects in transistors, etc., improving transistor characteristics and globe yield (approximately 10
%).

+21 On the other hand, due to the high concentration impurity diffusion in the impurity layer of the high voltage MO3 capacitor part, the oxide film of the high voltage MO8 capacitor part is grown to the required thickness (2500 to 3000X) at the same time as the gate oxidation treatment for forming the MOS gate oxide film. can be secured.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof.

For example, the high concentration impurity diffusion of the MO8 capacitor portion may be divided into two times, and one of the times may be used in combination with the collector diffusion of the bipolar transistor.

The present invention can also be applied to other semiconductor devices that require concentration selection by changing the degree of impurity in the same diffusion.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, it is possible to eliminate leakage defects in the collector portion of the high voltage transistor, improve the yield of probes, and take measures against destruction of the high voltage capacitor portion.

In this example, it was applied to a bipolar C-MOS using an aluminum (AJ) gate, but
A similar effect can be obtained even when applied to a bipolar C-MO8 using a ySi) gate.

[Brief explanation of the drawing]

FIGS. 1 to 4 are bi-bodies showing a simple embodiment of the present invention.
) is a partial process sectional view of a C-MOS semiconductor device. FIG. 5 is an overall process chart of the bipolar C-MOS process according to the present invention. DESCRIPTION OF SYMBOLS 1... P type S1 substrate 5.3... N type epitaxial layer, 5... P well, 6... Oxide film, 7... Mask, 8... High concentration n+ diffusion layer, 9 ...Low concentration n+ diffusion layer (collector extraction part) °・7# Agent Patent attorney Katsuo Ogawa ゛ 5:・“′Figure 5

Claims (1)

[Claims] 1. High breakdown voltage transistor and MI on the surface of one semiconductor substrate
A method for manufacturing a semiconductor device forming an S capacitor, the method comprising: high concentration diffusion of one conductivity type impurity for extracting the collector of the transistor; and diffusion of the same conductivity type impurity concentration into the semiconductor surface for forming the MIS capacitor. A method for manufacturing a semiconductor device, characterized in that the manufacturing method is performed by changing the concentration in a separate process. 2. In the method for manufacturing a semiconductor device according to claim 1, the impurity diffusion concentration into the semiconductor surface for forming the MIS capacitor is higher than the impurity diffusion concentration for the transistor.