JPS63166257A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of steps by constructing a bi-polar transistor using the source region, drain region and well contact region of an MOS transistor formed in the well region respectively as an emitter region, collector region and base region, thereby maintaining the gate electrode in a predetermined bias relative to the opposite conductivity type well. CONSTITUTION:Into a region on a substrate in which transistors 11, 12, 14 are to be formed, phosphorus is introduced to form a region 2. Then boron is introduced into a region in the region 2 and a region in which a transistor 13 is to be formed, forming a region 3. An oxide film 4 is formed between the region 2 and the P-type well region 3, insulating and isolating the respective ones. And after forming polysilicon 5, arsenic is introduced to form an N-type source.drain region 15 and an N-type well contact region 16, and these are formed as an emitter region 19, a collector region 20 and a base region 21. Similarly, boron is introduced to form a P-type source.drain region 17 and a P-type well contact region 18, and these are formed as an emitter region 22, a collector region 23 and a base region 24. With this, coexistence with a bi-polar transistor is enabled without increasing the manufacturing steps of C-MOS elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to bipolar devices and C-
The present invention relates to a semiconductor device in which MOS elements are formed on the same substrate.

[Conventional technology]

Conventionally, when bipolar elements and C-MOS elements are mixed on the same substrate, a structure shown in FIG. 5, for example, has been adopted. In this example, an N-type buried region 5 is formed on a P-type semiconductor substrate 51.
2 and a P-type buried region 53 are formed, and an N-type epitaxial layer 54 is grown on the P-type semiconductor substrate 51, and a P-type impurity region 55 is formed in this epitaxial layer for element isolation.
At the same time, a bipolar element 56, and a C-MOS element 59 consisting of an N-channel MOS transistor 57 and a P-channel MOS transistor 58 were formed.

[Problem that the invention seeks to solve]

When the above-mentioned bipolar element and C-MOS element are mixed on the same substrate, the N-type buried region 52. is used to form the bipolar element. A P-type buried region 53 and an N-type epitaxial layer 54 are also required, as well as a P-type impurity region 55.
Compared to forming only a C-MOS element, the number of steps increases and the structure becomes more complex, such as the need for a P-type impurity region to form the base region of the PN transistor.
There is a problem in that the diffusion yield is reduced.

That is, in the conventional process, the process of forming each region, which is a process specific to a bipolar element, cannot be shared with the process of forming a C-Mos element, and a process specific to a bipolar element is required. The number will increase.

Furthermore, in the step of forming only the C-MOS element, N
It is conceivable to use the channel MOS transistor as a lateral N P N transistor and the P channel MOS transistor as a lateral PNP l-transistor, but in this configuration, simply because of the surface recombination between the silicon and the gate oxide film interface, the NPN transistor There is a problem in that the collector current hF decreases in the low current region.

The present invention does not increase the manufacturing process of C-MOS elements,
Also, h for the collector current of a bipolar transistor
F! It is an object of the present invention to provide a semiconductor device that can be mixed with a C-MOS element without deteriorating its characteristics.

[Failure to solve the problem]

In the semiconductor device of the present invention, a reverse conductivity type well is formed in a part of a -4 conductivity type well region formed in a semiconductor substrate, and a source region, a drain region, and a well of a MOS transistor formed in this reverse conductivity type well are provided. A bipolar transistor is constructed with contact regions as an emitter region, a collector region, and a base region, respectively, and the gate electrode of the MOS transistor is maintained at a predetermined bias with respect to the well of the opposite conductivity type.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

(First Embodiment) FIG. 1 is a cross-sectional view of a first embodiment of the present invention, and illustrations of the glabellar membrane, metallized layers such as contacts, etc. are omitted here.

In FIG. 1, 1 phosphorus is applied to a region on a P-type semiconductor substrate 1 where an NPN transistor 11, a PNP I-run raster 12, and a P-channel MOS transistor 14 are to be formed.
．． Ions were implanted at a concentration of 0x10"cm-" and
N-type well region 2 is formed by heat treatment at 0° C. for several hours.

Next, a region in the N-well region 2 forming the NPN transistor 11 and an N-channel MO3I-transistor 13 are shown.
1. Place poron in the area where it will be formed. P-type well region 3 is formed by ion implantation at a concentration of OX10I3cm-'' and heat treatment at 1200° C. for several hours.

An oxide film 4 having a thickness of 1 μm is formed at the boundaries of these N-type well regions 2 and P-type well regions 3 and in regions other than the element regions to isolate them from each other.

After forming polysilicon 5 as a gate electrode using an existing process, arsenic was added at 5.0x10+5cm-2.
N-type source/drain regions 15 are formed by ion implantation at a concentration of
and an N-type well contact region 16, which is
Emitter region 19 of PN transistor 11. Collector region 20 and base region 21 of PNP transistor 12
form as.

Similarly, boron is ion-implanted at a concentration of 5.0 x 10"cm-" to form a P-type source/drain region 17 and a P-type well contact region 18, which are then connected to the emitter region 22 of the PNP transistor 12. Collector 23 and NPN
It is formed as the base region 24 of the transistor 11.

As a result, the bipolar elements of the PNP transistor 11 and the NPN transistor 12, the N channel MOS transistor 13 and the P channel MOS transistor 14
A C-MOS device consisting of the following can be formed on the same substrate using the manufacturing process of the C-MOS device as is, and an increase in the manufacturing process can be prevented.

Further, by holding the N-well contact region at the highest potential in the circuit configuration, for example, the power supply voltage, the N P N transistor 11 is isolated from other elements by P-N, and electrically isolated by VA.

Further, the gate polysilicon 5 formed in the NPN transistor 11 is held at a negative potential 1, for example, 0.2 V more negative potential than the P-type well region 3.

Similarly, the gate polysilicon 5 formed in the PNP transistor 12 is held at a positive potential, for example, 0.1 V more positive than the N well region 2.

Note that the voltage to be maintained is optimized depending on the junction depth of the source region and drain region and the surface concentration of the N well region and the P well region.

FIGS. 2(a) and 2(b) are diagrams showing a part of FIG. 1 together with its planar pattern;
has a junction depth of 7 μm, and a P-type well 3 has a connection depth of 3 μm. An N-channel MOS transistor 13 and an NPN bipolar transistor 11 are formed here. Further, after forming a glabellar insulating film 6 such as PSG, a base electrode 7. Emitter electrode 8 and collector electrode 9
are formed so as to double as source/drain electrodes.

In such a configuration, for example, as described above, the width of the gate polysilicon 5 of the N-channel MOS transistor 13 is set to 1.6 μm, and then the gate polysilicon 5 is set to a potential 0.2 V more negative than that of the P-type well region 3, that is, the base region. FIG. 3 shows the voltage dependence of the hrt Ic characteristics when held.

Due to the bias applied to this gate polysilicon 5,
Surface recombination of base current can be suppressed, and hr! due to changes in collector current! The dependence can be improved from 40% to 90% compared to when gate polysilicon 5 is not biased.

Similarly, in a PNP transistor formed in the N-type well region 2, the gate polysilicon 5 is 0.0. By keeping the IV positive potential, the h1 dependence due to changes in collector current can be reduced from 20% to 6% compared to when the gate polysilicon is unbiased.
It can be improved to 0%.

(Second example) FIG. 4 is a sectional view showing a second embodiment of the present invention.

In this embodiment, a PNP transistor 42 and an NPN transistor 1 on an N-type semiconductor substrate 31 and an N-channel MO
1.0% boron is added to the region where the S transistor 43 is to be formed.
Ion implantation was performed at a concentration of 1200
A P-type well region 33 is formed by heat treatment at .degree. C. for several hours.

Similarly, PNP transistor 4 in P-type well region 33
2 and the region forming P channel MOS transistor 4
Phosphorus is ion-implanted at a concentration of 1.0.times.10"cm@-" into the region where 4 is to be formed, and an N-type well region 32 is formed by heat treatment at 1200.degree. C. for several hours.

Thereafter, an oxide film 34 and a gate polysilicon 35 are formed by the same steps as in the first embodiment 1, and an N-type source and gate polysilicon 35 are formed.
Drain region 36. An N-type well contact region 37, a P-type source/drain region 33, and a P-type well contact region 39 are formed, and these are configured as an emitter region, a collector region, and a base region, respectively. C-MO3 consisting of a bipolar element, an N-channel MOS transistor 43, and a P-channel MOS transistor 44
The elements can be formed on the same substrate.

In addition, the gate polysilicon 35 formed in the NPN transistor 41 is set to a negative potential, and the PNP transistor 4
It is also the same as the first embodiment that a positive potential is maintained in the gate polysilicon 35 formed in the second embodiment.

It's the same.

Similarly to the first embodiment, this second embodiment also allows a significant improvement in the hFE characteristics with respect to the collector current without increasing the number of manufacturing steps.

〔Effect of the invention〕

As explained above, the present invention provides a source region of a MOS transistor formed in a well region provided in a semiconductor substrate;
Since a bipolar transistor is configured with the drain region and well contact region as the emitter region, collector region, and base region, respectively, and the gate electrode of the MOS transistor is maintained at a predetermined bias with respect to the opposite conductivity type well, C- Bipolar transistors can be manufactured using the manufacturing process of MO3 elements without increasing the number of steps, and the dependence of hFE on changes in collector current in this bipolar transistor can be significantly reduced compared to when there is no bias on the gate electrode. It becomes possible to improve.

[Brief explanation of the drawing]

FIG. 1 is a vertical sectional view of the first embodiment of the present invention, FIG. 2(a)
is a plan layout diagram of a part of the completed state, the second
Figure (b) is a cross-sectional view along the AA line, and Figure 3 is the hFE.
FIG. 4 is a vertical cross-sectional view of the second embodiment of the present invention, and FIG. 5 is a vertical cross-sectional view of the conventional structure. ■... type semiconductor substrate, 2... N type well region, 3...
... P-type well region, 4... Oxide film, 5... Gate polysilicon, 6... Interlayer box 11 film, 7... Base electrode, 8... Emitter electrode, 9... Collector electrode,
11...NPN transistor, 12...PNP
l-transistor, 13... N-channel seven-channel MOS transistor, 14... P-channel MOS transistor, 15
...N type source/drain region, 16...N type contact region, 17...P type source/drain region, 1
8... P type contact region, 19... N type emitter region, 20... N type collector region, 21... N type base region, 22... P type emitter region, 23... P
Type collector area, 24...P type base area, 31...
・N-type semiconductor substrate, 32...N-type well region, 33.
...P type well region, 34...Oxide film, 35...Gate polysilicon, 36...N type source/drain region, 37...N type contact region, 38...P type source/ drain region, 39...P-type contact region,
41...NPN transistor, 42...PNP transistor, 43...N channel MOS transistor, 44...P channel MO3I-transistor 51...
・N-type semiconductor substrate, 52...N-type buried region, 53...
・P type buried region, 54...N type epitaxial growth layer, 55...P type impurity region, 56...bipolar element, 57...N channel MOS transistor, 5th day・
...P channel MOS transistor, 59...C-M
O3 element. Agent Patent Attorney Akio Suzuki 1st (), 2nd
Figure IGFAI Figure 5.

Claims (2)

[Claims] (1) In a semiconductor device in which a bipolar element and a C-MOS element are formed on the same semiconductor substrate, an opposite conductivity type well is formed in a part of one conductivity type well region formed in the semiconductor substrate, and the opposite conductivity type well is A bipolar transistor is constructed by using the source region, drain region, and well contact region of the MOS transistor formed in the type well as the emitter region, collector region, and base region, respectively, and the gate electrode of the MOS transistor is connected to the opposite conductivity type well. 1. A semiconductor device characterized in that the semiconductor device is maintained at a predetermined bias. (2) An N-type well region is formed in a P-type semiconductor substrate, and a P-type well region is formed in a part of the P-type well region, and an N-channel MOS transistor is configured in this P-type well region.
It is configured as a PN bipolar transistor, and the N
2. The semiconductor device according to claim 1, wherein the gate electrode of the channel MOS transistor is of P type and is held biased at a more negative potential than the well region.