JPH01185951A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a yield and the reliability by a method wherein a silica- coated film is used as an interlayer insulating film and a slit is formed in a wiring part on the interlayer insulating film so that a residual component in the silica-coated film can be easily diffused to the outside. CONSTITUTION:In a semiconductor device having two or more layers of wiring layers 103, 106, an interlayer insulating film used to insulate the individual wiring layers 103, 106 from each other is composed of a single layer or a multilayer having at least a silica-coated film 105; in the wiring part 106 formed on the interlayer insulating film, slits 108 are formed in a region where the wiring part does not overlap with the wiring parts 103 formed under the interlayer insulating film. By this setup, a residual component in the silica-coated film 105 is diffused upward through the slits 108 even during a heat treatment operation at the formation of a passivating film 107 and during an operation of the semiconductor device and is hardly diffused in the direction of a silicon substrate 101 ; a yield and the reliability are enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interlayer insulating film structure and a wiring supplement in a semiconductor device having two or more wiring layers.

[Conventional technology]

As semiconductor devices become more highly integrated and faster, there is an increasing demand for multi-layered wiring, but in order to achieve this, fEtI! Not only IB processing technology but also planarization technology is becoming very important.

Among the many planarization techniques, one that is considered promising is the use of a silica coating film (hereinafter abbreviated as SOG film). In other words, a solution of silanol, etc. dissolved in a certain type of organic solvent is spin-coated onto a semiconductor substrate, and then heated to volatilize the organic solvent and at the same time cause the silanol to undergo condensation polymerization to form a silicon oxide film. It is.

Figures 2(a) and 2(b) show a plan view and a cross-sectional view of the case where the interlayer insulating film of a two-layer wiring is planarized using this technique.
), that is, a silicon oxide film 204 is formed as a 0th order interlayer insulating film on which a first layer 1203 is formed on a silicon oxide film 202 on a silicon substrate 201, and a SOG film is further formed on it. A film 205 is formed. At this time, the SOG film 205 is formed thicker between the first layer wirings 203 than on the first layer wirings 203, and is planarized. On top of this, a second layer wiring 206 is formed with a wide width that covers the three first layer wiring 203.
is formed and finally protected with a passivation film 207.

[Problem to be solved by the invention]

However, in the above-mentioned conventional technology, the thickness (5OGWA 205) between the first layer wiring 203 becomes dull, and in the subsequent heat treatment process, high temperature and long time treatment cannot be performed in consideration of the adverse effect on the element characteristics. It is difficult to completely remove organic solvents, moisture, etc., and furthermore, since the second layer wiring 206 completely covers the organic solvents, moisture, etc., these remaining organic solvents, moisture, etc. may be sealed inside the semiconductor device. If the particles remain as they are, they may diffuse toward the silicon substrate 201 during subsequent thermal processes or during operation of the semiconductor device, which may have an adverse effect on yield, reliability, and the like.

[Means to solve the problem]

In the semiconductor device of the present invention, in a semiconductor device having two or more wiring layers, an interlayer insulating film that insulates each wiring layer from each other is composed of a jet layer or a multilayer having at least a silica coating film, and The wiring to be formed is characterized in that a slit is provided in a region that does not overlap with the wiring formed under the interlayer insulating film.

[Real noodles example]

FIG. 1 is a plan view (a) and a main cross-sectional view (b) showing the present invention as an example of a semiconductor device having two-layer wiring.Hereinafter, the present invention will be explained in detail step by step.

A first layer wiring 103 is formed on a silicon oxide film 102 on a silicon substrate 101 with a film thickness of 0.8 μm. Aluminum alloy is used as the wiring material. Next, as an insulating film between the eyebrows, a silicon oxide film 104 of 0.5 μm is grown by vapor phase epitaxy, and then an SOG film 105 is spin-coated. It is formed by

At this time, the film thickness of the SOG film 105 is
031, the thickness is about 0.05 μm, and the distance between the first layer wirings is about 0.3 μm, which is flattened. After this, heat treatment is performed for the purpose of polycondensation of silanol in the SOG film 105, volatilization removal of organic solvents, etc., and densification of the film quality. Considering that the material is an aluminum alloy, heat treatment is only performed at 400° C. for 20 minutes. After heat treatment at 400℃ for about 20 minutes, SQG film 10
It is impossible to completely remove organic solvents, moisture, etc. in 5, and these remain in the SOG film 105. In particular,
These residual amounts are particularly large between interconnects in the first layer where the SOG film is thick.

Next, a second layer wiring 106 is formed on this SOG film 105. The material of the second layer wiring is an aluminum alloy, and the film thickness is 1 μm. Further, at this time, the slit 108 is provided in the second layer wiring in a region that does not overlap with the first layer wiring 103, that is, in a region where the first layer wiring 103 does not exist. The slit 108 is
It is provided in almost the entire area of the second layer wiring 106 that does not overlap with the first layer wiring 103. By providing this slit 108, residual components in the SOG film 105 are diffused upward through the slit 108 during heat treatment during the formation of the passivation film 107, during operation of the semiconductor device, and so on. It hardly diffuses in the 101 direction and has no adverse effect on the device.

〔Effect of the invention〕

As described above, according to the present invention, in a semiconductor device having two or more layers of wiring, planarization is achieved by using an SOG film as an interlayer insulating film, and at the same time, slits are provided in the wiring on the interlayer insulating film. This made it possible to easily diffuse the residual components in the 5ocs to the outside, suppress diffusion toward the silicon substrate, prevent adverse effects on device characteristics, and improve yield and reliability.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view (a) and a main sectional view (b) showing a semiconductor device according to an embodiment of the present invention. FIGS. 2(a) and 2(b) are a plan view (a) and a main sectional view (b) showing a conventional semiconductor device. 101.201...Silicon substrate 102.202...Silicon oxide film 103.203...First layer wiring 104.204...Silicon oxide film 105.205...5OG 106.206...・Second layer wiring 107.207...passivation film 108...
... 1st icb above the slit)

Claims (1)

[Claims] In a semiconductor device having two or more wiring layers, an interlayer insulating film that insulates each wiring layer from each other is composed of a single layer or multiple layers having at least a silica coating film, and the wiring formed on the interlayer insulating film includes: A semiconductor device characterized in that a slit is provided in a region that does not overlap with a wiring formed under the interlayer insulating film.