JPH0118430B2 - - Google Patents
Info
- Publication number
- JPH0118430B2 JPH0118430B2 JP58138260A JP13826083A JPH0118430B2 JP H0118430 B2 JPH0118430 B2 JP H0118430B2 JP 58138260 A JP58138260 A JP 58138260A JP 13826083 A JP13826083 A JP 13826083A JP H0118430 B2 JPH0118430 B2 JP H0118430B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- bit
- signal
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 11
- 239000011159 matrix material Substances 0.000 description 1
Landscapes
- Digital Computer Display Output (AREA)
- Memory System (AREA)
- Controls And Circuits For Display Device (AREA)
- Image Input (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58138260A JPS6029786A (ja) | 1983-07-28 | 1983-07-28 | メモリ制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58138260A JPS6029786A (ja) | 1983-07-28 | 1983-07-28 | メモリ制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6029786A JPS6029786A (ja) | 1985-02-15 |
JPH0118430B2 true JPH0118430B2 (ko) | 1989-04-05 |
Family
ID=15217779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58138260A Granted JPS6029786A (ja) | 1983-07-28 | 1983-07-28 | メモリ制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6029786A (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62249283A (ja) * | 1986-04-23 | 1987-10-30 | Casio Comput Co Ltd | 動的メモリ駆動回路 |
-
1983
- 1983-07-28 JP JP58138260A patent/JPS6029786A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6029786A (ja) | 1985-02-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5924111A (en) | Method and system for interleaving data in multiple memory bank partitions | |
EP0492939B1 (en) | Method and apparatus for arranging access of VRAM to provide accelerated writing of vertical lines to an output display | |
JPH0420489B2 (ko) | ||
JPH0375873B2 (ko) | ||
US4845640A (en) | High-speed dual mode graphics memory | |
JP3271151B2 (ja) | デジタルビデオデータの記憶装置 | |
US4737780A (en) | Display control circuit for reading display data from a video RAM constituted by a dynamic RAM, thereby refreshing memory cells of the video RAM | |
JPS61186991A (ja) | メモリシステム | |
JPH0118430B2 (ko) | ||
JPH06167958A (ja) | 記憶装置 | |
JP3078048B2 (ja) | メモリモジュール | |
JPH04237099A (ja) | 画面表示素子 | |
US6275243B1 (en) | Method and apparatus for accelerating the transfer of graphical images | |
JP3741464B2 (ja) | Dramアクセス方法 | |
JP3833366B2 (ja) | 画像データ記憶装置 | |
JP2708841B2 (ja) | ビットマップメモリの書き込み方法 | |
JPS58136093A (ja) | 表示制御装置 | |
JP2846357B2 (ja) | フォントメモリ装置 | |
JPH05113928A (ja) | 画像メモリ装置 | |
JPH0544680B2 (ko) | ||
JPS5981689A (ja) | 表示装置 | |
JP2833902B2 (ja) | ビットマップ表示装置の表示アトリビュート制御回路 | |
JPS5935120B2 (ja) | メモリ装置 | |
JPH05113768A (ja) | フレームメモリ回路 | |
JPH043874B2 (ko) |