JPH01176679A - Mounting method for semiconductor element - Google Patents
Mounting method for semiconductor elementInfo
- Publication number
- JPH01176679A JPH01176679A JP97088A JP97088A JPH01176679A JP H01176679 A JPH01176679 A JP H01176679A JP 97088 A JP97088 A JP 97088A JP 97088 A JP97088 A JP 97088A JP H01176679 A JPH01176679 A JP H01176679A
- Authority
- JP
- Japan
- Prior art keywords
- element chip
- printed board
- semiconductor element
- output terminals
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000000034 method Methods 0.000 title claims description 13
- 239000002184 metal Substances 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 230000020169 heat generation Effects 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Manufacturing Of Electrical Connectors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明はバンブ接続法によって半導体素子またはそれを
搭載した素子チップ(以下素子チップとよぶ)をプリン
ト板に実装する際における半導体素子の実装方法に関し
、
特に半導体素子とプリント板との熱膨張率の差によって
バンブに歪応力が加わった際における接合破壊の防止方
法の開発を目的とし、
前記プリント板側のパッドパターンと素子チップ側の出
力端子の形状が、素子チップの中心から外方に向かって
伸びる放射状線に沿う形の長円形に形成されている。[Detailed Description of the Invention] [Summary] The present invention relates to a method for mounting a semiconductor element or an element chip (hereinafter referred to as an element chip) on which a semiconductor element is mounted on a printed circuit board using a bump bonding method, and particularly relates to The purpose of this study was to develop a method for preventing bond failure when strain stress is applied to bumps due to the difference in thermal expansion coefficient between the semiconductor element and the printed circuit board.The pad pattern on the printed board side and the shape of the output terminal on the element chip side , is formed into an oval shape along a radial line extending outward from the center of the element chip.
本発明は素子チップをプリント板に実装する際に適用さ
れる半導体素子の実装方法に関する。The present invention relates to a semiconductor element mounting method that is applied when mounting an element chip on a printed board.
第2図(alと中)は素子チップの実装方法を説明する
ための要部斜視図と要部側断面図、第3図(alと(b
lは従来の出力端子とパッドパターンの形状を示す要部
平面図である。Figure 2 (al and middle) is a perspective view and side sectional view of the main part for explaining the mounting method of the element chip, and Figure 3 (al and (b)
FIG. 1 is a plan view of main parts showing the shapes of conventional output terminals and pad patterns.
第2図(a)、 (b)および第3図(a)、 (b)
ニ示すように従来の素子チップ1は、マトリクス状に配
置された複数の出力端子2を装備している。また、プリ
ント板20は該出力端子2と対応する位置にパッドパタ
ーン12を装備している。なお、前記金属バンブ11は
、通常は半田メツキ法等の手段を用いて出力端子2.お
よびパッドパターン12上に被着される。 そして、素
子チップ1をプリント板20に実装する際は、プリント
板20のパッドパターン12上に素子チップ1の出力端
子2を位置決めした後、例えばりフローボンディング法
等を用いて前記金属バンブ11を溶融させてボンディン
グを行う。Figure 2 (a), (b) and Figure 3 (a), (b)
As shown in D, the conventional element chip 1 is equipped with a plurality of output terminals 2 arranged in a matrix. Further, the printed board 20 is equipped with a pad pattern 12 at a position corresponding to the output terminal 2. Note that the metal bump 11 is usually attached to the output terminal 2 using a soldering method or the like. and is deposited on the pad pattern 12. When mounting the element chip 1 on the printed board 20, after positioning the output terminals 2 of the element chip 1 on the pad pattern 12 of the printed board 20, the metal bumps 11 are bonded using, for example, a flow bonding method. Melt and bond.
なお、従来の出力端子2とパッドパターン12とは第3
図(alと(b)に示すように、マトリクス状に配置さ
れている。Note that the conventional output terminal 2 and pad pattern 12 are
As shown in Figures (al and b), they are arranged in a matrix.
しかしながら上記従来の出力端子2.およびパッドパタ
ーン12は、第2図、および第3図に示す如く何れも円
形に形成されている。このため、ボンディング時や通電
時の素子発熱で生じた熱歪による応力が出力端子2とパ
ッドパターン12間に加わり接合破壊に到ることがある
。この応力による接合破壊はプリント板20と素子チッ
プ1間の熱膨脹率差によって生じるものであるため、両
者が同一材料で製作されない限りこれを回避することは
不可能とされていた。即ち、従来はこのことが素子チッ
プ1のサイズを大きくできない、即ち集積度を上げられ
ない最大の制約条件となっていたわけである。However, the conventional output terminal 2. The pad patterns 12 are each formed in a circular shape as shown in FIGS. 2 and 3. Therefore, stress due to thermal distortion caused by element heat generation during bonding or energization may be applied between the output terminal 2 and the pad pattern 12, leading to bond breakdown. Since bond failure due to this stress is caused by the difference in coefficient of thermal expansion between the printed board 20 and the element chip 1, it has been considered impossible to avoid this unless both are made of the same material. That is, in the past, this was the biggest constraint that prevented the size of the element chip 1 from being increased, that is, the degree of integration could not be increased.
本発明はこの問題点を解決するためになされたものであ
る。The present invention has been made to solve this problem.
本発明は第1図の実施例図に示すように、プリント板2
0側のパッドパターン12と前記素子チップ1側の出力
端子2の形状が、碁盤目状の格子線上に中心点を有し、
かつ出力端子2の形成中心0から外方に向かって伸びる
放射状線kに沿う形の長円形に形成されている。As shown in the embodiment diagram of FIG.
The shapes of the pad pattern 12 on the 0 side and the output terminal 2 on the element chip 1 side have a center point on a grid line in a checkerboard shape,
The output terminal 2 is formed in an oval shape along a radial line k extending outward from the formation center 0 of the output terminal 2.
出力端子2とパッドパターン12とをこのように配置す
ることにより、ボンディング時や素子発熱時においてプ
リント板20と素子チップ1間に熱膨脹率差が生じた場
合でも、両者を結合する金属バンブ11はその接合力を
応力の方向に有効に作用させ、著しく高い限界をもたら
す。By arranging the output terminal 2 and the pad pattern 12 in this way, even if a difference in coefficient of thermal expansion occurs between the printed circuit board 20 and the element chip 1 during bonding or when the element heats up, the metal bump 11 that connects the two can be The bonding force is effectively applied in the direction of stress, resulting in a significantly higher limit.
以下実施例図に基づいて本発明の詳細な説明する。 EMBODIMENT OF THE INVENTION The present invention will be described in detail below based on embodiment figures.
第1図(alと(′b)は本発明の一実施例を示す素子
チップの模式的平面図と素子チップおよびプリント板上
に形成されるパッドパターンの一形状例を示す要部平面
図であるが、前記第2図、第3図と同一部分には同一符
号を付している。FIG. 1 (al and 'b) is a schematic plan view of an element chip showing an embodiment of the present invention, and a plan view of essential parts showing an example of the shape of a pad pattern formed on the element chip and a printed board. However, the same parts as in FIGS. 2 and 3 are given the same reference numerals.
第1図(a)と申)に示すように、本発明による半導体
素子の実装方法は、素子チップ1の中心Oから外方に向
かう複数の放射状線にの各線上に長円型(幅がWで長さ
がL)の出力端子2が形成された素子チップ1と、前記
出力端子2に対応するバンドパターン12を備えたプリ
ント板20とを互いに対向させてボンディングを行う方
式になっている。As shown in FIG. 1(a), the method for mounting a semiconductor element according to the present invention is to form an elliptical shape (width: The bonding method is such that an element chip 1 on which an output terminal 2 of W and length L) is formed and a printed board 20 provided with a band pattern 12 corresponding to the output terminal 2 are faced to each other and bonded. .
この場合、第1図(a)に示す素子チップ1の中心0と
、これに対応するプリント板20側の中心(図示せず)
とを合致させるべきであることはいうまでもない。In this case, the center 0 of the element chip 1 shown in FIG. 1(a) and the corresponding center on the printed board 20 side (not shown)
It goes without saying that these should match.
素子チップ1をこのようにしてプリント板20に実装す
るようにすれば、その熱膨張率の差に起因する応力に対
して著しく強い構造となり、結合部が破損するような現
象は的確に防止される。If the element chip 1 is mounted on the printed circuit board 20 in this manner, the structure becomes extremely strong against stress caused by the difference in the coefficient of thermal expansion, and phenomena such as damage to the bonded parts can be accurately prevented. Ru.
なお、前記パッドパターン12の幅Wと長さしとは、素
子チップ1のサイズや素子チップ1とプリント板20と
の熱膨脹率差等を勘案して適宜法められる。Note that the width W and length of the pad pattern 12 are determined as appropriate, taking into consideration the size of the element chip 1, the difference in coefficient of thermal expansion between the element chip 1 and the printed board 20, and the like.
以上の説明から明らかなように本発明によれば、素子チ
ップ(半導体素子)とこれを搭載するプリント板間の熱
膨脹率差によって惹起される素子チツブとプリント板と
の破壊事故が防止され、信頼性の高いプリント板実装を
行い得る、といった著しい工業的効果がある。As is clear from the above description, according to the present invention, damage accidents between the element chip and the printed board caused by the difference in coefficient of thermal expansion between the element chip (semiconductor element) and the printed board on which it is mounted can be prevented, and reliability can be improved. This has significant industrial effects, such as the ability to perform printed board mounting with high performance.
第1図(alと(blは本発明の一実施例を示す模式的
平面図、
第2図(a)と(blは素子チップの実装方法を示す要
部斜視図と要部側断面図、
第3図は従来の出力端子とパッドパターンの形状例を示
す模式的要部平面図である。
図中、1は素子チップ、
2は出力端子、
11は金属バンプ、
12はパッドパターン、
20はプリント板、
Lはパッドパターンの長手方向寸法、
Wはパッドパターンの幅寸法、
kはパッドパターンの中心線、
Oは素子チップの中心、
をそれぞれ示す。
(Q)
tl)>
手発明シーだ油側図
第1図
O
↑5チッ7°、友袈7及をt!明11図第2図
彩珀、+I71士力′石り子を八6〜.p−八ダ降那イ
丈゛別11第3図FIGS. 1A and 1B are schematic plan views showing an embodiment of the present invention; FIGS. 2A and 2B are a perspective view of a main part and a side sectional view of a main part showing a method of mounting an element chip; FIG. 3 is a schematic plan view of main parts showing an example of the shape of a conventional output terminal and pad pattern. In the figure, 1 is an element chip, 2 is an output terminal, 11 is a metal bump, 12 is a pad pattern, and 20 is a Printed board, L is the longitudinal dimension of the pad pattern, W is the width dimension of the pad pattern, k is the center line of the pad pattern, and O is the center of the element chip. (Q) tl)> Hand-invented sea oil Side view Figure 1 O ↑5chi 7°, 7° tomojo! Figure 11 Meiji Figure 2 Saikaku, +I71 Shiriki' Ishiriko 86~.p-Yada Renai length 11 Figure 3
Claims (1)
(2)とプリント板(20)のパッドパターン(12)
とを金属バンプ(11)で接合して前記半導体素子また
はそれを搭載した部品(1)の実装を行う半導体素子の
実装方法において、 前記プリント板(20)側のパッドパターン(12)と
前記半導体素子またはそれを搭載した部品(1)側の出
力端子(2)の形状を、碁盤目状の格子線上に中心点を
有し、かつ出力端子(2)の形成中心(o)から外方に
向かって伸びる放射状線(k)に沿う形の長円形に形成
したことを特徴とする半導体素子の実装方法。[Claims] Output terminal (2) of a semiconductor element or a component (1) on which it is mounted and a pad pattern (12) of a printed board (20)
In a method for mounting a semiconductor element, the semiconductor element or a component (1) having the semiconductor element mounted thereon is mounted by bonding the pad pattern (12) on the printed board (20) side with the semiconductor element using metal bumps (11). The shape of the output terminal (2) on the side of the element or the component (1) on which it is mounted is such that the center point is on the grid line of a checkerboard, and the shape extends outward from the formation center (o) of the output terminal (2). A method for mounting a semiconductor element, characterized in that the semiconductor element is formed into an oval shape along a radial line (k) extending toward the direction of the semiconductor element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP97088A JPH01176679A (en) | 1988-01-05 | 1988-01-05 | Mounting method for semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP97088A JPH01176679A (en) | 1988-01-05 | 1988-01-05 | Mounting method for semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01176679A true JPH01176679A (en) | 1989-07-13 |
Family
ID=11488482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP97088A Pending JPH01176679A (en) | 1988-01-05 | 1988-01-05 | Mounting method for semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01176679A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2766653A1 (en) * | 1997-05-21 | 1999-01-29 | Gen Electric | Contact range for electrical connections with flexible support connected to circuit board |
-
1988
- 1988-01-05 JP JP97088A patent/JPH01176679A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2766653A1 (en) * | 1997-05-21 | 1999-01-29 | Gen Electric | Contact range for electrical connections with flexible support connected to circuit board |
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