JPS63289942A - Substrate for packaging semiconductor element - Google Patents
Substrate for packaging semiconductor elementInfo
- Publication number
- JPS63289942A JPS63289942A JP62125422A JP12542287A JPS63289942A JP S63289942 A JPS63289942 A JP S63289942A JP 62125422 A JP62125422 A JP 62125422A JP 12542287 A JP12542287 A JP 12542287A JP S63289942 A JPS63289942 A JP S63289942A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- finger
- substrate
- finger lead
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 title claims abstract description 19
- 238000004806 packaging method and process Methods 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000011347 resin Substances 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 3
- 238000007789 sealing Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000012141 concentrate Substances 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 7
- 235000014676 Phragmites communis Nutrition 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、 半導体素子の実装用基板のフィンガーリー
ドの機械的強度を向上する構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure for improving the mechanical strength of finger leads of a substrate for mounting semiconductor elements.
従来の半導体装置の、実装用基板は、 第２図（ａ）に
示す様にフィンガーリードの形状が先端に近づくに従っ
て幅が狭（なっているか、あるいは、第２図（ｂ）に示
す様にフィンガーリード全体が同一の幅となっており、
その幅は半導体装置の電極の幅、あるいは、電極のピッ
チにより設計されていた。Conventional mounting substrates for semiconductor devices have finger leads that become narrower as they approach the tip, as shown in Figure 2(a), or narrower as shown in Figure 2(b). The entire finger reed has the same width,
The width was designed based on the width of the electrodes of the semiconductor device or the pitch of the electrodes.
しかし、 前述の従来技術ではフィンガーリードが半導
体素子の電極と接合された後において、フィンガーリー
ドに引張などの外力が働いた場合に、 接合部に応力が
集中するためにフィンガーリードが接合部において破断
し易くなる。 さらに、フィンガーリードと接合された
半導体素子を樹脂封止した場合は、樹脂の熱膨張により
前記接合部に引張応力が山く他、フィンガーリードが樹
脂から外部に延出する部分に外力が集中して破断し易く
なる。However, in the conventional technology described above, if an external force such as tension is applied to the finger lead after the finger lead is bonded to the electrode of the semiconductor element, the finger lead may break at the bond because stress is concentrated at the bond. It becomes easier to do. Furthermore, when the semiconductor element bonded to the finger leads is sealed with resin, the thermal expansion of the resin causes tensile stress to pile up at the bonded portion, and external force is concentrated on the part where the finger leads extend from the resin to the outside. It becomes easy to break.
また、フィンガーリードをハーフエツチングすることに
よりバンプを形成した半導体素子の実装用基板において
は、半導体素子の電極と接合されるバンプ部はもちろん
、フィンガーリード他方の段差部にも前記応力が集中し
てフィンガーリードの破断を招くことになる。In addition, in a substrate for mounting a semiconductor element in which bumps are formed by half-etching finger leads, the stress is concentrated not only at the bump part that is bonded to the electrode of the semiconductor element but also at the stepped part of the other finger lead. This will cause the finger reed to break.
そこで、本発明はこのような問題点を解決するもので、
その目的は半導体素子を実装した基板に外力、あるいは
、 封止樹脂の内部応力が働いても基板のフィンガーリ
ードが容易に破断しない半導体素子の実装用基板の構造
を提供することにある。Therefore, the present invention aims to solve these problems.
The purpose is to provide a structure of a substrate for mounting a semiconductor element in which the finger leads of the substrate do not easily break even if external force or internal stress of the sealing resin acts on the substrate on which the semiconductor element is mounted.
本発明の半導体素子の実装用基板は、半導体素子の電極
に対応したフィンガーリードの少なくとも１部が、他の
リード部よりも幅が広い形状としたことを特徴とする。The substrate for mounting a semiconductor element of the present invention is characterized in that at least one part of the finger leads corresponding to the electrodes of the semiconductor element has a shape wider than other lead parts.
半導体素子の電極に対応したバンプをハーフエツチング
により形成した前記フィンガーリードの幅を広くした部
分が、バンプ周辺であることを特徴とする。The finger lead is formed by half-etching a bump corresponding to an electrode of a semiconductor element, and the width of the finger lead is increased around the bump.
前記フィンガーリードの幅を広くした部分が、ハーフエ
ツチングにより段差を生じた部分であることを特徴とす
る。The finger lead is characterized in that the widened portion is a stepped portion formed by half etching.
第１図（ａ）は本発明の実施例における半導体素子の実
装用基板に半導体素子１を実装した時の平面図である。FIG. 1(a) is a plan view when a semiconductor element 1 is mounted on a semiconductor element mounting substrate in an embodiment of the present invention.
（ｂ）図は、（ａ）図のＡ−Ａ′における断面図である
。(b) is a sectional view taken along line AA' in (a).
半導体素子１の電極６に対応して基板に形成されたフィ
ンガーリード群２は、電極に接続されるバンプ８を形成
するためにエツチング処理が施されている。（ｂ）図に
おけるハーフエツチング部４をフィンガーリードの厚み
に対して半分程度エツチングすることによりバンプ３が
形成される。A finger lead group 2 formed on the substrate corresponding to the electrode 6 of the semiconductor element 1 is subjected to an etching process to form a bump 8 connected to the electrode. (b) The bump 3 is formed by etching the half-etched portion 4 shown in the figure to about half the thickness of the finger lead.
この場合、３５μｍ厚の９！Ａ箔を用いてフィンガーリ
ードを形成し、バンプの高さが１５μｍ程度になる様に
エツチングされている。In this case, 9! with a thickness of 35 μm! Finger leads are formed using A foil and etched so that the height of the bumps is approximately 15 μm.
しかし、エツチングによりフィンガーリード厚が半分程
度になると、それに比例してフィンガーリードの機械的
強度も半分程度に低下する欠点を生ずる。また、フィン
ガーリードに外力が働いた場合に、バンプ部３及びハー
フエツチングにより生じた段差部５には応力が集中する
ため、特に破断し易くなる。However, when the thickness of the finger leads is reduced by about half due to etching, the mechanical strength of the finger leads is also reduced by about half in proportion to the thickness. Further, when an external force is applied to the finger leads, stress is concentrated on the bump portion 3 and the stepped portion 5 caused by half etching, making them particularly susceptible to breakage.
そこで、フィンガーリードの機械的強度を向上するため
に、第１図（ａ）に示す様にバンプ部３及び段差部５に
おいて、フィンガーリードの幅を広＜抽成する。フィン
ガーリードの一般部の幅を７０μｍに形成した場合、バ
ンプ部及び段差部の幅の最も広い部分を１２０μｍ程度
に形成する。Therefore, in order to improve the mechanical strength of the finger leads, the width of the finger leads is widened at the bump portion 3 and the stepped portion 5, as shown in FIG. 1(a). When the width of the general portion of the finger lead is 70 μm, the widest portion of the bump portion and the stepped portion is formed to be approximately 120 μm.
幅を広くした部分の形状は円弧を描（様に形成すること
により、有効的にバンプ部及び段差部に集中する応力を
分散して、 低強度でのフィンガーリードの破断を防ぐ
ことができる。By forming the widened part in a circular arc shape, it is possible to effectively disperse the stress concentrated in the bump and step parts and prevent the finger lead from breaking at low strength.
又、このハーフエツチング部４には、 フィンガーリー
ドの裏面に凹部が形成されるが、との凹部が半導体素子
１、の外形７部を逃げるので、ショートの危険性も少な
くな゛る利点も有する。Furthermore, although a recess is formed on the back surface of the finger lead in the half-etched portion 4, since the recess escapes the outer shape 7 of the semiconductor element 1, it also has the advantage of reducing the risk of short-circuiting. .
以上述べたように、本発明によれば基板のフィンガーリ
ードの比較的機械的強度の弱い部分を、フィンガーリー
ド幅を広くすることによって補強するために、外部から
のストレスに強（なり、また、温度変化などによる内部
応力にも強くなり、半導体ＨＨの信頼性が向上する。As described above, according to the present invention, in order to strengthen the relatively weak mechanical strength portion of the finger leads of the substrate by widening the finger lead width, it becomes resistant to external stress. It also becomes resistant to internal stress due to temperature changes, etc., and improves the reliability of the semiconductor HH.
さらに本発明は、ハーフエツチングによりバンプを形成
したフィンガーリードを存する基板には特に有効に作用
し、信頓性向上に効果的である。Further, the present invention is particularly effective for substrates having finger leads with bumps formed by half-etching, and is effective in improving reliability.
第１図（ａ）は、本発明の半導体素子の実装用基板の実
施例を示す平面図。（ｂ）図は（ａ）図のＡ −Ａ−に
おける断面図。
第２図（ａ）、（ｂ）は、各々従来の半導体素子の実装
用基板を示す平面図。
１・・・半導体素子
２・・・フィンガーリード群
３・・・バンプ
５・・・段差部
以 上
出願人 セイコーエプソン株式会社
第１図FIG. 1(a) is a plan view showing an embodiment of a substrate for mounting a semiconductor element of the present invention. The figure (b) is a sectional view taken along A-A- of the figure (a). FIGS. 2(a) and 2(b) are plan views each showing a conventional mounting board for semiconductor elements. 1... Semiconductor element 2... Finger lead group 3... Bump 5... Step portion or above Applicant Seiko Epson Corporation Figure 1
Claims (3)
の少なくとも１部が、他のリード部よりも幅が広い形状
としたことを特徴とする半導体素子の実装用基板。(1) A substrate for mounting a semiconductor element, characterized in that at least one part of the finger leads corresponding to the electrodes of the semiconductor element has a shape wider than other lead parts.
チングにより形成したフィンガーリードの幅を広くした
部分が、バンプ周辺であることを特徴とする特許請求の
範囲第１項記載の半導体素子の実装用基板。(2) For mounting a semiconductor device according to claim 1, wherein the finger lead formed by half-etching a bump corresponding to the electrode of the semiconductor device has a widened portion around the bump. substrate.
ーフエッチングにより段差を生じた部分であることを特
徴とする特許請求の範囲第１項記載の半導体素子の実装
用基板。(3) The substrate for mounting a semiconductor element according to claim 1, wherein the widened portion of the finger lead is a portion where a step is created by half etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62125422A JPS63289942A (en) | 1987-05-22 | 1987-05-22 | Substrate for packaging semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62125422A JPS63289942A (en) | 1987-05-22 | 1987-05-22 | Substrate for packaging semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63289942A true JPS63289942A (en) | 1988-11-28 |
Family
ID=14909709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62125422A Pending JPS63289942A (en) | 1987-05-22 | 1987-05-22 | Substrate for packaging semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63289942A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009238925A (en) * | 2008-03-26 | 2009-10-15 | Hitachi Cable Ltd | Tab tape carrier for semiconductor device, and method of manufacturing the same |
-
1987
- 1987-05-22 JP JP62125422A patent/JPS63289942A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009238925A (en) * | 2008-03-26 | 2009-10-15 | Hitachi Cable Ltd | Tab tape carrier for semiconductor device, and method of manufacturing the same |
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