JPH11354579A - Mounting structure for semiconductor chip - Google Patents

Mounting structure for semiconductor chip

Info

Publication number
JPH11354579A
JPH11354579A JP16068498A JP16068498A JPH11354579A JP H11354579 A JPH11354579 A JP H11354579A JP 16068498 A JP16068498 A JP 16068498A JP 16068498 A JP16068498 A JP 16068498A JP H11354579 A JPH11354579 A JP H11354579A
Authority
JP
Japan
Prior art keywords
semiconductor chip
electrode
substrate
passivation
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP16068498A
Other languages
Japanese (ja)
Inventor
Tomoyuki Kubota
智之 久保田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP16068498A priority Critical patent/JPH11354579A/en
Publication of JPH11354579A publication Critical patent/JPH11354579A/en
Withdrawn legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To perform face down bonding of semiconductor chip without using any bump electrode. SOLUTION: A terminal electrode 2 is disposed on a substrate through a conductive adhesive while facing the electrode pad 4 of a semiconductor chip 3 and the gap is filled with anisotropic conductive adhesive 6. The semiconductor chip 3 is provided with a passivation having an opening at a position corresponding to the electrode pad 4. The terminal electrode 2 on the substrate 1 is smaller than the opening of the passivation and the distance from the electrode pad 4 to the terminal electrode 2 is shorter than the distance from the passivation to the substrate 1. According to the structure, bump electrode can be eliminated without causing defective contact.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップと回
路基板上の端子電極との電気的接続を行う半導体チップ
の実装構造に関し、とくに異方性導電接着剤を用いてフ
ェイスダウンボンディングにより接続を行う半導体チッ
プの実装構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting structure for making an electrical connection between a semiconductor chip and terminal electrodes on a circuit board, and more particularly, to a connection structure by face-down bonding using an anisotropic conductive adhesive. The present invention relates to a mounting structure of a semiconductor chip to be performed.

【0002】[0002]

【従来の技術】異方性導電接着剤を用いた従来のフェイ
スダウン実装においては、半導体チップに形成されてい
る電極パッド上に、予めAu(金)等からなるバンプ電
極を形成しておき、このバンプ電極と回路基板上の端子
電極との間に異方性導電接着剤を入れ、加熱および加圧
により半導体チップの電極パッドと回路基板上の端子電
極との導通を確保するようにしている。
2. Description of the Related Art In conventional face-down mounting using an anisotropic conductive adhesive, a bump electrode made of Au (gold) or the like is formed in advance on an electrode pad formed on a semiconductor chip. An anisotropic conductive adhesive is inserted between the bump electrodes and the terminal electrodes on the circuit board, and the conduction between the electrode pads of the semiconductor chip and the terminal electrodes on the circuit board is ensured by heating and pressing. .

【0003】[0003]

【発明が解決しようとする課題】しかしながら従来の半
導体チップの実装構造においては、半導体チップにバン
プ電極を形成する必要があるので、その分コストアップ
になる。またバンプ電極を複数形成する場合、バンプ電
極の高さにばらつきがあると、接続不良を招くという問
題があった。
However, in a conventional mounting structure of a semiconductor chip, it is necessary to form bump electrodes on the semiconductor chip, which increases the cost. In addition, when a plurality of bump electrodes are formed, if the height of the bump electrodes varies, there is a problem that a connection failure is caused.

【0004】[0004]

【課題を解決するための手段】上記課題を解決するため
に本発明は、導電性接着剤により、基板上に設けられた
端子電極に対して半導体チップの電極パッドを接続する
とともに該半導体チップを基板に対して固定する半導体
チップの実装構造において、前記電極パッドに対応する
位置に開口部を有するパシベーションを前記導電性接着
剤と前記半導体チップとの間に配設し、前記電極パッド
に対向する前記端子電極の対向面の大きさを前記開口部
の大きさより小さくし、前記電極パッドから前記端子電
極までの距離を前記パシベーションから前記基板側まで
の距離より短くしたことを特徴とする。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention connects an electrode pad of a semiconductor chip to a terminal electrode provided on a substrate by using a conductive adhesive. In the mounting structure of the semiconductor chip fixed to the substrate, a passivation having an opening at a position corresponding to the electrode pad is provided between the conductive adhesive and the semiconductor chip, and faces the electrode pad. The size of the opposing surface of the terminal electrode is smaller than the size of the opening, and the distance from the electrode pad to the terminal electrode is shorter than the distance from the passivation to the substrate.

【0005】上記構成を有する本発明によれば、バンプ
電極を形成することなく基板上の端子電極と半導体チッ
プの電極パッドとの接続を確保することができるので、
バンプ電極のコストが削減できるとともに、バンプ電極
の高さのばらつきによる接続不良がなくなる。
According to the present invention having the above structure, the connection between the terminal electrode on the substrate and the electrode pad of the semiconductor chip can be secured without forming a bump electrode.
The cost of the bump electrode can be reduced, and connection failure due to variation in the height of the bump electrode is eliminated.

【0006】[0006]

【発明の実施の形態】以下、本発明の実施の形態を図面
にしたがって説明する。なお各図面に共通の要素には同
一の符号を付す。図1は本発明の実施の形態の半導体チ
ップの実装構造を示す断面図である。
Embodiments of the present invention will be described below with reference to the drawings. Elements common to the drawings are denoted by the same reference numerals. FIG. 1 is a sectional view showing a mounting structure of a semiconductor chip according to an embodiment of the present invention.

【0007】図1において、基板(印刷配線板)1上に
は端子電極2が形成され、また半導体チップ3上には電
極パッド4が設けられている。半導体チップ3はフェイ
スダウン実装され、図における半導体チップ3の下側に
はパシベーション5が形成されている。半導体チップ3
と基板1の間には異方性導電接着剤6が注入されてい
る。パシベーション5は半導体チップ3の表面を保護す
るもので、ガラス等から成っている。また基板1にはス
ルーホール7が形成され、端子電極2が導体パターン1
0と接続されるようになっている。スルーホール7の中
には絶縁性樹脂11が埋め込まれている。
In FIG. 1, terminal electrodes 2 are formed on a substrate (printed wiring board) 1, and electrode pads 4 are provided on a semiconductor chip 3. The semiconductor chip 3 is mounted face-down, and a passivation 5 is formed below the semiconductor chip 3 in the figure. Semiconductor chip 3
An anisotropic conductive adhesive 6 is injected between the substrate and the substrate 1. The passivation 5 protects the surface of the semiconductor chip 3 and is made of glass or the like. Further, a through hole 7 is formed in the substrate 1, and the terminal electrode 2 is connected to the conductor pattern 1.
0 is connected. Insulating resin 11 is embedded in through hole 7.

【0008】上記構造の実装方法を説明すると、まず半
導体チップ3上の電極パッド4と基板1上の端子電極2
との間に異方性導電接着剤6を入れる。このとき電極パ
ッド4上にバンプ電極は形成されない。次に電極パッド
4と端子電極2の位置合わせを行い、その後加熱および
加圧することにより半導体チップ3をフェイスダウンで
基板1上に実装する。
The method of mounting the above structure will be described. First, the electrode pads 4 on the semiconductor chip 3 and the terminal electrodes 2 on the substrate 1
And an anisotropic conductive adhesive 6 is put between them. At this time, no bump electrode is formed on the electrode pad 4. Next, the electrode pads 4 and the terminal electrodes 2 are aligned, and then the semiconductor chip 3 is mounted face down on the substrate 1 by applying heat and pressure.

【0009】図2は実施の形態の半導体チップを示す平
面図であり、図1における半導体チップを下方から見た
図である。図2において、パシベーション5は半導体チ
ップ3のほぼ全面に渡って形成され、パシベーション5
の電極パッド4に対向する部分には開口部5aが形成さ
れている。
FIG. 2 is a plan view showing the semiconductor chip of the embodiment, and is a view of the semiconductor chip in FIG. 1 as viewed from below. In FIG. 2, the passivation 5 is formed over almost the entire surface of the semiconductor chip 3, and the passivation 5 is formed.
An opening 5a is formed in a portion facing the electrode pad 4.

【0010】図1、図2において、パシベーション5の
開口部5aの面積S1は、端子電極2の、電極パッド4
に対向する面の面積より大きくなっている。即ち、端子
電極2の上面の全体が、パシベーション5の開口部5a
の中に含まれる大きさになっている。この構成により、
図1における端子電極2上の導電粒子6aは開口部5a
を介して電極パッド4とのみ接触し、パシベーション5
とは接触しない。異方導電接着剤6には導電粒子6aが
含まれており、この導電粒子6aが端子電極2と電極パ
ッド4とにより上下から押し潰されることにより、端子
電極2と電極パッド4との間で通電可能な状態になる。
導電粒子6aの大きさは数〜20μm程度であり、導電
粒子6aが押し潰されて通電可能な状態になるには、端
子電極2と電極パッド4とは、間の距離が数〜20μm
以下になるまで接近する。
In FIG. 1 and FIG. 2, the area S1 of the opening 5a of the passivation 5 is
Is larger than the area of the surface opposed to. That is, the entire upper surface of the terminal electrode 2 is covered with the opening 5 a of the passivation 5.
The size is included in the. With this configuration,
The conductive particles 6a on the terminal electrode 2 in FIG.
Contact only with the electrode pad 4 through the
Does not contact with The anisotropic conductive adhesive 6 contains conductive particles 6a, and the conductive particles 6a are crushed from above and below by the terminal electrode 2 and the electrode pad 4, so that the conductive particles 6a are formed between the terminal electrode 2 and the electrode pad 4. It will be in a state where it can be energized.
The size of the conductive particles 6a is about several to 20 μm, and the distance between the terminal electrode 2 and the electrode pad 4 is several to 20 μm in order for the conductive particles 6a to be crushed and become energized.
Approach until it is below.

【0011】また端子電極2と電極パッド6との間の距
離T1は基板1からパシベーション5までの距離T2よ
り小さく設定されている。この構成により、図1におけ
る端子電極2上の導電粒子6aが電極パッド4に接触す
るのが、基板1上の導電粒子6aがパシベーション5に
接触するのより先になる。これにより基板1上の導電粒
子6aがパシベーション5に先に接触することによる電
気的接続不良あるいはパシベーション5の破壊等を防止
できる。
The distance T1 between the terminal electrode 2 and the electrode pad 6 is set smaller than the distance T2 from the substrate 1 to the passivation 5. With this configuration, the conductive particles 6 a on the terminal electrode 2 in FIG. 1 contact the electrode pad 4 before the conductive particles 6 a on the substrate 1 contact the passivation 5. Accordingly, it is possible to prevent an electrical connection failure or breakage of the passivation 5 due to the conductive particles 6a on the substrate 1 coming into contact with the passivation 5 first.

【0012】図3は他の半導体チップの実装構造を示す
断面図である。図3において、基板1上には端子電極2
のほかにパターン8a、8bが実装されている。これら
のパターン8a、8bは半導体チップ3の搭載領域T3
より外側に形成されている。即ち、半導体チップ3の搭
載領域T3とパターン8a、8bとの間に間隙T4を設
けている。仮にパターン8a、8bが半導体チップ3の
搭載領域T3内に設けられ、パターン8a、8bとパシ
ベーション5との間の距離が端子電極2と電極パッド4
との間の距離より小さいとすると、端子電極2上の導電
粒子6aが電極パッド4に接触するよりも先に、パター
ン8a、8b上の導電粒子6aがパシベーション5に接
触することになり、電気的接続不良あるいはパシベーシ
ョン5の破壊等が発生することになる。このように半導
体チップ3の搭載領域T3内をパターン非形成部とする
ことによりこれらの問題が解決される。
FIG. 3 is a sectional view showing a mounting structure of another semiconductor chip. In FIG. 3, a terminal electrode 2 is provided on a substrate 1.
In addition, patterns 8a and 8b are mounted. These patterns 8a and 8b correspond to the mounting area T3 of the semiconductor chip 3.
It is formed more outside. That is, the gap T4 is provided between the mounting area T3 of the semiconductor chip 3 and the patterns 8a and 8b. Assuming that the patterns 8a and 8b are provided in the mounting area T3 of the semiconductor chip 3, the distance between the patterns 8a and 8b and the passivation 5 is determined by the terminal electrode 2 and the electrode pad 4.
If the distance is smaller than the distance between the conductive particles 6a on the terminal electrodes 2, the conductive particles 6a on the patterns 8a and 8b contact the passivation 5 before the conductive particles 6a contact the electrode pad 4, and A poor connection or destruction of the passivation 5 will occur. These problems can be solved by setting the inside of the mounting area T3 of the semiconductor chip 3 as the pattern non-forming portion.

【0013】仮にパターン8a、8bを半導体チップ3
の搭載領域T3内に設けても、パターン8a、8bとパ
シベーション5との間の距離が端子電極2と電極パッド
4との間の距離より大きければ問題はないことになる
が、この条件を満たすような高さを持ったパターン8
a、8bを製造するのは極めて困難であるので、半導体
チップ3の搭載領域T3内には全面的にパターン8a、
8bを設けないことにした方が製造上容易である。しか
しながら、上記条件を満足する高さを有するパターン8
a、8bを製造可能であれば、基板1の半導体チップ3
側で搭載領域T3内に設けるようにしてもよい。
If the patterns 8a and 8b are temporarily
No problem occurs if the distance between the patterns 8a and 8b and the passivation 5 is larger than the distance between the terminal electrode 2 and the electrode pad 4 even if they are provided in the mounting region T3. Pattern 8 with such height
Since it is extremely difficult to manufacture the patterns 8a, 8b, the patterns 8a, 8b are entirely formed in the mounting region T3 of the semiconductor chip 3.
It is easier to manufacture without providing 8b. However, the pattern 8 having a height satisfying the above condition
a and 8b can be manufactured, the semiconductor chip 3 of the substrate 1
May be provided in the mounting area T3 on the side.

【0014】以上のように異方性導電接着剤を用いた半
導体チップのフェイスダウンボンディングにおいて、バ
ンプ電極を形成せずに接続を確保することができるの
で、バンプ電極のコストが削減できるとともに、バンプ
電極の高さのばらつきを考慮する必要がなくなるので、
接続品質の向上が図れる。
As described above, in face-down bonding of a semiconductor chip using an anisotropic conductive adhesive, connection can be secured without forming a bump electrode, so that the cost of the bump electrode can be reduced and the bump electrode can be cut. Since there is no need to consider variations in electrode height,
Connection quality can be improved.

【0015】[0015]

【発明の効果】以上詳細に説明したように本発明によれ
ば、導電性接着剤により、基板上に設けられた端子電極
に対して半導体チップの電極パッドを接続するとともに
該半導体チップを基板に対して固定する半導体チップの
実装構造において、前記電極パッドに対応する位置に開
口部を有するパシベーションを前記導電性接着剤と前記
半導体チップとの間に配設し、前記電極パッドに対向す
る前記端子電極の対向面の大きさを前記開口部の大きさ
より小さくし、前記電極パッドから前記端子電極までの
距離を前記パシベーションから前記基板までの距離より
短くしたので、バンプ電極を形成することなく基板上の
端子電極と半導体チップの電極パッドとの接続を確保す
ることができるので、バンプ電極のコストが削減できる
とともに、バンプ電極の高さのばらつきによる接続不良
がなくなる。
As described above in detail, according to the present invention, the electrode pads of the semiconductor chip are connected to the terminal electrodes provided on the substrate by the conductive adhesive, and the semiconductor chip is connected to the substrate. In the semiconductor chip mounting structure to be fixed to the semiconductor chip, a passivation having an opening at a position corresponding to the electrode pad is provided between the conductive adhesive and the semiconductor chip, and the terminal facing the electrode pad is provided. The size of the opposing surface of the electrode was smaller than the size of the opening, and the distance from the electrode pad to the terminal electrode was shorter than the distance from the passivation to the substrate, so that the bump electrode was not formed on the substrate. The connection between the terminal electrode of the semiconductor chip and the electrode pad of the semiconductor chip can be secured, so that the cost of the bump electrode can be reduced and Poor connection due to variation in the pole height is eliminated.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施の形態の半導体チップの実装構造を示す断
面図である。
FIG. 1 is a cross-sectional view illustrating a mounting structure of a semiconductor chip according to an embodiment.

【図2】実施の形態の半導体チップを示す平面図であ
る。
FIG. 2 is a plan view showing a semiconductor chip of the embodiment.

【図3】他の半導体チップの実装構造を示す断面図であ
る。
FIG. 3 is a cross-sectional view illustrating a mounting structure of another semiconductor chip.

【符号の説明】[Explanation of symbols]

1 基板 2 端子電極 3 半導体チップ 4 電極パッド 5 パシベーション 6 異方性導電接着剤 8a、8b パターン DESCRIPTION OF SYMBOLS 1 Substrate 2 Terminal electrode 3 Semiconductor chip 4 Electrode pad 5 Passivation 6 Anisotropic conductive adhesive 8a, 8b Pattern

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 異方性導電接着剤により、基板上に設け
られた端子電極に対して半導体チップの電極パッドを接
続するとともに該半導体チップを基板に対して固定する
半導体チップの実装構造において、 前記電極パッドに対応する位置に開口部を有するパシベ
ーションを前記異方性導電接着剤と前記半導体チップと
の間に配設し、 前記電極パッドに対向する前記端子電極の対向面の大き
さを前記開口部の大きさより小さくし、 前記電極パッドから前記端子電極までの距離を前記パシ
ベーションから前記基板側までの距離より短くしたこと
を特徴とする半導体チップの実装構造。
In a semiconductor chip mounting structure, an electrode pad of a semiconductor chip is connected to a terminal electrode provided on a substrate by an anisotropic conductive adhesive, and the semiconductor chip is fixed to the substrate. A passivation having an opening at a position corresponding to the electrode pad is provided between the anisotropic conductive adhesive and the semiconductor chip. A mounting structure for a semiconductor chip, wherein the distance from the electrode pad to the terminal electrode is shorter than the distance from the passivation to the substrate side, the size being smaller than the size of the opening.
【請求項2】 前記半導体チップの搭載領域内をパター
ン非形成部を設けた請求項1記載の半導体チップの実装
構造。
2. The semiconductor chip mounting structure according to claim 1, wherein a pattern non-forming portion is provided in a mounting area of said semiconductor chip.
JP16068498A 1998-06-09 1998-06-09 Mounting structure for semiconductor chip Withdrawn JPH11354579A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16068498A JPH11354579A (en) 1998-06-09 1998-06-09 Mounting structure for semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16068498A JPH11354579A (en) 1998-06-09 1998-06-09 Mounting structure for semiconductor chip

Publications (1)

Publication Number Publication Date
JPH11354579A true JPH11354579A (en) 1999-12-24

Family

ID=15720241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16068498A Withdrawn JPH11354579A (en) 1998-06-09 1998-06-09 Mounting structure for semiconductor chip

Country Status (1)

Country Link
JP (1) JPH11354579A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8198729B2 (en) 2004-07-16 2012-06-12 Megica Corporation Connection between a semiconductor chip and a circuit component with a large contact area

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8198729B2 (en) 2004-07-16 2012-06-12 Megica Corporation Connection between a semiconductor chip and a circuit component with a large contact area

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

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Effective date: 20050906