JPH01168117A - Error pulse eliminating circuit - Google Patents

Abstract

PURPOSE:To eliminate many erroneous pulses completely even if they are inputted even at a short time interval by using a monostable multivibrator to decide the threshold width of an error pulse included in an input pulse signal. CONSTITUTION:When an error pulse (a) is inputted and changes from '0' to '1', the change is fed to a rising trigger input of a monostable multivibrator 3 through an AND gate 1, a pulse of a width T2 is outputted, and an inverse of SQ1 is inputted to a timing terminal of a D flip-flop 4. Thus, the D flip-flop 4 reads an input signal SI at the point of time when the output of pulses of the monostable multivibrator 3 is finished. When many error pulses below the threshold value are inputted at a short interval, the monostable multivibrator 3 is retrigged and the inverse of output SQ1 is kept to '0' till the error pulse is finished. Thus, the error pulse with a pulse width below the time constant T2 of the monostable multivibrator 3 is not read in the D flip-flop 4 and the error pulse (a) is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error pulse removal circuit for a digital logic circuit.

[Conventional technology]

Conventionally, this type of erroneous pulse removal circuit has used an RC time constant circuit including a resistor 11 and a capacitor 12, as shown in FIG.

[Problem that the invention seeks to solve]

In the above-described erroneous signal elimination circuit, if a large number of erroneous noculus are inputted at short intervals, the next erroneous signal will be inputted before the capacitor 12 is sufficiently discharged. For this reason, there is a drawback that the threshold value of the Noculus width is smaller than the expected value, and erroneous pulses cannot be removed sufficiently.

In addition, in the circuit shown in FIG. 3, the threshold value of the pulse width is determined using the input voltage threshold value of the inverter gate 13, so the threshold value of the inverter gate 13 is exactly 1/2 of the power supply voltage. Otherwise, there will be a difference in charging time and discharging time. Therefore, when a normal pulse having a width equal to or larger than a threshold value is input, there is a drawback that pulse width distortion occurs.

The present invention aims to provide an erroneous cycle elimination circuit with a simple configuration that eliminates the above-mentioned drawbacks.

[Means for solving problems]

The false signal elimination circuit of the present invention includes a monostable multivibrator for determining the threshold width of the false signal included in the input pulse signal, and a D-type flip-flop that reads the input signal using the output of the monostable multivibrator. and input A? according to the output of the flip-flop. and a logic circuit for triggering the monostable multivibrator at both the rising edge and falling edge of the pulse.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. 1 is and gate,
2 is an OR f-), 3 is a monostable multivibrator, and 4 is a D-type flip-flop! It is.

FIG. 2 is a time chart of the signals of each part in FIG.

First, a case will be described in which the erroneous pulse (2) of FIG. 2 is input to the circuit of FIG. 1.

When the error pulse ■ is input and changes from 0 to 1, the change is applied to the trigger input for monostable multivibrator 3 through AND gate 1, and monostable multivibrator 3 .

Outputs f pulses of width T2. The inverted output SQI of the monostable multivibrator 30 is input to the timing terminal of the D-type flip-flop 4. For this reason.

The D-type flip-flop 4 reads the input signal SI at the time when the output pulse of the monostable multivibrator 3 ends. By doing this, an error pulse with a pulse width less than the time constant T2 of the monostable multivibrator 3 is not read into the D-type flip-frog 4.

False 9 No. 4 Rus ■ will be removed. Note that if a large number of false pulses below the threshold are input at short intervals, the monostable multivibrator 3 is retriggered.

Incorrect t) Set the inverted output SQI to '0' until the z4 pulse is completed.
Therefore, the threshold width does not become smaller as in conventional circuits.

Next, a case where normal 9 pulses (pulse width T3) is input will be described. Monostable multivibrator 3 is triggered by the rising edge of input signal SI.

Outputs the width T2. When the signal SQI rises after the lapse of time T2, 11'' is read into the D-type flip-flop f4 because T3>T2, and '1' is output as the output SQ2. When the pulse (2) falls after 73 hours, the monostable multipubulator 3 is triggered again through the or-dart 2 and outputs a pulse of width T2 to the terminal Q1. D-type FRI: Zoflog 4 reads the input signal 60'' at the time when the / mother pulse of this width T2 rises, and outputs 0'' to the terminal Q2. That is, when a normal pulse is input.

This is because the same monostable multivibrator 3 is triggered at the rising and falling points of the input pulse.

The delay of the signal at the time of rising and the delay of the signal at the time of falling become equal, and no signal width distortion occurs.

〔Effect of the invention〕

As explained above, the present invention uses a monostable multivibrator to determine the threshold width, thereby completely eliminating even if a large number of false pulses are input at short time intervals. It is possible to do so. And normal A that exceeds the threshold width? This has the effect that even when a pulse is input, it can be output without generating Nockles width distortion.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of an embodiment of the present invention, Fig. 2 is a time chart of signals of each part in Fig. 1, and Fig. 3 is a conventional error No. 4
This is a noise removal circuit. 3... Monostable multivibrator, 4... D type flip frog, 13... Inverter gate.

Claims (1)

[Claims] 1. A monostable multivibrator that determines the threshold width of the error pulse included in the input pulse signal, a D-type flip-flop that reads the input pulse signal using the output signal of the monostable multivibrator as a timing, and the D-type flip-flop. An error pulse removal circuit comprising a logic circuit for selecting a trigger input terminal of the monostable multivibrator in accordance with the output of the monostable multivibrator, and preventing generation of pulse width distortion of input pulses.