JPH01161848A - Manufacture of semiconductor device with field oxide film - Google Patents
Manufacture of semiconductor device with field oxide filmInfo
- Publication number
- JPH01161848A JPH01161848A JP32081987A JP32081987A JPH01161848A JP H01161848 A JPH01161848 A JP H01161848A JP 32081987 A JP32081987 A JP 32081987A JP 32081987 A JP32081987 A JP 32081987A JP H01161848 A JPH01161848 A JP H01161848A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- si3n4
- field oxide
- resistant mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 43
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 abstract description 6
- 230000005611 electricity Effects 0.000 abstract description 5
- 230000003068 static effect Effects 0.000 abstract description 5
- 230000006378 damage Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910005091 Si3N Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
集積回路において回路素子を構成する半導体島領域を互
いに電気的に分離するフィールド酸化膜を有する半導体
装置の製造方法に関し、静電気によるフィールド酸化膜
境界部の破壊を未然に防止することを目的とし、
半導体基板上の第１の酸化膜上に耐酸化マスクを被着し
た後熱酸化処理を行なって第２の酸化膜を形成し、その
後該耐酸化マスクを除去する工程を、該耐酸化マスクの
サイズを各工程毎にｌｌｉ調的に変化させつつ一定回数
繰り返すことにより、多段階の段差からなる傾斜部を有
する酸化膜を素子分離用フィールド酸化膜として形成す
る工程を含むよう構成する。Detailed Description of the Invention [Summary] A method for manufacturing a semiconductor device having a field oxide film that electrically isolates semiconductor island regions constituting circuit elements in an integrated circuit from each other, which prevents destruction of field oxide film boundaries due to static electricity. In order to prevent this from occurring, an oxidation-resistant mask is deposited on the first oxide film on the semiconductor substrate, a thermal oxidation treatment is performed to form a second oxide film, and then the oxidation-resistant mask is removed. By repeating this process a certain number of times while changing the size of the oxidation-resistant mask in a lli scale for each process, an oxide film having a sloped portion consisting of multiple steps is formed as a field oxide film for element isolation. Configure to include processes.
本発明はフィールド酸化膜を有する半導体装置の製造方
法に係り、特に集積回路において回路素子を構成する半
導体島領域を互いに電気的に分離するフィールド酸化膜
を有する半導体装置の製造方法に関する。The present invention relates to a method of manufacturing a semiconductor device having a field oxide film, and more particularly to a method of manufacturing a semiconductor device having a field oxide film that electrically isolates semiconductor island regions forming circuit elements in an integrated circuit.
第４図（Ａ＞は集積回路内に使用されるＣＭＯＳトラン
ジスタの構造説明用平面図、同図（Ｂ）は同図（Ａ）の
Ａ−Ａ’線に沿う断面図を示す。第４図（Ａ）、（Ｂ）
中、１はシリコン基板、２はフィールド酸化膜、３はゲ
ート酸化膜、４は多結晶シリコンによるゲート電極、５
は保護膜、６はアルミニウム配線、７ａと７ｂはＰ＋拡
散層、８ａと８ｂはｎ＋拡散層である。ゲート電極４は
コンタクトホールを介してアルミニウム配線６と接続さ
れている。FIG. 4 (A> is a plan view for explaining the structure of a CMOS transistor used in an integrated circuit, and FIG. 4 (B) is a cross-sectional view taken along line AA' in FIG. 4 (A). (A), (B)
Inside, 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate electrode made of polycrystalline silicon, 5
6 is a protective film, 6 is an aluminum wiring, 7a and 7b are P+ diffusion layers, and 8a and 8b are n+ diffusion layers. Gate electrode 4 is connected to aluminum wiring 6 via a contact hole.
Ｐ＋拡散層７ａ、７ｂ、ゲート酸化膜３及びゲート電極
４はＰヂャンネルＭＯ８型電界効果トランジスタ（ＦＥ
Ｔ）を構成しており、ｎ＋拡散層８ａ、 ８ｂ、ゲート
酸化膜３及びゲート電極４はＮチャンネルＭＯ８型電界
効果トランジスタ（ＦＥＴ）を構成しており、またこれ
らのＦＥ［はフィールド酸化膜２により電気的に分離さ
れている。The P+ diffusion layers 7a, 7b, the gate oxide film 3, and the gate electrode 4 are a P channel MO8 type field effect transistor (FE).
The n+ diffusion layers 8a and 8b, the gate oxide film 3, and the gate electrode 4 constitute an N-channel MO8 type field effect transistor (FET), and these FE [are field oxide films 2 and 4]. electrically isolated by
かかるＣＭＯＳトランジスタを製）告する場合、通常は
シリコン基板１の上に二酸化シリコン（ＳｉＯｚ）より
なる酸化膜と窒化シリコン（ＳｔａＮ４）膜とを順次に
積層した後、所定のパターンにエツチングし、その後に
８！３Ｎ４膜を耐酸化マスクとして熱酸化処理を行ない
、はぼ９００℃で適切な膜厚（例えば約８０００人）の
酸化膜５ｆＯｚをシリコン基板１の表面上にフィールド
酸化膜２として形成する。When manufacturing such a CMOS transistor, normally an oxide film made of silicon dioxide (SiOz) and a silicon nitride (StaN4) film are sequentially laminated on a silicon substrate 1, and then etched into a predetermined pattern. Then, a thermal oxidation process is performed using the 8!3N4 film as an oxidation-resistant mask, and an oxide film of 5fOz with an appropriate thickness (for example, about 8000 layers) is formed on the surface of the silicon substrate 1 as a field oxide film 2 at approximately 900°C. .
その後、５Ｉ３Ｎａ膜を除去し、その除去部分下のゲー
ト酸化膜３上等に多結晶シリコンのゲート電極４を作成
した後、ソース領域、ドレイン領域としてＰ＋拡散層７
ａと７ｂをイオン注入により形成し、更に同様にしてｎ
＋拡散層８ａと８ｂも形成する。After that, the 5I3Na film is removed and a polycrystalline silicon gate electrode 4 is formed on the gate oxide film 3 under the removed portion, and then a P+ diffusion layer 7 is formed as a source region and a drain region.
a and 7b are formed by ion implantation, and then n is formed in the same manner.
+ Diffusion layers 8a and 8b are also formed.
しかるに、第４図（Ｂ）に９で示す如く、フィールド酸
化膜２とゲート酸化膜３との境界は大なる段差となるた
め、配線６を介して静電気によるノイズ等の極めて高い
電圧が入力されると、その段差部（フィールド酸化膜境
界部）に電荷の集中が発生する。これにより、上記の場
合は第４図（Ａ）に破線で囲んだ段差部分１０において
静電破壊が生ずることがあるという問題点があった。However, as shown by 9 in FIG. 4(B), the boundary between the field oxide film 2 and the gate oxide film 3 has a large step, so that extremely high voltages such as noise due to static electricity are inputted via the wiring 6. As a result, charge concentration occurs at the stepped portion (field oxide film boundary portion). As a result, in the above case, there is a problem in that electrostatic discharge damage may occur in the step portion 10 surrounded by the broken line in FIG. 4(A).
本発明は上記の点に鑑みてなされたもので、静電気によ
るフィールド酸化膜境界部の破壊を未然に防止すること
ができるフィールド酸化膜を有する半導体装置の製造方
法を提供することを目的とする。The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for manufacturing a semiconductor device having a field oxide film, which can prevent destruction of the boundary portion of the field oxide film due to static electricity.
本発明のフィールド酸化膜を有する半導体装置の製造方
法は、半導体基板上の第１の酸化膜上に耐酸化マスクを
被着した後熱酸化処理を行なって第２の酸化膜を形成し
、その後′Ｍ耐酸化マスク除去するＩ稈を、耐酸化マス
クのサイズを各工程毎に単調的に変化させつつ一定回数
繰り返すようにしたものである。The method of manufacturing a semiconductor device having a field oxide film according to the present invention includes depositing an oxidation-resistant mask on a first oxide film on a semiconductor substrate, performing thermal oxidation treatment to form a second oxide film, and then forming a second oxide film. The I culm in which the oxidation-resistant mask 'M is removed is repeated a fixed number of times while monotonically changing the size of the oxidation-resistant mask for each step.
耐酸化マスクはその勺イズが各：［程毎に単調的に変化
されるから、まず半導体基板上の第１の酸化膜上に耐酸
化マスクを被着した後熱酸化処理により第２の酸化膜が
形成される。次に少なくとも上記の第１の酸化膜が形成
されていない部分に上記の耐酸化マスクとはサイズが縮
小された（又は増加された）別の耐酸化マスクを被着し
た後、第３の酸化膜を上記第２の酸化股上に形成する。Since the oxidation-resistant mask changes monotonically with each step, the oxidation-resistant mask is first deposited on the first oxide film on the semiconductor substrate, and then the second oxidation film is applied by thermal oxidation treatment. A film is formed. Next, a different oxidation-resistant mask whose size is reduced (or increased) from the above-mentioned oxidation-resistant mask is deposited on at least the portion where the first oxide film is not formed, and then a third oxidation-resistant mask is applied. A film is formed on the second oxide crotch.
ここで、上記の２つの耐酸化マスクはサイズが異なるか
ら、第２及び第３の酸化膜の境界部分では段差がつき、
全体として傾斜部となる。Here, since the above two oxidation-resistant masks have different sizes, there is a step at the boundary between the second and third oxide films.
The entire area becomes a slope.
以下、上記と同様にして耐酸化マスクのサイズは順番に
縮小（又は増加）される］［稈を繰り返すことにより、
多段階の段差からなる傾斜部を有する酸化膜が形成され
る。Thereafter, the size of the oxidation-resistant mask is sequentially reduced (or increased) in the same manner as above] [By repeating the culm,
An oxide film having a sloped portion consisting of multiple steps is formed.
上記の多段階の段差の各々は従来のフィールド酸化膜の
境界部分の段差よりもはるかに小であるため、その１段
当りの段差への電荷の集中は少なく、全体として分散さ
れる。Since each of the above-mentioned multi-level steps is much smaller than the step at the boundary of a conventional field oxide film, the concentration of charge on each step is small and is dispersed as a whole.
第１図は本発明の第１実施例の各工程の説明図を示す。 FIG. 1 shows an explanatory diagram of each process of the first embodiment of the present invention.
まず、シリコン基板１２上に５ｉＯｚ膜１３とＳｉ３Ｎ
４膜１４とを順次に積層した後所定パターンでエツチン
グして第１図（Ａ）に示す如く、幅Ｗ１のサイズの５ｆ
Ｏｚ膜１３及びＳｉ３Ｎ４膜１４を形成する。First, a 5iOz film 13 and a Si3N film are placed on a silicon substrate 12.
After sequentially stacking the four films 14, they are etched in a predetermined pattern to form a 5f film with a width W1 as shown in FIG. 1(A).
An Oz film 13 and a Si3N4 film 14 are formed.
次にＳｉ３Ｎ４膜１４を耐酸化マスクとして熱酸化処理
を行なう。ここで、熱酸化処理は例えば９００℃の温度
下で行なった場合、第２図に示す如く６０分の処理時間
で８０００人の膜厚の酸化膜（Ｓ ！ ０２膜）が形成
され、また処理時間に略指数関数的に比例した膜厚の酸
化膜が形成される。Next, thermal oxidation treatment is performed using the Si3N4 film 14 as an oxidation-resistant mask. Here, when the thermal oxidation treatment is carried out at a temperature of, for example, 900°C, an oxide film (S!02 film) with a thickness of 8000 mm is formed in a treatment time of 60 minutes as shown in Fig. An oxide film is formed whose thickness is approximately exponentially proportional to time.
そこで、第１図（Ａ＞に示す半導体装置に対する熱酸化
処理は第２図にａで示す如り６００分行なうことにより
８０００人の膜厚の酸化膜が形成される。Therefore, the thermal oxidation treatment for the semiconductor device shown in FIG. 1 (A>) is carried out for 600 minutes as shown in FIG.
その後で、上記のＳｉＯ２膜１３及び３ｉ３Ｎ４膜１４
が夫々公知の手段で除去されることにより、第１図（Ｂ
）に示す如＜、−３ｉ３Ｎ４膜１４が存在しなかったシ
リコン基板１２の露出表面に上記の膜厚８０００人の酸
化膜（ＳｉＯ２）１５だけが形成されたものとなる。After that, the above-mentioned SiO2 film 13 and 3i3N4 film 14 are
1 (B) are removed by known means, respectively.
), only the oxide film (SiO2) 15 with a thickness of 8000 nm is formed on the exposed surface of the silicon substrate 12 where the -3i3N4 film 14 was not present.
次に第１図（Ｃ）に示す如く、再び前記Ｓｉ３Ｎ４膜１
４が位置した場所に、幅Ｗ２ （Ｗ２ ＜Ｗ＋）の５
ｉ３Ｎ４８１６を例えば化学気相成長法（ＣＶＤ法）に
より被着する。その後で熱酸化処理を第２図にｂで示す
時間行なって８０００人より小なる３ｉ０２ＷＪを成長
させ、Ｓ！３Ｎ４膜１６を除去する。Next, as shown in FIG. 1(C), the Si3N4 film 1 is again
5 of width W2 (W2 < W+)
i3N4816 is deposited, for example, by chemical vapor deposition (CVD). Thereafter, thermal oxidation treatment was carried out for the time indicated by b in FIG. 2 to grow 3i02WJ smaller than 8000, and S! The 3N4 film 16 is removed.
これにより、第１図（Ｄ）に示す如く、Ｓｉ３Ｎ４膜１
６の幅Ｗ２がＳｉ３Ｎ４膜１４の幅Ｗ＋よりも小なので
、５ｔＯｚ膜１５よりも穏やかな傾斜をもち、かつ、途
中に１８で示す如く段差のある５ｆＯｚ膜１７が形成さ
れる。As a result, as shown in FIG. 1(D), the Si3N4 film 1
Since the width W2 of 6 is smaller than the width W+ of the Si3N4 film 14, a 5fOz film 17 is formed which has a gentler slope than the 5tOz film 15 and has a step as shown at 18 in the middle.
以下、上記と同様にして前回のＳｉ３Ｎ４膜より幅の狭
い（リイズの小さい）ＳｉｓＮ４膜の被着→前回より時
間の短い熱酸化処理−→５ｉａＮａ膜の除去という一連
の工程を所定回数繰り返すことにより、最終的に第１図
（Ｅ）に示す如く、基板１２の表面に多段階の段差を有
する傾斜部を持つＳｉＯ２膜１９がフィールド酸化膜と
して形成される。なお、１３は３ｉ３Ｎ４ｇｌにより酸
化されないようにしていた部分の５ｉＯｚ膜で、ゲート
酸化膜として用いられる。Thereafter, in the same manner as above, the series of steps of depositing a SisN4 film having a narrower width (smaller rise) than the previous Si3N4 film -> thermal oxidation treatment for a shorter time than the previous time -> removing the 5iaNa film - is repeated a predetermined number of times. Finally, as shown in FIG. 1(E), an SiO2 film 19 having a sloped portion having multiple steps is formed on the surface of the substrate 12 as a field oxide film. Note that 13 is a portion of the 5iOz film that is protected from oxidation by 3i3N4gl, and is used as a gate oxide film.
次に本発明の第２実施例について第３図と共に説明する
。第１実施例ではＳｉ３Ｎ４膜を各工程毎に徐々に狭め
ていったが、本実施例は逆に徐々に広げていくようにし
たものである。Next, a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the Si3N4 film was gradually narrowed in each step, but in this embodiment, on the contrary, it was gradually widened.
すなわち、シリコン基板２１上に順次に５ＩＯｚ膜２２
．５ｔ３Ｎ４膜２３を形成した後、幅Ｗ３の５ｉｘＮ４
膜を耐酸化マスクとして熱酸化処理を短時間行ない、そ
の後に５ｔＯｚＷＡ２２及び５ｉｓＮ４膜２３を除去す
る。すると、第３図（Ｂ）に示す如く膜厚の薄い５ｉＯ
ｚｌ！ａ２４がＳ！３Ｎ４膜２３の存在しなかった基板
露出面上に生成される。That is, a 5IOz film 22 is sequentially formed on a silicon substrate 21.
．． After forming the 5t3N4 film 23, a 5ixN4 film of width W3 is formed.
A thermal oxidation process is performed for a short time using the film as an oxidation-resistant mask, and then the 5tOzWA film 22 and the 5isN4 film 23 are removed. Then, as shown in Figure 3(B), a thin 5iO film is formed.
zl! a24 is S! It is produced on the exposed surface of the substrate where the 3N4 film 23 did not exist.
次に第３図（Ｃ）に示す如く、Ｓ！３Ｎ４膜２３が存在
していた場所を含む幅Ｗ４ （Ｗ４ ＞Ｗ３）（７）
位！ＨＣ８ｉ ３ Ｎ４膜２５がＣＶＤ法等により被着
される。そして、この５ｉｚＮｔ膜２５を耐酸化マスク
として熱酸化処理を前記最初の処理時間よりも長い時間
かけて行なう。Next, as shown in FIG. 3(C), S! Width W4 including the area where the 3N4 film 23 was present (W4 > W3) (7)
Rank! A HC8i 3 N4 film 25 is deposited by CVD or the like. Then, using this 5izNt film 25 as an oxidation-resistant mask, thermal oxidation treatment is performed for a longer time than the first treatment time.
そして、上記のＳｉ３Ｎ４膜２５を除去すると、シリコ
ン基板２１の表面には、第３図（Ｄ）に示す如く、１段
の段差２７のある傾斜部を持つ５ｔＯ２膜２６が形成さ
れる。When the Si3N4 film 25 is removed, a 5tO2 film 26 having an inclined portion with a single step 27 is formed on the surface of the silicon substrate 21, as shown in FIG. 3(D).
以下、上記と同様にして前回のＳ ｉ ３Ｎ、４膜より
幅の広い（サイズの大ぎい）Ｓｉ３Ｎ４膜の被着→前回
より時間の長い熱酸化処理−→５ｉ３Ｎａ膜の除去とい
う一連の工程を所定の回数繰り返すことにより、最終的
に第３図（Ｅ）に示す如く、基板２１の表面に多段階の
段差を有する傾斜部を持つ５ｉＯｚ膜２８がフィールド
酸化膜として形成される。Hereinafter, in the same manner as above, a series of steps were performed: deposition of a Si3N4 film that was wider (larger in size) than the previous Si3N, 4 film -> thermal oxidation treatment that took longer than the previous time -> removal of the 5i3Na film. By repeating the process a predetermined number of times, a 5iOz film 28 is finally formed on the surface of the substrate 21 as a field oxide film, as shown in FIG. 3(E).
上述の如く、本発明によれば、フィールド酸化膜の境界
部分を、各々小なる多段の段差からなる傾斜部に作成し
たので、従来にくらべて静電気の電荷の集中がなく、分
散されるので、静電気による上記境界部分の破壊を未然
に防止する゛ことができ、またフィールド酸化膜の境界
部分に隣接するゲート酸化膜も十分に作成させることが
できる等の特長を有するものである。As described above, according to the present invention, the boundary portion of the field oxide film is formed into an inclined portion consisting of multiple small steps, so that electrostatic charges are not concentrated and are dispersed compared to the conventional method. This method has the advantage that it is possible to prevent the boundary portion from being destroyed by static electricity, and that the gate oxide film adjacent to the boundary portion of the field oxide film can also be sufficiently formed.
第１図及び第３図は夫々本発明の各実施例の各工程説明
図、
第２図は熱酸化時間と膜厚との関係図、第４図はＣＭＯ
Ｓトランジスタの構造説明図である。
図において、
１２．２１はシリコン基板、
１３．１５，１７．１９，２２．２４．２６゜２８はＳ
ｉＯ２膜、
１４．１６．２３．２５はＳ！ａＮ４膜、１８．２７は
段差
を示す。
特許出願人 富 士 通 株式会社
同 株式会社
九州富士通エレクトロニクス
第１図
（時間）６００分
選も西史イ乙吟閣と月糺季との関イ示図第２図
ＣＭＯ５）ラシジスタの構造都乙明図
第４図Figures 1 and 3 are explanatory diagrams of each process of each embodiment of the present invention, Figure 2 is a diagram showing the relationship between thermal oxidation time and film thickness, and Figure 4 is a CMO
FIG. 2 is a structural explanatory diagram of an S transistor. In the figure, 12.21 is a silicon substrate, 13.15, 17.19, 22.24.26°28 is S
iO2 film, 14.16.23.25 is S! aN4 film, 18.27 indicates a step. Patent Applicant: Fujitsu Co., Ltd. Kyushu Fujitsu Electronics Co., Ltd. Figure 1 (Time) 600 minutes Diagram showing the relationship between Saishi Itsuginkaku and Tsuki Tadasuki Figure 2 CMO 5) Structure of Lasisister Ming map figure 4
Claims (1)
化マスクを被着した後熱酸化処理を行なつて第２の酸化
膜を形成し、その後該耐酸化マスクを除去する工程を、
該耐酸化マスクのサイズを各工程毎に単調的に変化させ
つつ一定回数繰り返すことにより、多段階の段差からな
る傾斜部を有する酸化膜（１９、２８）を素子分離用フ
ィールド酸化膜として形成する工程を含むことを特徴と
するフィールド酸化膜を有する半導体装置の製造方法。After depositing an oxidation-resistant mask on the first oxide film on the semiconductor substrate (12, 21), a thermal oxidation treatment is performed to form a second oxide film, and then the step of removing the oxidation-resistant mask is performed. ,
By repeating the process a certain number of times while monotonically changing the size of the oxidation-resistant mask for each process, an oxide film (19, 28) having a sloped portion consisting of multiple steps is formed as a field oxide film for element isolation. 1. A method of manufacturing a semiconductor device having a field oxide film, the method comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32081987A JPH01161848A (en) | 1987-12-18 | 1987-12-18 | Manufacture of semiconductor device with field oxide film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32081987A JPH01161848A (en) | 1987-12-18 | 1987-12-18 | Manufacture of semiconductor device with field oxide film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01161848A true JPH01161848A (en) | 1989-06-26 |
Family
ID=18125584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32081987A Pending JPH01161848A (en) | 1987-12-18 | 1987-12-18 | Manufacture of semiconductor device with field oxide film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01161848A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714414A (en) * | 1996-08-19 | 1998-02-03 | Micron Technology, Inc. | Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate |
| US5780352A (en) * | 1995-10-23 | 1998-07-14 | Motorola, Inc. | Method of forming an isolation oxide for silicon-on-insulator technology |
| JP2008260463A (en) * | 2007-04-13 | 2008-10-30 | Takata Corp | Belt guide anchor and seat belt device provided with the same |
-
1987
- 1987-12-18 JP JP32081987A patent/JPH01161848A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5780352A (en) * | 1995-10-23 | 1998-07-14 | Motorola, Inc. | Method of forming an isolation oxide for silicon-on-insulator technology |
| US5714414A (en) * | 1996-08-19 | 1998-02-03 | Micron Technology, Inc. | Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate |
| US5989980A (en) * | 1996-08-19 | 1999-11-23 | Micron Technology, Inc. | Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate |
| JP2008260463A (en) * | 2007-04-13 | 2008-10-30 | Takata Corp | Belt guide anchor and seat belt device provided with the same |
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