JPH01149428A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01149428A JPH01149428A JP30886987A JP30886987A JPH01149428A JP H01149428 A JPH01149428 A JP H01149428A JP 30886987 A JP30886987 A JP 30886987A JP 30886987 A JP30886987 A JP 30886987A JP H01149428 A JPH01149428 A JP H01149428A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thickness
- exceeding
- semiconductor device
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 abstract description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000002542 deteriorative effect Effects 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 230000000452 restraining effect Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000007747 plating Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＡｕＳｎ等のいわゆるハードソルダーにより素
子チップをマウントする構造で、しかもチップの裏面が
いわゆるＰ）Ｉｓ （プレーティラドヒートシンク）構
造である半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device having a structure in which an element chip is mounted using a so-called hard solder such as AuSn, and in which the back surface of the chip has a so-called P)Is (plate rad heat sink) structure. Regarding equipment.
従来、この種の半導体装置は第２図に示すようにＦＥＴ
等の動作部を形成したＧａＡｓ等の半導体層１の裏面に
スパッタによりＴｉ層２を形成し、これにメツキ法によ
り３０ｐ以上のＡｕ層３を形成した構造のものがある。Conventionally, this type of semiconductor device is an FET as shown in FIG.
There is a structure in which a Ti layer 2 is formed by sputtering on the back surface of a semiconductor layer 1 made of GaAs or the like on which an operating part is formed, and an Au layer 3 of 30 p or more is formed on this by a plating method.
上述した従来の構造ではＡｕＳｎ合金のいわゆるハード
ソルダーを用いてチップをマウントした場合、マウント
時の熱及びその後にチップに加わるボンディングあるい
は封着等の熱によりソルダー中に含まれるＳｎがチップ
裏面より拡散し熱伝導性の良いＡｕ層に替り、熱伝導性
の劣るＡｕＳｎ合金層が厚く形成され、又はこの形成が
進行し本来熱の良導性を目的としたＰＨ３構造の目的を
十分に発揮できないという欠点があった。In the conventional structure described above, when a chip is mounted using a so-called hard solder made of an AuSn alloy, the Sn contained in the solder diffuses from the back surface of the chip due to the heat during mounting and the heat applied to the chip afterwards during bonding or sealing. However, instead of the Au layer with good thermal conductivity, a thick AuSn alloy layer with poor thermal conductivity is formed, or this formation progresses, making it impossible to fully demonstrate the purpose of the PH3 structure, which was originally intended to have good thermal conductivity. There were drawbacks.
本発明の目的は前記問題点を解消した半導体装置を提供
することにある。An object of the present invention is to provide a semiconductor device that solves the above problems.
上述した従来の構造に対し、本発明はチップ裏面のＡｕ
層にソルダー材が拡散し、熱伝導性を劣化させることを
抑制するために、従来のチップ裏面構造を改良し、従来
のＴｉ −Ａｕ層を被うようにさらに５００Å以上のＴ
ｉ層とＡｕ層へのソルダー材の拡散を抑制するための１
０００Å以上のｐｔ層を付加し、さらにその上層に１０
００Å以上のＡｕ層を付加した構造としたことに相違点
を有する。In contrast to the conventional structure described above, the present invention
In order to suppress the diffusion of solder material into the layer and deterioration of thermal conductivity, we improved the conventional chip backside structure and added an additional layer of T of 500 Å or more to cover the conventional Ti-Au layer.
1 to suppress diffusion of solder material into the i-layer and the Au layer
Add a PT layer with a thickness of 000 Å or more, and then add a PT layer with a thickness of 10 Å or more on top of it.
The difference is that the structure has an added Au layer of 00 Å or more.
本発明は半導体チップの裏面に薄いＴｉ層と３０庫以上
の厚さのＡｕ層を積層し、さらに酸層を被覆してＴｉ、
Ｐｔ、Ａｕ層を各々５００Å、 １０００Å、 １０
００Å以上積層した構造を有することを特徴とする半導
体装置である。In the present invention, a thin Ti layer and an Au layer with a thickness of 30 cm or more are laminated on the back side of a semiconductor chip, and an acid layer is further coated to form a Ti layer.
Pt and Au layers are respectively 500 Å, 1000 Å, 10
The present invention is a semiconductor device characterized by having a structure in which layers are stacked with a thickness of 00 Å or more.
以下１本発明を図により説明する。The present invention will be explained below with reference to the drawings.
第１図において、本発明は、 ＦＥＴの動作部を上面に
形成したＧａＡｓ等の半導体層１の裏面に薄いＴｉ層２
と３０．以上の厚さのＡｕ層３を形成し、さらにこれを
被うように５００Å以上のＴｉ層４を被着することによ
り密着性を良くし、この上にＳｎの拡散を抑制する機能
をもたせるためにｐｔ層５を１０００Å以上形成し、さ
らにマウント面を安定にするためにＡｕ層６＠１０００
Å以上形成した構造を有するものである。In FIG. 1, the present invention includes a thin Ti layer 2 on the back side of a semiconductor layer 1 made of GaAs or the like on which the FET operating section is formed.
and 30. In order to improve adhesion by forming the Au layer 3 with the above thickness and further covering this with the Ti layer 4 with a thickness of 500 Å or more, and to have a function of suppressing the diffusion of Sn on this. A PT layer 5 with a thickness of 1000 Å or more is formed, and an Au layer 6@1000 Å is further formed to stabilize the mounting surface.
It has a structure formed with a thickness of Å or more.
第１図は本発明の一実施例を示す断面図、第３図は第１
図に示すチップをマウントした状態を示す断面図である
。FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view showing a mounted state of the chip shown in the figure.
図において、本実施例はＦＥＴの動作部を上面に形成し
たＧａＡｓ等の半導体層１の裏面にスパッタによりＴｉ
層２を５００人程変形成し、これを導電バスとしてＡｕ
メツキ層３を３０．程度形成する。さらにＡｕメツキ層
３を被うようにＴｉ層４を５００Å、ｐｔ層５を例えば
２０００人形成し、さらにＡｕ層６を２０００人形成す
る。In the figure, in this embodiment, Ti is sputtered on the back surface of a semiconductor layer 1 made of GaAs or the like on which the operating part of the FET is formed.
Layer 2 was deformed by about 500 layers, and this was used as a conductive bus to connect Au.
Plating layer 3 is 30. form a degree. Further, a Ti layer 4 with a thickness of 500 Å and a PT layer 5 of, for example, 2000 layers are formed to cover the Au plating layer 3, and an Au layer 6 of 2000 layers is further formed.
前記チップをマウントした状態が第３図である。FIG. 3 shows a state in which the chip is mounted.
第３図において、７はＡｕＳｎソルダー、８はＣｕステ
ムを示す。ここで、マウント、ボンディング、封着時の
３００〜３５０℃程度の組立工程時の加熱によりソルダ
ー７中に含まれるＳｎがＡｕ層６に拡散してもｐｔ層Ｓ
中における拡散は極めて遅いため、上層のＡｕメツキ層
３には及ばない。In FIG. 3, 7 indicates an AuSn solder and 8 indicates a Cu stem. Here, even if Sn contained in the solder 7 is diffused into the Au layer 6 due to heating during the assembly process of about 300 to 350°C during mounting, bonding, and sealing, the pt layer S
Diffusion inside is extremely slow and does not reach the upper Au plating layer 3.
従って、放熱性を目的とするＡｕメツキ層３の熱良導性
は前記加熱後も保持されることになる。Therefore, the thermal conductivity of the Au plating layer 3, which is intended for heat dissipation, is maintained even after the heating.
〔発明の効果Ｊ
以上説明したように本発明は半導体チップの裏面に薄い
Ｔｉ層と３０１！ｍ以上の厚さを有するＡｕ層を形成し
、さらにこれを被うようにＴｉｅ Ｐｔ、 Ａｕ層を各
々５００Å、 １０００Å、 １０００Å以上積層した
構造とすることにより、組立工程等の加熱工程において
、ＡｕＳｎ等のマウントソルダーが厚いＡｕ層まで拡散
し、熱伝導性を劣化されることを抑制できる効果がある
。[Effect of the Invention J As explained above, the present invention has a thin Ti layer on the back surface of the semiconductor chip and 301! By forming an Au layer with a thickness of 500 Å or more, and further stacking Tie Pt and Au layers of 500 Å, 1000 Å, and 1000 Å or more so as to cover this, AuSn can be formed in a heating process such as an assembly process. This has the effect of preventing the mount solder from diffusing into the thick Au layer and deteriorating the thermal conductivity.
第１図は本発明の一実施例を示す縦断面図、第２図は従
来例を示す縦断面図、第３図は本発明に係るチップをマ
ウントした状態を示す縦断面図である。FIG. 1 is a vertical cross-sectional view showing an embodiment of the present invention, FIG. 2 is a vertical cross-sectional view showing a conventional example, and FIG. 3 is a vertical cross-sectional view showing a state in which a chip according to the present invention is mounted.
Claims (1)
の厚さのＡｕ層を積層し、さらに該層を被覆してＴｉ、
Ｐｔ、Ａｕ層を各々５００Å、１０００Å、１０００Å
以上積層した構造を有することを特徴とする半導体装置
。(1) A thin Ti layer and an Au layer with a thickness of 30 μm or more are laminated on the back surface of a semiconductor chip, and this layer is further covered with Ti,
Pt and Au layers are 500 Å, 1000 Å, and 1000 Å, respectively.
A semiconductor device characterized by having a structure in which the above layers are stacked.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62308869A JPH0620082B2 (en) | 1987-12-07 | 1987-12-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62308869A JPH0620082B2 (en) | 1987-12-07 | 1987-12-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01149428A true JPH01149428A (en) | 1989-06-12 |
| JPH0620082B2 JPH0620082B2 (en) | 1994-03-16 |
Family
ID=17986238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62308869A Expired - Fee Related JPH0620082B2 (en) | 1987-12-07 | 1987-12-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0620082B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018073858A (en) * | 2016-10-24 | 2018-05-10 | 富士通株式会社 | Semiconductor device and semiconductor device manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5654047A (en) * | 1979-10-08 | 1981-05-13 | Nec Corp | Compound semiconductor device |
| JPS6156422A (en) * | 1984-08-28 | 1986-03-22 | Nec Corp | Semiconductor device |
| JPS61135130A (en) * | 1984-12-06 | 1986-06-23 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6220338A (en) * | 1985-07-19 | 1987-01-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1987
- 1987-12-07 JP JP62308869A patent/JPH0620082B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5654047A (en) * | 1979-10-08 | 1981-05-13 | Nec Corp | Compound semiconductor device |
| JPS6156422A (en) * | 1984-08-28 | 1986-03-22 | Nec Corp | Semiconductor device |
| JPS61135130A (en) * | 1984-12-06 | 1986-06-23 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6220338A (en) * | 1985-07-19 | 1987-01-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018073858A (en) * | 2016-10-24 | 2018-05-10 | 富士通株式会社 | Semiconductor device and semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0620082B2 (en) | 1994-03-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |