JPS60176244A - Adhesive part of semiconductor device - Google Patents
Adhesive part of semiconductor deviceInfo
- Publication number
- JPS60176244A JPS60176244A JP59032187A JP3218784A JPS60176244A JP S60176244 A JPS60176244 A JP S60176244A JP 59032187 A JP59032187 A JP 59032187A JP 3218784 A JP3218784 A JP 3218784A JP S60176244 A JPS60176244 A JP S60176244A
- Authority
- JP
- Japan
- Prior art keywords
- package
- melting point
- pellet
- intermediate layer
- low melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（力技術分野
この発明は、発光ダイオード、ホトダイオード、電界効
果トランジスタなどの半導体素子をパッケージにボンデ
ィングするための接着部品に関する。TECHNICAL FIELD This invention relates to an adhesive component for bonding semiconductor devices such as light emitting diodes, photodiodes, field effect transistors, etc. to packages.
ＧａＡｓ 、 ＧａＰ 、 ＩｎＰなどの化合物半導体
基板の上へ、発光ダイオード、ホトダイオード、電界効
果トランジスタなどが製作できる。これは、ウェハプロ
セスによって、多量に製造され、スクライプされて、個
々の素子（チップ）に分けられる。半導体素子のそれぞ
れは、パッケージに接着しなければならない。Light emitting diodes, photodiodes, field effect transistors, etc. can be manufactured on compound semiconductor substrates such as GaAs, GaP, and InP. This is manufactured in large quantities by a wafer process, scribed, and divided into individual elements (chips). Each semiconductor element must be adhered to a package.
シリコン半導体チップの場合は、ダイボンドすべきチッ
プ面に金メッキし、Ａｕ −Ｓｉ共晶合金によって、チ
ップをパッケージにダイボンディングする。In the case of a silicon semiconductor chip, the chip surface to be die-bonded is plated with gold, and the chip is die-bonded to the package using an Au-Si eutectic alloy.
ところが、ＧａＡｓなどの化合物半導体チップは、Ｇａ
Ａｓと直接共晶するはんだがないので、Ｇｏ −Ｓｎ共
晶合金を使って、予めＡｕを蒸着したチップ面をパッケ
ージに接着するようにしている。However, compound semiconductor chips such as GaAs
Since there is no solder that directly eutectics with As, a Go-Sn eutectic alloy is used to bond the chip surface on which Au has been deposited in advance to the package.
第３図は半導体素子（チップ）５を、パッケージ６に接
着した従来構造を示す断面図である。FIG. 3 is a sectional view showing a conventional structure in which a semiconductor element (chip) 5 is bonded to a package 6.
Ａｕ −Ｓｎの共晶合金を使うのは融点が低く、Ａｕと
なじみやすいからである。半導体素子の接着面、パッケ
ージの接着面には、予め金を蒸着しておく。これが、半
導体素子５の下部電＋１ｆｆｉ ９と、パッケージ６の
表面金膜７である。The reason for using the Au-Sn eutectic alloy is that it has a low melting point and is easily compatible with Au. Gold is vapor-deposited in advance on the adhesive surface of the semiconductor element and the adhesive surface of the package. These are the lower electrode +1ffi 9 of the semiconductor element 5 and the surface gold film 7 of the package 6.
Ａｕ −Ｓｎ共晶合金８は、箔状のものを型抜きして、
パッケージ６に置き、この上に半導体素子５を重ねて、
荷重を掛け、加熱する。Ａｕ −Ｓｎ共晶合金８が融け
て、下部電極９、表面金膜７と密着する。The Au-Sn eutectic alloy 8 was cut out from a foil,
Place it in a package 6, stack the semiconductor element 5 on top of it,
Apply a load and heat. The Au-Sn eutectic alloy 8 melts and comes into close contact with the lower electrode 9 and the surface gold film 7.
このように、Ａｕ −Ｓｎ共晶合金によって、接着して
いる。In this way, they are bonded by the Au-Sn eutectic alloy.
（イ）従来技術の問題点
（１） Ａｕ −Ｓｎ共晶合金は低融点合金と呼ばれる
が、融点は３２０℃であシ、半導体素子の耐熱性力ら考
えると、なお高温であシすぎる。(a) Problems with the prior art (1) Although the Au-Sn eutectic alloy is called a low melting point alloy, its melting point is only 320° C., which is still too high when considering the heat resistance of semiconductor elements.
特に熱に敏感な半導体素子の場合、ダイポンディング工
程のため、歩留シが著しく低下してしまう。Particularly in the case of semiconductor devices that are sensitive to heat, the die bonding process significantly reduces yield.
■）接着するため８５０℃程度に加熱する。加熱すると
Ａｕ −Ｓｎ共晶合金は全体が均一に溶融してしまい、
液状となる。素子には上方から加圧力がかかつているの
で、液状の合金が素子の周辺部へ浸み出してくる。第３
図は浸み出した合金が素子の側面を濡らした状態を示す
。合金は導電性があるので、フェイスダウン型の素子の
場合、四周へもれだ合金が電極間をショートさせてしま
う。こうなると、素子は全く機能しないので、これは不
良品となる。■) Heat to about 850°C for adhesion. When heated, the entire Au-Sn eutectic alloy melts uniformly,
It becomes liquid. Since pressure is applied to the element from above, the liquid alloy seeps out to the periphery of the element. Third
The figure shows the leached alloy wetting the sides of the device. Since the alloy is conductive, in the case of a face-down type element, the alloy leaking to the periphery will cause a short circuit between the electrodes. In this case, the element does not function at all, and thus becomes a defective product.
ここで、フェイスダウン型というのは、素子の動作層１
１（ｐｎ接合）と、これに付けた電極９をパッケージに
接着するものをいう。動作層１１、電極９は結晶基板部
に比して、極めて薄いから、合金が廻シこむと、これら
を容易にショートさせてしまう。Here, the face-down type refers to the active layer 1 of the element.
1 (pn junction) and the electrode 9 attached thereto are bonded to the package. Since the active layer 11 and the electrode 9 are extremely thin compared to the crystal substrate portion, they are easily short-circuited when the alloy is rotated.
ここでは、上部電極１３、半導体結晶１２が、下部電極
９と短絡しているものが図示されている。Here, the upper electrode 13 and the semiconductor crystal 12 are shown short-circuited to the lower electrode 9.
これは致命的なトラブルである。This is a fatal problem.
（つ）発明の目的
この発明の目的は、半導体素子をパッケージに接着する
際、
（１）半導体素子を劣化させないよう、より低い温度で
接着できる、
（２）接着のための部柑が流動状に融けて素子の側面に
まわシこむことがない、
ようにした接着部品を与えることである。(1) Purpose of the Invention The purpose of the present invention is to: (1) be able to bond at a lower temperature to prevent deterioration of the semiconductor device when bonding a semiconductor device to a package; The object of the present invention is to provide an adhesive part that does not melt and become stuck to the sides of the element.
に）構成
本発明は、Ａｕ −Ｓｎ共晶合金ではなく、Ａｕの中間
層と低融点金属の表面層とよシなる積層金属を用いる。B) Structure The present invention uses a laminated metal consisting of an intermediate layer of Au and a surface layer of a low melting point metal, rather than an Au-Sn eutectic alloy.
第１図は本発明の接着用積層金属ベレット１の断面図を
示す。FIG. 1 shows a cross-sectional view of a laminated metal pellet for adhesive use 1 of the present invention.
中間層２はＡｕで最も厚く、この画側をＳｎなどの低融
点金属の表面層３．４が覆って“いる。The intermediate layer 2 is made of Au and is the thickest, and the image side is covered with a surface layer 3.4 of a low melting point metal such as Sn.
これは、Ａｕ箔の両面に、Ｓｎの薄膜を伺加したもので
ある。たとえば、５０μｍｔのＡｕ リボンに、真空蒸
着法で、厚さ２μｍのＳｎの薄い層を両面に、同時に形
成する。This is a thin film of Sn added to both sides of the Au foil. For example, a thin layer of Sn with a thickness of 2 μm is simultaneously formed on both sides of a 50 μm thick Au ribbon by vacuum evaporation.
このように積層金属のリボンを作り、次に、過当な寸法
に型抜きしてベレット状とする。例えば、半径５００μ
ｍφの円板状に型抜きしベレットとする。A ribbon of laminated metal is produced in this way, and then die-cut to appropriate dimensions into a pellet shape. For example, radius 500μ
Die cut into a disc shape of mφ to make a pellet.
第１図に示すものは、型抜き後のベレットを表す。What is shown in FIG. 1 represents the pellet after die cutting.
第２図は、この接着用積層金属ベレット１を使って、パ
ッケージ６の上に半導体素子５を接着した状態を示す断
面図である。FIG. 2 is a cross-sectional view showing a semiconductor element 5 bonded onto a package 6 using the adhesive laminated metal pellet 1. As shown in FIG.
この半導体素子５は、ＧａＡｓの発光ダイオードチップ
の例で、フェイスダウン型の素子数イ」になっている。This semiconductor element 5 is an example of a GaAs light emitting diode chip, and is of a face-down type with a number of elements.
下から順に、下部″電極９、絶縁膜１０、動作層１１、
半導体結晶（基板）１２、上部電極１３よシなる。In order from the bottom, a lower electrode 9, an insulating film 10, an operating layer 11,
It consists of a semiconductor crystal (substrate) 12 and an upper electrode 13.
動作層１１は、ｐｎ接合を含むダブルへテロ接合となっ
ているが、詳しいことは省略する。The active layer 11 is a double heterojunction including a pn junction, but the details will be omitted.
上部電極１３はＡｕで、下部電極９はＴｉ ／ Ａｕよ
υなっている。The upper electrode 13 is made of Au, and the lower electrode 9 is made of Ti/Au.
一方、パッケージ６の表面は薄（Ａｕを利けておく。表
面金膜７によシ接着を容易にすることは従来と変わらな
い。On the other hand, the surface of the package 6 is thin (Au is used).The surface gold film 7 facilitates adhesion, which is the same as before.
このようなパッケージ６の表面金膜７の上に、接着用積
層金属ベレット１を置き、さらに半導体素子５を重ねる
。An adhesive laminated metal pellet 1 is placed on the surface gold film 7 of such a package 6, and the semiconductor element 5 is further stacked thereon.
素子５、パッケージ６の両側からベレット１を加熱し、
素子５には５ｇの荷重を加えた。Heating the pellet 1 from both sides of the element 5 and package 6,
A load of 5 g was applied to element 5.
そして、２３０℃の温度で、３０秒間ペレット１を保持
した。Then, pellet 1 was held at a temperature of 230° C. for 30 seconds.
この結果、Ｓｎが溶融し、素子５の下部電極９とベレッ
ト１の中間層２のＡｕと溶けあい、またパッケージ６の
表面金膜７と中間層２のＡｕとＳｎが溶けあって、これ
らが互に接着された。As a result, Sn is melted and mixed with the lower electrode 9 of the element 5 and the Au of the intermediate layer 2 of the pellet 1, and the gold film 7 on the surface of the package 6 and the Au and Sn of the intermediate layer 2 are melted. glued together.
０う作 用
接着用積層金属ベレット１の表面層３．４の薄いＳｎが
溶けて、これが上下に接触するＡｕと反応して合金を作
り、これにより、上下のＡｕ同士を接着、するわけであ
る。The thin Sn of the surface layer 3.4 of the adhesive laminated metal pellet 1 melts and reacts with the Au in contact with the top and bottom to form an alloy, thereby bonding the top and bottom Au to each other. be.
ベレット１の全体が融けるのではなく、薄いＳｎ層だけ
が融けて活性化する。融溶してＡｕと反応するＳｎの量
はＡｕに比して、充分少なくしであることから、合金化
するＡｕの部分は、電極９、Ａｕリボンの中間層２、パ
ッケージのＡｕ ７の極＜一部に限定され、Ａｕ −Ｓ
ｎベレット全体が溶けない。The entire pellet 1 is not melted, but only the thin Sn layer is melted and activated. Since the amount of Sn that melts and reacts with Au is sufficiently small compared to Au, the parts of Au to be alloyed are the electrode 9, the intermediate layer 2 of the Au ribbon, and the Au electrode 7 of the package. <Limited to some parts, Au-S
nThe entire pellet does not melt.
これが優れた特長である。This is an excellent feature.
Ｓｎの融点は２１７℃、Ａｕの融点は１０６２℃である
から、この間の温度で接着するようにすれば、Ｓｎだけ
融ける、という事は常に可能である。Since the melting point of Sn is 217° C. and the melting point of Au is 1062° C., it is always possible to melt only Sn by bonding at a temperature between these.
ψ）効 果
（１）べＶブト１の薄い表面層３．′４だけが溶融し、
Ａｕと合金化する。Ａｕは溶けず、ベレット１は殆ど変
形しない。このため、接着前の形状、特に素子５と、パ
ッケージ６の位置関係（間隔、平行度）が、接着後も殆
ど変わらず、精度良く維持できる。ψ) Effects (1) Thin surface layer of V-button 13. Only '4 melted,
Alloyed with Au. Au does not melt, and the pellet 1 hardly deforms. Therefore, the shape before bonding, especially the positional relationship (spacing, parallelism) between element 5 and package 6, hardly changes after bonding and can be maintained with high precision.
（２）従来のペレツ）（Ａｕ−Ｓｎ共晶合金）にみられ
た浸み出しが皆無である。このため、組立工程の歩留り
が向上した。(2) There is no seepage seen in conventional pellets (Au-Sn eutectic alloy). As a result, the yield of the assembly process has improved.
（３）接着後の構造としては、素子の下部電極９−ベレ
ット１の中間層（Ａｕ）２．パッケージ６の表面金膜７
の各界面の僅かな領域にのみＡｕ Ｓｎ合金が形成され
たものであるから、素子５とパッケージ６の間の電気抵
抗、熱抵抗の増加も（ｊめて少いものに抑えることがで
きる。(3) As for the structure after adhesion, the lower electrode 9 of the element - the intermediate layer (Au) of the pellet 1 2. Gold film 7 on the surface of the package 6
Since the AuSn alloy is formed only in a small area of each interface, increases in electrical resistance and thermal resistance between the element 5 and the package 6 can also be suppressed to a minimum.
従来使用されていたＡｕ Ｓｎ共晶合金の電気抵抗、熱
抵抗はＡｕの数倍から数十倍大きいからである。Ａｕ
Ｓｎ合金領域が狭く、Ａｕの部分が広いので抵抗は低い
。This is because the electrical resistance and thermal resistance of the conventionally used Au-Sn eutectic alloy are several times to several tens of times higher than those of Au. Au
Since the Sn alloy region is narrow and the Au portion is wide, the resistance is low.
（４）本発明では、Ｓｎがまず溶融して液状となシ、こ
れと接触する固体のＡｕと固液反応を生じて合金化する
。このため、Ｓｎの融点２１７℃を少し越える温度で接
着可能である。Ａｕ −Ｓｎ共晶合金の融点は約３２０
′Ｃであるから、本発明は、従来法よシも、約ｌＯＯ℃
低い温度で接着することができる。(4) In the present invention, Sn is first melted into a liquid state and then undergoes a solid-liquid reaction with solid Au that comes into contact with it to form an alloy. Therefore, bonding is possible at a temperature slightly exceeding the melting point of Sn, 217°C. The melting point of Au-Sn eutectic alloy is about 320
'C, the present invention can improve the temperature of about lOO℃ compared to the conventional method.
Can be bonded at low temperatures.
このため、ポンディング時の熱による半導体素子の劣化
を著しく低減できる。Therefore, deterioration of the semiconductor element due to heat during bonding can be significantly reduced.
（５）固液反応を利用することから、接着時の荷重を、
従来法の数分の一原子にすることができる。素子の機械
的劣化を防ぎ、接着工程での歩留シを大きく向上させる
ことができる。(5) Since solid-liquid reactions are used, the load during adhesion can be reduced by
The number of atoms can be reduced to a fraction of that of conventional methods. It is possible to prevent mechanical deterioration of the element and greatly improve yield in the bonding process.
（６）γイｆ状のＳｎは表面張力を有するので、第２図
に示すように半導体素子５の下部電極９に四部があって
も、Ｓｎけ凹部の中までまわり込み、空隙を残すことな
く、接着できる。(6) Since γ-f-shaped Sn has surface tension, even if the lower electrode 9 of the semiconductor element 5 has four parts as shown in FIG. It can be glued without any problem.
（Ａ−） その他の例
本発明は、Ａｕ箔を母材とし、この両側の面に少址の薄
い低融点金属の表１ｍ層３．４が形成されていればよい
。(A-) Other Examples In the present invention, it is sufficient that the base material is Au foil, and a thin layer 3.4 of a low melting point metal with a small thickness is formed on both sides of the base material.
低融点金属の例としては、Ｓｎのみに限定されるのでは
ない。Ｉｎ、Ｇｅもｈ」能で、これによシ表面層３．４
を形成しても良い。Examples of low melting point metals are not limited to Sn. In and Ge also have the ability to form a surface layer of 3.4
may be formed.
本発明は、発光ダイオード、レーザダイオード、ホトダ
イオード、ＦＥＴなどのチップのパッケージへの接着に
用いられる。Ａｕ中間層２、低融点金属表面層３．４の
厚みは、目的に応じて任怠に設定できる。The present invention is used for bonding chips such as light emitting diodes, laser diodes, photodiodes, FETs, etc. to packages. The thicknesses of the Au intermediate layer 2 and the low melting point metal surface layer 3.4 can be arbitrarily set depending on the purpose.
低融点金属は一般に酸化されやすい。低融点金属表面へ
さらに、５００八程度のＡｕ層を形成することで低融点
金属の酸化を冶効に防１にすることができる。この場合
、ベレットは、例えばＡｕ（０、０５７）ｍ）、５ｎ（
２μｍ） 、Ａｕ（５０１１ｍ） 、５ｎ（２μｍ）
、Ａｕ（ｒ）、ｏ５μｍ） の５層溝造となる。Low melting point metals are generally easily oxidized. By further forming an Au layer of about 500% on the surface of the low melting point metal, the oxidation of the low melting point metal can be effectively prevented. In this case, the pellet is, for example, Au(0,057)m), 5n(
2μm), Au (5011m), 5n (2μm)
, Au(r), o5μm).
第１図は本発明の半導体装置の接着部品のベレット状に
したものの断面図。
第２図は半導体素子をパッケージ゛に接着部品を用いて
接着したものの断面図。
第３図は従来例にかかるＡｕ −Ｓｎ共晶合金で素子を
パッケージに接着した構造の断面図。
１ ・・・・・・・・接着用積層金属ベレット２・・・
・・・・・ベレットの中間層
３．４・・・・ベレットの表面層
５・・・・・・・・半導体素子
６・・・・・・・・パッケージ
７・・・・・・・・パッケージ表面金膜８・・・・・・
・・Ａｕ −Ｓｎ共晶合金９・・・・・・・・下部電極
１０・・・・・・絶縁膜
１１・・・・・・動作層
１２・・・・・・半導体結晶
１３・・・・・・上部７Ｌ極
発明者 江 畑 敏 樹
特に１出願人 住友電気工業株式会社
第１図
第２図
１FIG. 1 is a sectional view of a bullet-shaped adhesive component of a semiconductor device according to the present invention. FIG. 2 is a cross-sectional view of a semiconductor element bonded to a package using adhesive parts. FIG. 3 is a cross-sectional view of a conventional structure in which an element is bonded to a package using an Au-Sn eutectic alloy. 1... Laminated metal pellet for adhesive 2...
...Bellet intermediate layer 3.4 ...Bellet surface layer 5 ...Semiconductor element 6 ...Package 7 ...... Package surface gold film 8...
...Au-Sn eutectic alloy 9...Lower electrode 10...Insulating film 11...Active layer 12...Semiconductor crystal 13... ... Upper 7L pole Inventor Toshiki Ebata Particularly Applicant 1 Sumitomo Electric Industries, Ltd. Figure 1 Figure 2 Figure 1
Claims (3)
ジ６のＡｕを含む表面金膜７とを接着するだめの部品で
あって、Ａｕよシなる中間層２の両側に薄い低融点金属
の表面層３．４を形成しであることを特徴とする半導体
装置の接着部品。(1) #- A component for bonding the Au-containing electrode 9 of the conductor element 5 and the Au-containing surface gold film 7 of the package 6, and is a thin low-melting point part on both sides of the intermediate layer 2 made of Au. An adhesive component for a semiconductor device, characterized in that a metal surface layer 3.4 is formed.
る特許請求の範囲第（１）項記載の半導体装置の接着部
品。(2) An adhesive component for a semiconductor device according to claim (1), wherein the low melting point metal is Sn, In, or Ge.
覆われている特許請求の範囲第（１）項又は第（２）項
記載の半導体装置の接着部品。(3) An adhesive component for a semiconductor device according to claim (1) or (2), wherein the surface of the low melting point metal is covered with Au with a thickness of 500 Å or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59032187A JPH0636417B2 (en) | 1984-02-22 | 1984-02-22 | Adhesive parts for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59032187A JPH0636417B2 (en) | 1984-02-22 | 1984-02-22 | Adhesive parts for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60176244A true JPS60176244A (en) | 1985-09-10 |
| JPH0636417B2 JPH0636417B2 (en) | 1994-05-11 |
Family
ID=12351904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59032187A Expired - Lifetime JPH0636417B2 (en) | 1984-02-22 | 1984-02-22 | Adhesive parts for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0636417B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03230552A (en) * | 1990-02-05 | 1991-10-14 | Matsushita Electric Ind Co Ltd | Joint material for packaging semiconductor device |
| JPH07147292A (en) * | 1993-11-25 | 1995-06-06 | Nec Corp | Manufacture of semiconductor device |
| JPH08264765A (en) * | 1995-03-27 | 1996-10-11 | Hitachi Ltd | Power chip carrier and power semiconductor device using the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5450269A (en) * | 1977-09-28 | 1979-04-20 | Nec Home Electronics Ltd | Semiconductor device |
| JPS54150988A (en) * | 1978-05-19 | 1979-11-27 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5858786A (en) * | 1981-10-05 | 1983-04-07 | Hitachi Ltd | Mounting structure of compound semiconductor element |
-
1984
- 1984-02-22 JP JP59032187A patent/JPH0636417B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5450269A (en) * | 1977-09-28 | 1979-04-20 | Nec Home Electronics Ltd | Semiconductor device |
| JPS54150988A (en) * | 1978-05-19 | 1979-11-27 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5858786A (en) * | 1981-10-05 | 1983-04-07 | Hitachi Ltd | Mounting structure of compound semiconductor element |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03230552A (en) * | 1990-02-05 | 1991-10-14 | Matsushita Electric Ind Co Ltd | Joint material for packaging semiconductor device |
| JPH07147292A (en) * | 1993-11-25 | 1995-06-06 | Nec Corp | Manufacture of semiconductor device |
| JPH08264765A (en) * | 1995-03-27 | 1996-10-11 | Hitachi Ltd | Power chip carrier and power semiconductor device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0636417B2 (en) | 1994-05-11 |
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